JPH0630429B2 - Limit amplifier - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a limit amplifier for waveform shaping of a timing extraction clock signal of a digital communication repeater.

[Background of the Invention]

In digital transmission for regenerative repeat transmission, a clock signal is extracted from the main symbol for each repeater, and the main signal is identified and reproduced by this signal. In this case, the amplitude of the clock signal changes by 20 to 30 dB depending on the pattern of the main signal.
For stable identification and reproduction of the main signal, it is necessary to shape the waveform into a rectangular wave signal with a constant amplitude and a small phase fluctuation.
A limit amplifier is generally used as this waveform shaping circuit.

When limiting the amplitude of a clock signal whose amplitude fluctuates significantly, the limit amplifier causes the amplitude-phase conversion because the junction capacitance of the transistor varies nonlinearly depending on the input signal level, and the clock output signal has a phase difference. Fluctuation (jitter) occurs. In the low frequency range of the jitter, it is necessary to reduce the junction capacitance of the transistor, and it is effective to widen the band of the limit amplifier. FIG. 1 shows the circuit configuration of a conventional amplifier (Linear IC data book, manufactured by Fairchild, page 7-40 μA733). The operation will be briefly described. First, a signal is input from the terminal V _{IN IN} , and the current distribution rate flowing through the transistors Q ₁ and Q ₂ changes according to this signal. This change appears as a voltage change across the load resistors R _L1 and R _L2 . This circuit realizes a wide band by adopting a negative feedback configuration with a resistor R _F. However, the transistor _Q 1, the collector potential _V 1 of the _{Q 2, V 2} are each _V 1 V _CC when the potential difference between V _IN and _IN is maximized at the time of large input _{amplitude, V 2 = V CC -R L2} 2 becomes , The transistors Q ₃ and Q ₄ are saturated. Due to this saturation, the balance of charge and discharge of Q ₃ and Q ₄ is disturbed, and there is a drawback that the jitter characteristic is deteriorated.

[Object of the Invention]

SUMMARY OF THE INVENTION In view of the conventional drawbacks, an object of the present invention is to provide a limit amplifier for limiting the amplitude of a clock signal, which avoids the saturation of the transistors constituting the negative feedback differential amplifier and lowers the jitter generated by the amplitude-phase conversion. To do.

[Outline of Invention]

As a first method for realizing the above object of the present invention, R
_A level shift diode is provided between _L1 and V _CC , and due to the voltage drop of this diode, transistors Q ₃ and Q ₄
To operate in a non-saturated state. The second method is V ₁ ,
Since the level of V ₃ is determined by the resistance ratio between V _CC and the potential of ₀ and V ₀ , saturation is eliminated by lowering the levels of ₀ and V ₀ . Actually Q ₅ and Q ₆ , Emitter and R _F
It is realized by inserting an n-stage level shift diode between the two.

Example of Invention

 Hereinafter, the present invention will be described in detail with reference to Examples.

FIG. 2 shows the basic unit circuit configuration of the limit amplifier according to the first embodiment of the present invention. In this embodiment, the resistors R _L1 , R
_L2 , R _E1 , R _F and transistors Q ₁ , Q ₂ , Q ₃ , Q
_This is a circuit configuration in which a diode D ₁ is added to the limit amplifier of FIG. 1 composed of ₄ , Q ₅ , and Q ₆ .

V ₀ , ₀ of the limit amplifier 2 shown in FIG. 2 is a differential output, and a waveform whose amplitude is limited in a non-linear region is output. In the circuit shown in FIG. 2, Q ₃ and Q ₄ are most severe in terms of saturation when the potential difference between the differential inputs V _IN and _IN is the largest, and considering the voltage drop v _BE of the diode D ₁ , _V 3, _{V 4} at this time, respectively, it becomes _{V 3 = V CC -v bE ...} (1) V 4 V CC -R L2 · I 2 ... (2).

For example, if R _L1 = R _L2 = 800Ω RE 1 = 100Ω R _F 3 kΩ I ₁ = I ₂ = I ₃ = I ₄ = 1 mA, the saturation current I _{S of the} transistor is generally ^Therefore , I ₀ = 10 ⁻¹⁶ (A), β = 26 × 10
When ^-3 (V), at about _{v BC = 0.65V, I s =} 0.07mA
Becomes Since this value is 7% of I ₂ = 1 mA, it cannot be ignored. In the configuration of FIG. 1, V _BE = 0.85V (1mA) is V ₃ from the collector current-base-collector voltage characteristic.
_{-V 4 = R L2 · I 2} = severely made, but relative to the 0.8V becomes saturated, according to the present invention, (1), (2) from _equation, V 3 -V
₄ = RR _L2 · I ₂ −v _BE = 0.8V−0.85V = −0.05V, satisfying V ₃ <V ₄ and no saturation occurs.

FIG. 3 shows another embodiment of the present invention. This embodiment is the first
This is a circuit in which n stages of level shifting diodes Q _{1 to} Q _n are added to the limit amplifier shown in the figure. The transistor Q ₃ is the most severe with respect to saturation in the circuit shown in Figure 3, when the largest potential difference of the differential input V _IN and _IN, this _{time, V 7 = V CC -R L2} · I 2 ... ( 3) Since V ₆ becomes the resistance ratio of V _CC and V ₀ , Becomes

In order to prevent Q _{3 from} being saturated, the relationship of V ₆ <V ₇ should be established. If the same circuit constants as in the first embodiment are used, from the above equations (3) and (4), V ₆ <V ₇ at n = 4,
The same effect as that of the first embodiment can be obtained.

FIG. 4 shows the simulation effect of the input amplitude jitter characteristic in the conventional limit amplifier in which four basic unit circuits are connected in cascade and in the limit amplifier according to the present invention. Clock frequency 150 MHz, transistor _T = 4 GHz, base resistance 600 Ω, base-collector capacitance 0.082 pF,
The base-emitter capacitance was 0.063 pF and the collector-substrate capacitance was 0.21 pF. Input is normally used 0.8V
_{As a pp} reference, the jitter was measured up to 50 mV _pp, which corresponds to a mark rate fluctuation of 1/15. As shown in FIG.
According to the limit amplifier of the present invention, the vegeta characteristic can be improved to about 1/6 as compared with the conventional limit amplifier.

〔The invention's effect〕

According to the invention, a level shifting diode or n
By adding cascaded diodes in stages,
Since it is possible to avoid saturation of the transistors forming the differential amplifier for negative feedback, the jitter can be lowered and a wideband limit amplifier can be realized.

[Brief description of drawings]

FIG. 1 is a contradictive feedback type limit amplifier circuit diagram, FIG. 2 is a first limit amplifier circuit diagram of the present invention, FIG. 3 is a second limit amplifier circuit diagram of the present invention, and FIG. 4 is a conventional type. FIG. 6 is a jitter characteristic diagram of the limit amplifier and the limit amplifier of the present invention. 2 ... 1st non-saturation limit amplifier basic unit circuit, 3 ... 2nd non-saturation limit amplifier basic unit circuit.

Claims (2)

[Claims] 1. A first differential amplifier comprising a pair of transistors, each collector having a load resistance, and each emitter connected to a first constant current source through a resistance element, and each collector. Has a load resistance and the emitter is the second
Second differential amplifier comprising a pair of transistors commonly connected to the constant current source, each base connected to the collector output of the first differential amplifier, and each base having the second difference. A pair of emitter follower circuits connected to the collector output of the dynamic amplifier and having their emitters connected to the base of the second differential amplifier via a feedback resistance element. A limit amplifier characterized in that the other end is commonly connected and is connected to a power supply terminal via a diode. 2. A first differential amplifier comprising a pair of transistors, each collector having a load resistance, and each emitter connected to a first constant current source via a resistance element, and each collector. Has a load resistance and the emitter is the second
Second differential amplifier comprising a pair of transistors commonly connected to the constant current source, each base connected to the collector output of the first differential amplifier, and each base having the second difference. A pair of emitter follower circuits connected to the collector output of the dynamic amplifier and having emitters connected to the bases of the second differential amplifiers via feedback resistance elements, wherein each of the emitter follower circuits comprises an emitter and a feedback resistor. A limit amplifier characterized in that it has a plurality of diodes connected in series between and.