JPH0632220B2 - Sense amplifier for semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sense amplifier of a semiconductor memory device, and more particularly to detecting a change in an input address of the memory device inside a chip and generating an internal synchronizing signal in response to the change. The present invention relates to a sense amplifier of a semiconductor memory device using an internal synchronization circuit system.

[Conventional technology]

Conventionally, this type of device has been shown in FIG.
FIG. 2 shows a sense amplifier used in a CMOS static RAM. In the figure, Q1, Q4 and Q7 are P
Channel MOS field effect transistor (hereinafter p-chMO
SFET), Q2, Q3, Q5, Q6 and Q8 are n-channel MOS type field effect transistors (hereinafter n-ch MOSFETs).
Vcc is a power supply potential and GND is a ground potential.

In addition, 1 is the above MOSFET Q1, Q2, Q3, Q4, Q5, Q
It is a current mirror type differential amplifier circuit configured by 6, and receives two inputs by MOSFETs Q2 and Q5, detects and amplifies the difference, and outputs one output. 2 is MOSFET Q7, Q
8 is an inverter. I / O,
▲ ▼ is the input of the differential amplifier circuit 1, SA1 is the output of the first stage current mirror type differential amplifier circuit 1, and ▼ is 2
It is the output of the inverter 2 of the stage and is usually connected to the output buffer. SE2 is an input for power cut of the first-stage current mirror type differential amplifier circuit 1. The high level activates the current mirror type differential amplifier circuit 1 and the low level cuts the power.

Next, the operation will be described.

FIG. 4 shows the timing of the sensing operation. Now, when the power cut input SE2 of the differential amplifier circuit 1 is set to high, a potential difference is generated between the I / O line and the line ▼ depending on the selected memory cell. This potential difference is detected by the first-stage current mirror type differential amplifier circuit 1 performing a sensing operation,
As a result, as shown in FIG. 4, the differential amplifier circuit output SA1
Changes. When the output SA1 reaches the threshold voltage of the second stage inverter 2, the inverter output ▲ ▼
Changes to complete the sensing operation.

[Problems to be solved by the invention]

Since the sense amplifier of the conventional semiconductor memory device is configured as described above and the slope of the differential amplifier circuit output SA1 of the first stage is gentle, the differential amplifier circuit output SA1 changes as shown in FIG. The delay from the start to the threshold of the second stage inverter (the period A in FIG. 4) is large,
Moreover, since the change in the inverter output (1) is also delayed as in the period B in FIG. 4, it hinders the high-speed read operation of the RAM.

The present invention has been made in order to eliminate the above-mentioned drawbacks of the conventional one, and eliminates the delay from the start of the change of the differential amplifier circuit output SA1 to the start of the change of the inverter output RD, thereby realizing a high-speed RAM. An object of the present invention is to provide a sense amplifier for a semiconductor memory device that enables a read operation.

[Means for solving problems]

The sense amplifier of the semiconductor memory device according to the present invention is the first
And a second input node for amplifying a potential difference between the potential applied to the first input node and the potential applied to the second input node, and outputting the amplified difference to the output node. Means, the power supply potential node and the ground potential node, and the input node is directly connected to the output node of the differential amplifying means to output a potential according to the potential appearing at the output node of the differential amplifying means. An inverter for outputting to the node and a potential that is connected between the input node and the output node of the inverter and that is applied to the power supply potential node at the input and output nodes and the output node of the differential amplifying means. And a short-circuiting transistor for setting a potential between that and the potential applied to the ground potential node.

[Operation] In the present invention, since the short-circuiting transistor conducts between the input and output of the inverter, the potential of the input node and the output node of the inverter becomes an intermediate potential between the power supply potential and the ground potential, and moreover, the input of the inverter. Since the node and the output node of the differential amplifying means are directly connected, the output node of this differential amplifying means also has the intermediate potential. By setting the potential of the input node of the inverter to the intermediate potential, the potential of the output node of the inverter changes greatly even if the potential of the input node of the inverter slightly changes. Further, since the output node of the differential amplifying means is set to the intermediate potential, as soon as the short-circuiting transistor becomes non-conductive, the differential amplifying means immediately outputs its output according to the potential difference appearing at the first and second input nodes. Increases or decreases the potential of the node.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a sense amplifier of a semiconductor memory device according to an embodiment of the present invention. This embodiment device is similar to the conventional device shown in FIG. 2 except that n-ch MOSFETs (short-circuiting transistors) Q10, p are added.
A -ch MOSFET Q9 is added. And this n-
The chMOSFET Q10 is for short-circuiting the input and output of the second-stage inverter 2 in the read period, and its gate is connected to the terminal SE1. The terminal SE1 is high and the second-stage inverter 2 is input, Short the output and open low. The p-ch MOSFET Q9 is the second inverter 2
For eliminating the through current of the gate of the gate of the gate terminal SE2.

Here, in FIG. 1, I / O = non-reading period =
The differential amplifier circuit so that the output voltage of the current mirror type differential amplifier circuit 1 at the time of ▲ ▼ is the same as the threshold voltage of the inverter 2 (the input / output voltage when the input and the output are short-circuited). The circuit constant of 1 is set.

Next, the operation will be described. FIG. 3 shows the timing of the sensing operation. While both terminals SE1 and SE2 are low,
The current mirror type differential amplifier circuit 1 of the first stage is power cut, and the input of the inverter 2 of the second stage is MOSF.
Since it is clamped to Vcc by ETQ9, no through current flows through the inverter 2 at this time.

Next, the terminals SE1 and SE2 are both raised to high by the first internal synchronization signal generated by detecting the change in the input address signal of the memory device by the internal synchronization signal generation circuit inside the chip. Then, the first-stage current mirror type differential amplifier circuit 1 is activated, and at the same time, the input / output of the second-stage inverter 2 is short-circuited by the transistor Q10 and the node SA
1 becomes an intermediate potential by precharging or discharging.

The reason why the input and output of the inverter 2 are short-circuited to the intermediate potential will be explained below.
In the CMOS inverter composed of the -ch MOSFET Q11 and the p-ch MOSFET Q12, its input / output characteristic is the sixth.
It becomes as shown by the solid line in the figure. If the input and output are short-circuited here, since VIN = VOUT, the input and output terminals VIN and VOUT of the inverter have the values at the intersections of the solid line and the alternate long and short dash line in FIG.

Next, when there is a slight difference in the I / O and ▲ ▼ lines,
The terminal SE1 is set to low by the second internal synchronization signal generated by the internal synchronization signal generation circuit. Then, the current mirror type differential amplifier circuit 1 starts sensing, and the potential of the node SA1 thereof starts to change from the intermediate potential. And
Since the output node of the differential amplifier circuit 1 and the input node of the inverter 2 are directly connected, the change in the potential of the output node of the differential amplifier circuit 1 directly changes the input node of the inverter 2 and this inverter In response to this slight change in potential, 2 greatly changes the inverter output ▲ ▼, and the sensing operation is completed. After the completion of this sensing operation, the power is cut to the differential amplifier circuit 1 when the terminal SE2 is made low by the third internal synchronization signal created by the internal synchronization signal creation circuit.

As described above, according to the device of this embodiment, it is possible to significantly speed up the sensing operation as compared with the conventional example, and by using this device, it is possible to provide a memory device capable of high-speed reading.

In the above embodiment, the two-stage configuration of the current mirror type differential amplifier circuit and the CMOS inverter has been described, but the first stage may not be the current mirror type, and the second stage may not be the CMOS inverter. , NMOS E-
It may be an inverter having an E configuration or an E-D configuration, and has the same effect as that of the above embodiment.

〔The invention's effect〕

As described above, in the sense amplifier of the semiconductor memory device according to the present invention, the output node of the differential amplifier is directly connected to the input node of the inverter, and the short-circuit transistor for short-circuiting the input node and the output node of the inverter is provided. The potential of the input node and the output node of the inverter and the potential of the output node of the differential amplifier are set to an intermediate potential between the power supply potential and the ground potential by the short-circuit transistor before the input potential is applied to the differential amplifying means. Then, by making the short-circuiting transistor non-conductive, the differential amplifying means immediately raises or lowers the potential of the output node from the intermediate potential in accordance with the potential difference between the first and second input nodes. The potential of the output node is immediately transmitted to the input node of the inverter, and the potential of the input node of the inverter changes slightly from the intermediate potential. Only the potential of the output node of the inverter is greatly changed with. As a result, there is an effect that the speed of the differential amplifying means and the speed of the inverter can be increased, and the speed of the output of the inverter with respect to the input potential can be increased.

[Brief description of drawings]

1 is a circuit diagram of a sense amplifier of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional sense amplifier, FIG. 3 is an operation timing diagram of the sense amplifier of FIG. 1, and FIG. The figure shows the operation riming diagram of the conventional sense amplifier,
FIG. 5 is a circuit diagram of a CMOS inverter, and FIG. 6 is a CMO.
It is an input / output characteristic view of an S inverter. DESCRIPTION OF SYMBOLS 1 ... Current mirror type sense amplifier (sense amplifier main body), 2 ... CMOS inverter, Q10 ... Field effect transistor for short circuit, Q9 ... Field effect transistor for removal of through current. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (4)

[Claims] 1. A first input node and a second input node, amplifying a potential difference between a potential applied to the first input node and a potential applied to the second input node. An output node of the differential amplifying means, which is connected between the power supply potential node and the ground potential node, and whose input node is directly connected to the output node of the differential amplifying means. An inverter for outputting a potential corresponding to the potential appearing at the node to the output node, and an inverter connected between the input node and the output node of the inverter, and having the input and output nodes and the output node of the differential amplifying means. A semiconductor memory including a short-circuiting transistor for setting a potential between a potential applied to the power supply potential node and a potential applied to a ground potential node. The sense amplifier of the location. 2. A first MO transistor having a drain electrode connected to an output node of the differential amplifier means and a gate electrode connected to a first input node of the differential amplifier means.
An S-type field effect transistor and a second MO field-effect transistor which forms a differential pair with the first MOS-type field effect transistor and has a gate electrode connected to the second input node of the differential amplifying means.
The sense amplifier of the semiconductor memory device according to claim 1, further comprising an S-type field effect transistor. 3. A differential amplifying means is a p-channel MOS field effect transistor connected between a power supply potential node and an output node of the differential amplifying means, and between the power supply potential node and a first node. P-channel MOS connected to
N-channel MOS having a drain electrode connected to the output node of the differential amplifying means and a gate electrode connected to the first input node of the differential amplifying means. Type field effect transistor and an n-channel MOS type field effect transistor whose drain electrode is connected to the first node and whose gate electrode is connected to the second input node of the differential amplifying means. , A p-channel MOS field effect transistor connected between the power supply potential node and the output node of the inverter and having its gate electrode directly connected to the output node of the differential amplifying means, and the output node of the inverter and the ground potential. N connected to the node, and the gate electrode of which is directly connected to the output node of the differential amplifying means.
7. A sense amplifier for a semiconductor memory device according to claim 1, further comprising a channel MOS field effect transistor. 4. The differential amplifying means is the first differential amplifying means.
When the potential applied to the input node of the differential amplifier is the same as the potential applied to the second node of the differential amplifier, the potential output to the output node of the differential amplifier and the threshold value of the inverter. The sense amplifier of a semiconductor memory device according to any one of claims 1 to 3, wherein the circuit constant of the differential amplifying means is set so that the voltages become equal to each other.