JPH0632221B2 - Memory circuit - Google Patents

Description

The present invention relates to a semiconductor memory circuit, and more particularly to a bit line pull-up circuit for SRAM using MES FET.

[Conventional technology]

In a semiconductor device using gallium arsenide (GaAs) for a semiconductor substrate, it is difficult to form a MOS (Metal Oxide Semi conductor) type FET (field effect transistor). Therefore, a junction type or a Schottky barrier type MES (Metal Sem) is used.
i-conductor) type FET is used. There are PN junction type and heterojunction type in this junction type, and the latter part is HE
It is called MT (High Electron Mobility Transistor), and the operating principle is different, but in this case, these are simply MES.
It is called FET.

SRAM (Static Ramdom Acce) using MES FET
ss Memory) has the configuration shown in FIG. Q _{1 to} Q ₄ are MES FETs forming flip-flops, Q ₅ and Q ₆
Is a MES FET for transfer gate, and these 6 transistors form one memory cell MC.
B1 and B2 are a pair of bit lines that control the input / output of memory cell data. W is a word line, which opens and closes the transfer gate transistors Q ₅ and Q ₆ . There are many such bit line pairs and word lines in a memory, and a memory cell MC is connected to each intersection thereof. In this memory, the word line W is selected and becomes the H level, and the transistor Q ₅ ,
When the Q ₆ is turned on, and the transistor _{Q 1} is turned on in the memory cell MC, and when _{Q 2} is turned off, B1 of the transistors _Q 7, the bit lines are pulled up to the power supply V _DD through _{Q 8} B1, B2 are The potential is lowered because it is pulled down to the ground through the gate Q ₅ and the transistor Q ₁ , and the potential is not lowered because B ₂ does not have the pull-down through Q ₆ and Q ₂ , thus the potential difference between B 1 and B 2 occurs and the cell storage data Read-out is performed.

In this way, the SRAM using the MES FET also has a MOS
Same operation as SRAM using FET, but M
In the ES FET, the gate is a diode and the MOS F
There is a slight difference in that it is not insulating like ET. For example above, _Q 6 from the bit line B2, _{Q 2}
Although there is no current to the ground through the gates of Q _{6 and} Q ₁ , there is a current to the ground through the gates of Q _{6 and} Q ₁ , so that the potential of the bit line B 2 becomes the built-in voltage (about 0.7V) of the gate of the MES FET. Limited. M whose gate is insulating
This is not the case with memories that use OS FETs.

[Problems to be solved by the invention]

When the transistor Q ₁ is turned on and Q ₂ is turned off, the current from the bit line B ₁ flows to the ground through the transistors Q ₅ and Q ₁ , and the drain voltage of the transistor Q ₁ is 0.
Since it drops to about 1 V, the gate current of the transistor Q ₂ does not flow. But transistors Q _5, Q 1 and a high potential of the bit line _B1, current ground path becomes large, the gate current of the transistor Q ₂ flows up the drain voltage of the transistor Q ₁ is, the transistor Q ₂ May turn on. Further, the transistors Q ₆ and Q
The current of the gate and ground path of ₁ also becomes large when the potential of the bit line B2 is high, and the gate of the transistor Q ₁ may be burned out. As described above, since the gate current flows in the MES FET, it is necessary to suppress the bit line potential to an appropriate value. If it is too high, there are problems such as gate burnout and stored data destruction.

As the pull-up circuit, instead of using the illustrated depletion MES FETs Q ₇ and Q ₆ for shorting the gate and the source, an enhancement MES for shorting the drain and the gate is used.
Some use FETs. The former is a constant current type,
The latter is a constant voltage source type (having the same characteristics as a diode). In any case, there is a problem in properly setting the bit line potential to a desired value. That is, in the former, the potential fluctuates (when the bit line current is small, the bit line potential rises up to the power supply V _DD ), and in the latter, a constant voltage drop is caused while a current of a constant value or more is flown. It is necessary to set the bit line power supply voltage itself to a desired value so as to obtain the bit line potential, and thus to use a bit line pull-up power supply different from the cell power supply.

It is preferable that the bit line potential of the SRAM using the MES FET is at most about the built-in voltage from the viewpoint of blocking the above gate current, and if the bit line is connected to the ground with a transistor because it is necessary to read and write, the potential is 0V ( The pull-up circuit is required to have such a function. The present invention is intended to provide a bit line pull-up circuit having such a function.

[Means for solving problems]

The present invention relates to a semiconductor memory circuit including a memory cell including a flip-flop composed of an MES FET and a transfer gate connecting a pair of input / output terminals of the flip-flop to a pair of bit lines, and the pair of bit lines is supplied with power. A depletion type MES FET having a gate and a source short-circuited,
It is characterized in that it is composed of a diode connected between the gate of the FET and the ground with the anode on the gate side.

[Operation and Example]

In the present invention, as shown in FIG. 1, the gates of the depletion type MES FETs Q ₇ and Q _{8 with} the gate and the source short-circuited are connected to the ground through the diodes D ₁ and D ₂ having the polarities shown. By doing so, the potentials of the bit lines B1 and B2 are limited to the forward voltage (0.6 to 0.7 V) of the diode and do not rise further. When the word line W becomes H level and the transistors Q ₅ and Q ₆ are turned on and the memory cell MC is selected, if the transistor Q ₁ is turned on and Q ₂ is turned off in this memory cell, the bit line B ₁ is turned on. Is Q ₅ ,
It is dropped to the ground through the path of Q ₁ , and the voltage of the transistor Q ₇ drops to 0V (actually about 0.1V) on the bit line. Keeping the non-selection level of 0.6~0.7V since no pull-down due to the bit line B2 in _Q 6, _{Q 2.}

FIG. 2 is a diagram showing this in the ground. C1 shows the potential change of B2 in this example of the non-selected side bit line, and C2 shows the potential change of B1 in this example of the selected side bit line. In this figure, the vertical axis represents the bit line potential and the horizontal axis represents the word line potential. Since the word line driver is also composed of MES FETs, the selected H level is about the built-in voltage, which is 0.5 V in this example, and the non-selected L level.
The level is 0-0.1V. Here's a numerical example:
Enhancement (E) type MES FET Q ₁ , Q ₂ ,
The threshold voltage Vth of Q ₅ and Q ₆ is + 0.1V ± 0.05V, and the depletion (D) type MES FETs Q ₃ , Q ₄ and Q ₇ ,
Vth of Q ₈ is -0.5V ± 0.1V, the voltage of the power supply V _DD is 2V. Diodes D ₁ and D ₂ are transistors Q ₁ and Q ₂
If the diode of the gate is a junction type, it may be a junction type, and if it is a Schottky barrier type, it may be a Schottky barrier type.

As shown in FIG. 3, the sense amplifier of the SRAM using the MES FET has E-type MES FETs Q ₁₁ and Q ₁₂ , a gate-source shorted D-type MES FET Q ₁₃ and a resistor R ₁ .
It is composed of a differential amplifier composed of R ₂ . The positive power supply V _DD of this amplifier is also 2V and the negative power supply V _ss is -1V. If this sense amplifier is composed of two ED type inverters as shown in FIG. 4, the diodes D ₁ and D ₂ of the bit line pull-up circuit become unnecessary. In this FIG. 4, Q ₁₄ ,
Q ₁₅ is an E-type MES FET, Q ₁₆ and Q ₁₇ are gate-source short-circuited D-type MES FETs, and Q ₁₆ and Q
₁₇ and Q ₁₄ , Q ₁₅ are respectively connected in series to form two E-D inverters. In this type of sense amplifier, the gates and sources of the driver transistors Q ₁₄ and Q ₁₅ are diodes that connect the bit line to the ground, and therefore the diodes D ₁ and D ₂ are not necessary. Since it is not necessary to provide the constant current source transistor Q ₁₃ as in FIG. 3, it is not necessary to provide the negative power source V _ss, and the sources of the driver transistors Q ₁₄ and Q ₁₅ can be simply connected to the ground. Only the transistors Q ₁₄ and Q ₁₅
Since the gate of (2) always passes current, it must be large enough to withstand this energization. Unlike the memory cell, the sense amplifier is provided only for each bit line pair and therefore for each column, so that even if the size is increased slightly, the degree of integration is not so serious.

〔The invention's effect〕

As described above, according to the present invention, it is possible to prevent the gate from being burned and the stored data from being destroyed due to the excessive potential of the bit line by an extremely simple means. Further, since the same power source V _DD as the memory cell power source is used as the bit line pull-up power source, the number of power source types does not increase, and the voltage 2.0 V which is sufficiently higher than the required voltage 0.6 to 0.7 V is used. Is stabilized by the transistors Q ₇ and Q ₈ and the diodes D ₁ and ₂ to obtain the required voltage, so that high stability can be obtained, which is very effective.

[Brief description of drawings]

FIG. 1 is a circuit diagram illustrating an embodiment of the present invention, FIG. 2 is a graph showing changes in bit line potential, FIG. 3 is a circuit diagram of a sense amplifier, and FIG. 4 is another embodiment of the present invention. Circuit diagram,
FIG. 5 is a circuit diagram showing a conventional example. In the drawing, Q _{1 to} Q ₄ are MESs forming a flip-flop.
FETs, Q ₅ and Q ₆ are MES FETs forming a transfer gate, B1 and B2 are a pair of bit lines, MC is a memory cell, and Q ₇ and Q ₈ are pull-up circuit MES Fs.
ET, D ₁ and D ₂ are the same diode, and Q ₁₄ and Q ₁₅ are MES forming a driver of an inverter type sense amplifier.
It is a FET.

Claims (2)

[Claims] 1. A semiconductor memory circuit comprising a memory cell composed of a flip-flop composed of an MES FET and a transfer gate connecting a pair of input / output terminals of the flip-flop to a pair of bit lines. Depletion type MES FET with shorted gate and source
And a diode connected between the gate of the MES FET and the ground, with the anode on the gate side, and a semiconductor memory circuit. 2. The memory circuit according to claim 1, wherein the diode is composed of a gate and a source of a MES FET forming a driver of a pair of inverters forming a sense amplifier.