JPH0632235B2 - Shift register - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register, which can perform a stable bidirectional shift operation without causing any racing, and has a small number of elements. The present invention relates to a shift register suitable for circuitization.

[Conventional technology]

A conventional shift register uses a storage element having a large number of elements such as a D flip-flop as a basic cell.

[Problems to be solved by the invention]

The conventional shift register described above is a D-type flip-flop (hereinafter referred to as D / F / F / F / FF) as a storage element for storing information.
F) is often used, but this D / F / F itself has a large number of elements, and the number of elements increases if a set / reset function is added, and the area is large especially when it is configured in an integrated circuit. It had the drawback of becoming

[Means for solving problems]

The shift register of the present invention comprises two single channel MO with two inverters each having its control line at the gate input.
A memory cell configured by connecting via S-transistors is a 1-bit storage cell, and the connection between the storage cells is via two single-channel MOS transistors having a control line at the gate input different from the above. However, unlike the conventional shift register, it has an original content that it is configured by using memory cells.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a memory cell used in the present invention, and FIG. 2 is an embodiment of a shift register which operates in one clock phase using the memory cell of FIG. FIG. 3 is a timing chart for explaining the shift operation of the embodiment shown in FIG.

In FIG. 2, reference numerals 1, 2, 5, 6 are CMOS inverters constituting memory cells 21, 22, 3, 4, 7, 8, 19,
Reference numeral 20 is an Nch enhancement type MOS transistor (hereinafter abbreviated as Nch Tr), 9 to 11 are inverters for inverting input signals at terminals 16 to 18, and 12 and 15 are ANs.
D gates, 13 to 14 AND-OR gates, 16 shift enable terminals, 17 forward / reverse shift switching terminals, and 18 clock terminals.

In FIG. 3, in the section I, AND gates 12 and 15
Output is low level (hereinafter abbreviated as L), so Nch Tr
19, 20 turn off. Also, AND-OR gate 1
Since the outputs of 3 and 14 are at a high level (hereinafter abbreviated as H), the Nch Trs 3, 4, 7 and 8 are turned on. Therefore, the information stored in each memory cell is stably held and the shift operation is not performed.

In section II, when the clock is H, AND-O
Nch by R gates 13 and 14 and AND gate 15
The Trs 3, 4, 7, 8 and 20 are turned off, and the Nch Tr 19 is turned on by the AND gate 12. At this time, the information of the memory cell 21 held in the gate capacitance of the CMOS inverter 2 is
It is transferred to the gate capacitance of the CMOS inverter 5 forming the memory cell 22 through the Nch Tr 19. Then, when the clock becomes L, the Nch Tr 19 is turned off by the AND gate 12 and the Nch Trs 4 and 8 are turned on by the AND-OR gate 14, so that the information of the memory cell 21 transferred to the gate capacitance of the CMOS inverter 5 in the memory cell 22. Is Nc
It is stored in the gate capacitance of the CMOS inverter 6 through the h Tr 8. That is, in the section II, the information in the memory cell 21 is shifted to the memory cell 22 by 1 bit.

Since L is input to the forward / reverse shift switching terminal in section II, AND-O in the section where the clock is H
The outputs of the R gate 1314 and the AND gate 12 are L
Therefore, Nch Tr3,4,7,8,19 is turned off, and AN
Since the output of the D gate 15 becomes H, the Nch Tr 20 turns on. At this time, the information of the memory cell 22 stored in the gate capacity of the CMOS inverter 5 is transferred to the gate capacity of the CMOS inverter 2 forming the memory cell 21 through the Nch Tr 20. Then, when the clock becomes L, the Nch Tr 20 is turned off by the AND gate 15, and the Nch Trs 3 and 7 are turned on by the AND-OR gate 13, so that the memory cell 21
At, the information of the memory cell 22 transferred to the gate capacity of the CMOS inverter 2 is stored in the gate capacity of the CNOS inverter 1 through Nch 3. That is, in the section III, the shift is one bit, which is the reverse of the case in the section II.

FIG. 4 is a circuit diagram of the second embodiment of the present invention. In FIG. 4, a memory cell, a shift enable terminal, a forward / reverse shift switching terminal and an inverter for inverting the signals input from the two terminals are the same as those in FIG. Then, the shift operation is performed by inputting the two-phase clocks to the terminals 27 and 28, respectively.

FIG. 5 is a diagram showing a timing at which the circuit of FIG. 4 operates. The principle of the shift operation is the same as that of FIG. 3 and therefore the explanation thereof is omitted. In this case, there is a slit in the two-phase clock. Therefore, a more stable shift operation can be performed.

〔The invention's effect〕

As described above, the present invention includes two inverters.
A memory cell is configured by connecting via one single-channel MOS transistor, and a stable shift operation without racing is achieved by connecting via two single-channel MOS transistors to the memory cell in the next stage. A bidirectional shift register that can be implemented and has a small number of elements can be configured.

Also, the setting and resetting functions can be added by adding a few transistors.

[Brief description of drawings]

1 is an example of a memory cell according to the present invention, FIG. 2 is a first embodiment of a shift register according to the present invention using the memory cell of FIG. 1, and FIG. 3 is an operation of the shift register of FIG. 4 is a timing chart for explaining the above, FIG. 4 is a second embodiment of the shift register according to the present invention using the memory cell of FIG. 1, and FIG. 5 is a diagram for explaining the operation of the shift register of FIG. Timing chart. 1, 2, 5, 6 ... CMOS inverters, 3, 4, 7,
8, 19, 20 ... Nch enhancement MOS transistors, 9-11 ... Inverters, 12, 15, 23, 26
... AND gate, 13, 14, 24, 25 ... AND-O
R gate, 16 ... Shift enable input terminal, 17 ...
Forward / reverse shift switching input terminals, 18, 27, 2
9 ... Clock input terminal.

Claims (1)

[Claims] 1. A shift register capable of transferring information bit by bit, the storage cell of which comprises an input of a first inverter and an output of a second inverter, and a first inverter.
Output of the inverter and the input of the second inverter are a first single-channel MOS transistor whose first control line is input to the gate and a second single-channel MOS transistor whose second control line is input to the gate, respectively. Between the memory cells, the input and output of the second inverter, the output and input of the first inverter in the memory cell of the next stage, and the gates of the third and fourth control lines, respectively. Third and fourth single channel MOSs
A shift register, which is connected through a transistor.