JPH0632493B2 - Router cell - Google Patents

Description

The present invention relates to a router cell, and more particularly to a router cell used to connect a plurality of processors to form a multiprocessor.

[Conventional technology]

For example, in a large-scale information processing such as a logic simulation required for development of a large-scale system using an LSI, the processing capacity is becoming insufficient with a sequential processing by a single processor. In order to solve such problems,
A method has been proposed in which the processor has a multi-configuration and high-speed processing is performed.

In such a multiprocessor system, it is considered to use a multistage connection network composed of a plurality of switching nodes as a method of connecting dozens of processors and transferring a large amount of events with a relatively small amount of hardware. There is. Events are transferred between processors in the form of packets. A router node (routing cell) is provided as a switching node that has the function of selecting its own output destination from the address that specifies the transfer destination processor (self-routing).
ter cell). Normally, the address is added to the beginning of the transferred data packet.

In a multi-stage connection network, blocking may occur in which a plurality of input signals collide with each other at a switching node, so it is customary to provide each router cell with some buffer function.

The details of the multiprocessor system using a non-cyclical network (a type in which a signal passing through one switching node does not return to the switching node again) composed of router cells of a two-input two-output crossbar switch are described in, for example, information. Journal of Processing Academia, 25 (1984) P.864〜872
And the papers, "Architecture of Logic Simulation Machine" and "Hardware Configuration of Logic Simulation Machine", on pages 873 to 881.

In the multistage connection network, there is also a cyclic network in which switching nodes are interconnected so that a signal passing through one switching node can be returned to the switching node again. The cyclic multi-stage connected network can realize the same connection function with fewer switching nodes as compared with the non-cyclic multi-stage connected network, and therefore requires less hardware. When a cyclic multistage connection network is used in a multiprocessor system, a processor is connected to each switching node, and therefore, as a router cell, for example, one set of input / output ports for the processor directly connected and two sets of input / output ports for the network are used. The one having a total of three sets of input / output ports is used.

m input m output (input / output port m to the network
The number N of processors that can be connected by self-routing a cyclic network multistage connection network consists of switching node set) is expressed as the number of stages of the network N = s · m s ^...... as s (1). When the router cell of m = 2 described above is used as a switching node, N = s · 2 ^s . In this cyclic multistage connection network, log ₂ s (log ₂ m +
1) All processors can be addressed by bit address data. The processor connected to each router cell has a vertical address of log ₂ s · log ₂ m bits and a horizontal address of log ₂ s bits. Each router cell first decodes the vertical address of the address added to the beginning of the input data packet. If the decoded vertical address does not match the vertical address of the connected processor, the data packet is output from the output port determined by the first bit of the vertical address. If there is a match, then the lateral address is decoded. When the horizontal address also matches the horizontal address of the connected processor, the data packet is output to the connected processor. When the horizontal addresses do not match, the data packet is output from the output port connected to the router cells having the same vertical address.

FIG. 2 is a block diagram showing an example of such a conventional router cell.

The conventional example shown in FIG. 2 has two sets of input / output ports for forming a network, namely, an input port PI1 and an output port PO1 and an input port PI2 and an output port PO2, and an input / output port directly connected to a processor. That is, it has an input port PIP and an output port POP.

For example, when transferring data from a transfer source router cell (not shown) connected to the input port PI1 to a transfer destination router cell (not shown) connected to the output port PO1 via the conventional example shown in FIG. The operation of the conventional example shown in FIG. 2 will be described.

When the input control device 111 receives the SEND signal SI1 notifying that the data signal is transferred from the transfer source connected to the input port PI1, when the input buffer 101 is empty, the data signal DI from the transfer source is sent to the input buffer 101.
Busy signal B that causes 1 to be latched and then completes reception
I1 is sent to the transfer source, and the output discriminating apparatus 211 is notified of that fact. Output discrimination device 2 that received this notification
11 is for outputting the data latched by the input buffer 101 when the output buffer 201 is empty.
1 and decodes the transfer destination address by the built-in decoder as described above to select the output port PO1. The data latched in the output buffer 201 is sent to the transfer destination as the data signal DO1 and the data is transferred. The SEND signal SO1 is sent from the output control device 301 to the transfer destination. This completes the data transfer preparation.
The output control device 301 makes completion of reception from the transfer destination
When receiving the Busy signal BO1, the output discriminating apparatus 211 erases the data latched in the output buffer 201 and completes the data transfer. When the output buffer 201 completes the latching of data, the output discriminating apparatus 211 notifies the input control apparatus 111 of the fact, and the input control apparatus 111 which has received the notification notifies the data latched in the input buffer 101. Erase. The input buffer 101 has a capacity of 2 packets, and the output buffer 201 has a capacity of 1 packet.

As explained above, the conventional example shown in FIG.
Data is transferred by handshaking with the Busy signal.

[Problems to be solved by the invention]

Since the conventional router cell performs all the above-mentioned data transfer operations electrically, the operation speed is slow, and it takes much time to transfer data in the multi-stage connection network as compared to data processing in each processor. There is a drawback that the high speed function of is not fully utilized.

An object of the present invention is to provide a router cell capable of transferring data at high speed by solving the above drawbacks and replacing the processing inside the multi-stage connection network with light.

[Means for solving problems]

The router cell of the present invention has a self-routing function which constitutes a switching node of a multi-stage connection network which is provided with a data optical signal in which data to be transferred is on-off modulated with this data and an address for designating the destination of the data is provided with an electric signal. And a first photodetector for detecting an input data signal input from a data transfer source, and a detection output end of the first photodetector controlled from the outside, connected to a drive input end. A single monochromatic light source that emits light while the detection output of the first photodetector indicates that the input data optical signal is present, and a first control light that indicates that the data transfer source has transferred data. A second photodetector that detects a signal, a second monochromatic light source, a third photodetector, and when the third photodetector detects light, receives data from the transfer source. A third monochromatic light source that sends out a pulsed second control light signal to indicate that the second monochromatic light source is not emitting light and the second photodetector is the first control. When the optical signal is detected, the drive input end of the first monochromatic light source is connected to the detection output end of the first photodetector and the second monochromatic light source is caused to emit light, and the third photodetector is A first control means for detecting light and disconnecting the connection between the detection output end of the first photodetector and the drive input end of the first monochromatic light source and stopping the emission of the second monochromatic light source. And having a plurality of first sets in which the first and second monochromatic light sources and the third photodetector are arranged so that their respective output optical axes or input optical axes are parallel to and close to each other, An input device in which these first groups are arranged adjacent to each other and external control Is set to a storable state and the output light of the first monochromatic light source is input, and the input light of the output light of the first monochromatic light source is stored, and while the input is stored, An optical memory that sends output light as an output data optical signal to a data transfer destination and stops light emission by external control to erase the memory,
A fourth photodetector for detecting the output light of the second monochromatic light source, and a fourth monochromatic light source for sending out a third control optical signal indicating that data has been transferred to the data transfer destination by external control. A fifth photodetector that detects a fourth control optical signal that indicates that the transfer destination has completed data reception, and pulsed light that completes storage of the optical memory under external control. A fifth monochromatic light source for sending to a third photodetector; and the optical memory when the fourth photodetector detects the output light of the second monochromatic light source and the fourth monochromatic light source is not emitting light. Is set to a storable state, the fourth control light signal is transmitted to the fourth monochromatic light source after a predetermined time has elapsed, and the pulsed light is transmitted to the fifth monochromatic light source. The five photodetectors are the fourth And a second control means for erasing the memory of the optical memory when detecting an optical signal and for stopping the light emission of the fourth monochromatic light source, the optical memory, the fourth photodetector, and the fifth The relative positional relationship of the input optical axis or the output optical axis of each of the monochromatic light sources is such that the output optical axis or the input optical axis of each of the first and second monochromatic light sources of the input device and the third photodetector is relative to each other. The same number of the first set of the second set arranged so as to match the positional relationship is provided, these second sets are adjacent to each other and at a predetermined interval from each of the first set. The output devices arranged so as to face each other and the variable pitch diffraction gratings whose grating pitch is controlled by a grating control signal respectively inputted from the outside are provided at least as many as the number of the first set, and these variable pitch diffraction gratings are provided. The first monochromatic light source and the second monochromatic light source, the third photodetector, and the output device of each of the first set of input devices corresponding to respective changes of the grating control signal. And the input device for switching the optical connection between the optical memory and the fourth photodetector and the fifth monochromatic light source of each of the second set in units of the first and second sets. A spatial light switch disposed between the output signal,
The address electrical signal input from each of the data transfer sources is decoded to obtain optical connection information between each of the first set of input devices and each of the second set of output devices. A switch control device that sends the address electrical signal to each of the data transfer destinations corresponding to the optical connection information, generates each of the grating control signals corresponding to the optical connection information, and sends the grid control signal to the spatial optical switch. It is configured to include.

〔Example〕

The router cell of the present invention is used to form a switching node of a multistage connection network. A processor or the like connected by a multistage connection network composed of a plurality of router cells of the present invention inputs / outputs data in the form of packets transferred via the multistage connection network as a data optical signal which is on / off modulated by this data. Then, the SEND signal indicating that 1 bit of the data optical signal has been transferred and the BUSY signal indicating that the reception of the transferred 1 bit has been completed are also input and output as optical signals. Normally, the address which is added to the head of the packet and which designates the destination of the packet is given to the multistage connection network not as a part of the data optical signal but as an electric signal.

Hereinafter, the present invention will be described in detail with reference to the drawings illustrating an embodiment.

FIG. 1 is a block diagram of an embodiment of the router cell of the present invention.

The router cell shown in FIG. 1 has three sets of input / output ports, namely, input ports PI1, PI2, PIP and output ports PO1, PO2, POP. The input device 1, the spatial light switches 2 and 3, and the output device 4 are provided. , And the switch control device 5. Input device 1
Via the optical fiber 61 which is a set of three,
The transfer source corresponding to each input port, the data signal that is the input data optical signal, the SEND signal that is the first control optical signal that indicates that the transfer source has transferred data, and that the data reception to the transfer source is completed. The BUSY signal, which is the second control light signal that causes The transfer source is another router cell preceding this router cell, a processor directly connected to this router cell, or the like. Output device 3
Through the optical fiber 62 which is a set of three,
A transfer destination corresponding to each output port, a data signal that is an output data optical signal, a SEND signal that is a control optical signal that indicates that data has been transferred to the transfer destination, and a transfer destination that indicates that the transfer destination has completed data reception. The four control light signals
Exchange BUSY signals. The transfer destination is another router cell subsequent to this router cell, or a processor directly connected to this router cell, or the like. Switch control device 5
Inputs address signals AI1, AI2, and AI3, which are electrical signals for designating a destination as a multistage connection network of data signals input to the input ports PI1, PI2, and PIP, from the transfer source of these data signals. The switch control device 5 decodes the address signals AI1 to AI3 to obtain information of three transfer destinations to which each data signal should be transferred, and also corresponds to the address signals AI1 to AI3, as already described as the prior art. Send to the transfer destination of the data signal. The reference numbers of the address signals sent to the transfer destinations connected to the output ports PO1, PO2, and PO3 are AO1 and A.
O2 and AO3.

FIG. 3 shows an input port PI1 of the embodiment shown in FIG.
The data signal DI1 from the transfer source connected to the output port to the transfer destination connected to the output port POP.
FIG. 3 is a partial configuration diagram showing an optical part related to transfer as No. 3. The configuration of the embodiment shown in FIG. 1 will be further described with reference to FIG.

The input device 1 includes input devices 1a, 1b, 1c corresponding to the input ports PI1, PI2, PIP. The input device 1a is driven by a control circuit (not shown), photodetectors 11 and 13 for detecting the data signals DI1 and SEND signals SI1 input from the data transfer source, and output light driven by the detection output of the photodetector 11. Of the semiconductor laser 12 for sending the light to the spatial light switch 2 side, the semiconductor laser 14 for turning on and off the output light to the side of the spatial light switch 2 and the light for detecting the light input from the side of the spatial light switch 2 Detector 1
5 and a semiconductor laser 16 that is driven by the detection output of the photodetector 15 to emit light and output the output light as a BUSY signal BI1 to the transfer source. The detection output end of the photodetector 11 and the drive input end of the semiconductor laser 13 are connected by the control of the control circuit and are disconnected. When connected, if there is input light of the data signal DI1, the semiconductor laser 13 is driven by the electric signal which is the detection output of the photodetector 11 to generate monochromatic light. In this way, the input device 1 reproduces the level of light attenuated by the optical fiber 61 and the spatial light switches 2 and 3. The configurations of the input devices 1b and 1c are exactly the same as the configuration of the input device 1a.

The output device 4 includes output devices 4a, 4b and 4c corresponding to the output ports PO1, PO2 and POP. The output device 4c includes a control circuit (not shown) and input devices 1a and 1b.
Alternatively, the output light of the semiconductor lasers 12 and 13 of 1c is input through the spatial light switches 2 and 3 to the optical memory 41 and the photodetector 42, and on / off is controlled by the control circuit, and the output light is sent to the transfer destination as the SEND signal SO3. The semiconductor laser 43 that operates and the BUSY signal BO3 input from the data transfer destination
And a semiconductor laser 45 which is controlled by a control circuit to turn on / off the output light and sends the output light to the photodetector 15 of the input device 1a, 1b or 1c via the spatial light switches 3 and 2. It is configured. The optical memory 41 is a semiconductor laser that is electrically driven by a control circuit and is electrically stopped. When electrically driven, the optical memory 41 is biased so as to oscillate when light of a level higher than the threshold value is input and continue to generate monochromatic light, or to maintain the oscillation stop state. The presence or absence of light is latched and stored, and when it is present, the light emission output is output to the corresponding transfer destination via the optical fiber 62. When the electric drive is stopped, the optical memory 4
The memory of 1 is erased. In this way, the output device 4c
Stores the optical signal input to the optical memory 41 as light without converting it into an electrical signal. The configurations of the output devices 4a and 4b are exactly the same as the configuration of the output device 4c.

The spatial light switch 2 is configured to include variable pitch diffraction gratings 21, 22 and 23, which are arranged facing the input devices 1a, 1b and 1c and the output device 4 side, respectively. The spatial light switch 3 includes variable pitch diffraction gratings 31, 32, 32, which are arranged to face the diffraction gratings 21, 22, 23, respectively.
It comprises 33. Output device 4a / 4b / 4
c is arranged facing the diffraction gratings 31, 32, and 33, respectively. Three lights, which are data signals, SEND signals, and BUSY signals input to and output from one port, need to be exchanged between the input device 1 and the output device 4 through the same optical path,
For that purpose, the optical axes of the semiconductor laser 12, semiconductor laser 14, and photodetector 15 of the input devices 1a, 1b, 1c are orthogonal to the input / output surfaces of the diffraction gratings 21, 22, 23, and the output devices 4a, 4b, Since the optical axes of the optical memory 41, the photodetector 42, and the semiconductor laser 45 of 4c must be orthogonal to the input / output surfaces of the diffraction gratings 31, 32, and 33, two sets of diffraction gratings, that is, the diffraction gratings 21 to 23 and the diffraction gratings Lattice 31-33
Is provided.

First, the operation of the variable pitch diffraction grating will be generally described.

The pitch of the diffraction grating is, for example, in the case of an amplitude type diffraction grating, the interval between the portions (or the portions that do not transmit) that periodically transmit light. When monochromatic light having a wavelength λ is incident on the diffraction grating perpendicularly, the incident light is mainly diffracted in the direction of the diffraction angle θ of the + 1st order diffracted light corresponding to the grating pitch d. The diffraction angle θ is expressed by the following equation.

sin θ = λ / d (2) A variable-pitch diffraction grating refers to a device that can change the grating pitch continuously or intermittently. The variable pitch diffraction grating can change the diffraction angle of the incident light by changing the grating pitch.

In this embodiment, the diffraction gratings 21 to 23 and 31 to 33 are composed of variable grating mode liquid crystal in which the pitch of the grating generated inside the liquid crystal can be changed by changing the voltage applied to the liquid crystal. A grating control signal, which is information for controlling the grating pitch of the diffraction gratings 21 to 23 and 31 to 33, is supplied from the switch control device 5.

As described above, the switch destination of each data signal obtained by decoding the address signals AI1 to AI3 by the switch control device 5 is the input device 1 from the spatial optical switches 2 and 3.
It is the information of the optical connection between a. 1b. 1c and the output device 4a. 4b. 4c. The switch controller 5 generates a grating control signal indicating this optical connection information to generate the spatial optical switches 2.3.
Output to. The spatial light switches 2 and 3 respond to the grating control signal supplied from the switch control device 5 in response to the diffraction grating 2
R in which the voltage value to be applied to 1 to 23 and 31 to 33 is written
It incorporates an OM, reads out the voltage value addressed by the grating control signal from this ROM, and applies the voltage of this value to the diffraction gratings 21-23, 31-33. In this way, the spatial light switches 2 and 3 have the variable pitch diffraction grating 21.
.. 23.31-33 are used to change the deflection angle of the optical path, and input devices 1a, 1b, 1c and output devices 4a, 4b.
Switching of optical connection with 4c. This switching of optical connection is done by inputting / outputting data signal / SEND signal /
It is performed in units of three lights that are BUSY signals.

In the range shown in FIG. 3, the photodetector 11, the semiconductor laser 12, the diffraction grating 21, the diffraction grating 33, and the optical memory 4 are shown.
1 is used for transmitting and receiving data signals, the photodetector 13, the semiconductor laser 14, the diffraction grating 21, the diffraction grating 33, the photodetector 42, and the semiconductor laser 43 are used for transmitting and receiving SEND signals, and the photodetector 44, the semiconductor. Laser 45, diffraction grating 33,
The diffraction grating 21, the photodetector 15, and the semiconductor laser 16 are BUSY.
Used to send and receive signals.

From the transfer source connected to the input port PI1 to the output port P
The operation of the embodiment shown in FIG. 1 will be described by taking as an example the case of transferring data to the transfer destination connected to the OP.

FIG. 4 is a time chart of each signal in this case.

The switch control device 5 receives the address signal AI from the transfer source.
1 is deciphered to determine the transfer destination, the address signal AI1 is sent to the transfer destination as the address signal AO3, and the lattice control signal indicating the correspondence between the transfer source input port and the transfer destination output port is generated to generate the spatial optical switch 2・ Output to 3.

The spatial light switches 2 and 3 read out the voltage value addressed by the grating control signal from the built-in ROM and apply this voltage to the diffraction gratings 21 and 33 to input the semiconductor laser 12, the semiconductor laser 14, and the light of the input device 1a. The optical memory 41, the photodetector 42, and the semiconductor laser 14 of the output device 4c of the detector 15.
Optically connect to.

In this state, from the transfer source to the photodetectors 11 and 13 of the input device 1a via the optical fiber 61, the data signals DI1 and SE
The ND signal SI1 is input. The control circuit of the input device 1a is
When the input port PI1 is not busy, that is, when the semiconductor laser 14 is not sending light to the output device 4c, the detection output end of the photodetector 11 is connected to the drive input terminal of the semiconductor laser 12 to prepare data. Also, the semiconductor laser 14 is caused to emit light. As illustrated in FIG. 4, if there is input light of the data signal DI1 at this time, the semiconductor laser 12 emits light. The output light of the semiconductor lasers 12 and 14 is diffracted by the diffraction gratings 21 and 33, sent to the output device 4c, and input to the optical memory 41 and the photodetector 42.

The control circuit of the output device 4c uses the SE when the output port POP is not busy, that is, the semiconductor laser 43 emits light.
When the ND signal SO3 is not transmitted, the optical memory 41 is electrically driven, and if there is input light, it is latched to store the presence or absence of input light, that is, data is set.
In this case, since the output light of the semiconductor laser 12 is input to the optical memory 41, the optical memory 41 emits the output light to the transfer destination via the optical fiber 62 and the data signal DO3.
As. When the data set in the optical memory 41 is completed, the control circuit causes the semiconductor laser 43 to emit light, sends the SEND signal SO3 to the transfer destination via the optical fiber 62, and causes the semiconductor laser 45 to emit light in pulsed form. Output light is sent to the input device 1a via the diffraction gratings 33 and 21, and data transfer preparation is completed.

When the photodetector 15 of the input device 1a detects the output light of the semiconductor laser 45, the semiconductor laser 16 emits light in pulses and sends a BUSY signal BI1 as shown in FIG. 4 to the transfer source. Further, the control circuit of the input device 1a disconnects the connection between the detection output end of the photodetector 11 and the drive input end of the semiconductor laser 12, and stops the emission of the semiconductor laser 14.

When the photodetector 44 detects the BUSY signal BO3 from the transfer destination, the control circuit of the output device 4c stops the electrical driving of the optical memory 41 to erase the storage (as a result, the output light of the data signal DO3 is At the same time, the emission of the semiconductor laser 43 is stopped and the sending of the SEND signal SO3 is stopped, whereby the data transfer is completed.

On the other hand, when the BUSY signal BI1 is received by the transfer source, the transfer source also stops sending the data signals DI1 and SEND signals SI1.

When the SEND signal SI1 is input, the data signal DI1
If there is no input light, the semiconductor laser 12 does not emit light, and the optical memory 41 stores that there is no input light.
The level of the data signal DO3 during transmission of the ND signal SO3 becomes zero.

As described above by taking the embodiment of FIG. 1 as an example, the router cell of the present invention processes the data signal, SEND signal, and BUSY signal as optical signals, and switches the signal path between the input port and the output port by the spatial light. Do it with a switch. Temporary storage of data is performed by an optical memory that holds only a 1-bit data optical signal. When blocking occurs, the data optical signal of the bit after the bit stored in the optical memory is held at the transfer source. As described above, in the router cell of the present invention, the conventional electrical router cell has the buffer memory that holds the data as a packet in the case of blocking, whereas it is difficult to realize the optical high-speed and large-capacity memory. Deal with blocking without using.

The data transfer rate per port of the conventional router cell is 1
It is about 0 MHz, but the router cell of the present invention is IGHz.
The above data transfer rate can be realized.

〔The invention's effect〕

As described in detail above, the router cell of the present invention processes the data signal to be transferred and the signal (SEND signal / BUSY signal) for controlling the data transfer as an optical signal, and switches the signal path between the input and output ports by the spatial light. Since it is done with a switch, it is possible to transfer data at high speed. Also, the only electrical signals that can be input and output are address signals, and all other input and output signals are optical signals. Since it can be performed at a much higher density as compared with the above, there is an effect that the size can be reduced even when the number of input / output ports is increased, and a high density can be achieved even when a large number of router cells are mounted.

[Brief description of drawings]

1 is a block diagram of an embodiment of a router cell of the present invention, FIG. 2 is a block diagram showing an example of a conventional router cell, FIG. 3 is a partial configuration diagram of the embodiment shown in FIG. FIG. 4 is a time chart for explaining the operation of the embodiment shown in FIG. 1, 1a ... Input device, 2, 3 ... Spatial light switch,
4, 4c ... Output device, 5 ... Switch control device, 11
・ 13 ・ 15 ・ 42 ・ 44 ... Photodetector, 12 ・ 14 ・
16 ・ 43 ・ 45 …… Semiconductor lasers 21-23, 31
~ 33 …… Diffraction grating, 41 …… Optical memory.

Claims (1)

[Claims] 1. A self-routing function which constitutes a switching node of a multi-stage connection network in which data to be transferred is provided as a data optical signal which is on-off modulated with this data and an address for designating a destination of the data is provided as an electric signal. And a first photodetector that detects an input data optical signal input from a data transfer source, and a detection output end of the first photodetector that is externally controlled and is connected to a drive input end. A first monochromatic light source that emits light while the detection output of the first photodetector indicates that the input data optical signal is present, and a first control light that indicates that the data transfer source has transferred data. A second photodetector for detecting a signal, a second monochromatic light source,
A third photodetector, and a third monochromatic light source for sending a pulsed second control light signal to the transfer source when the third photodetector detects light, which indicates completion of data reception. When the second monochromatic light source is not emitting light and the second photodetector detects the first control light signal, the first monochromatic color at the detection output end of the first photodetector. The drive input end of the light source is connected and the second monochromatic light source is caused to emit light, and when the third photodetector detects light, the detection output end of the first photodetector and the first monochromatic light source. And a first control means for stopping the emission of the second monochromatic light source and disconnecting the connection with the drive input end, the first and second monochromatic light source and the third photodetector, respectively. The first set arranged so that the output optical axis or the input optical axis of the An input device having a plurality of these first sets arranged adjacent to each other, and when the output light of the first monochromatic light source is input and is set to a storable state by external control, The input light output of the first monochromatic light source is stored, and while the input light is stored, the output light is sent to the data transfer destination as an output data optical signal, and the light emission is stopped by external control to store. An optical memory for erasing, a fourth photodetector for detecting the output light of the second monochromatic light source, and a third control optical signal for indicating that data has been transferred to the data transfer destination by external control. A fourth monochromatic light source, a fifth photodetector that detects a fourth control light signal that indicates that the transfer destination has completed data reception, and a pulse shape that completes storage of the optical memory under external control. The light of A fifth monochromatic light source for sending to a third photodetector; and the optical memory when the fourth photodetector detects the output light of the second monochromatic light source and the fourth monochromatic light source is not emitting light. Is set to a storable state, the fourth control light signal is transmitted to the fourth monochromatic light source after a predetermined time has elapsed, and the pulsed light is transmitted to the fifth monochromatic light source. And a second control means for erasing the memory of the optical memory and stopping the emission of the fourth monochromatic light source when the fifth photodetector detects the fourth control light signal. Four photodetectors and the fifth monochromatic light source, the relative positional relationship of the input optical axis or the output optical axis of each of the first and second monochromatic light sources of the input device and the third photodetector, respectively. Output optical axis or input The same number as the number of the first set of the second set arranged so as to match the relative positional relationship of the optical axis, and these second sets are adjacent to each other and predetermined with each of the first set The output devices arranged so as to face each other at intervals, and the variable pitch diffraction gratings whose grating pitch is controlled by a grating control signal respectively inputted from the outside are provided at least as many as the number of the first set, and these variable pitches are provided. A diffraction grating corresponding to each change of the grating control signal, the first monochromatic light source and the second monochromatic light source and the third photodetector of each of the first set of the input device; The input to switch the optical connection between the optical memory and the fourth photodetector and the fifth monochromatic light source of each of the second set of output devices in units of the first and second sets. Equipment and front A spatial optical switch disposed between the output signal and each of the first set of the input device and the second set of the output device by decoding an address electric signal input from each of the data transfer sources. Optical connection information with each of the optical connection information, the address electrical signal is sent to each of the data transfer destinations corresponding to the optical connection information, and each of the grid control signals is generated corresponding to the optical connection information. And a switch control device for sending to the spatial light switch.