JPH0634156B2 - LCD segment drive circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a drive circuit for a liquid crystal segment.

2. Description of the Related Art A liquid crystal display device composed of a C-MOS or the like has attracted attention as a terminal for a handheld computer due to its low power consumption. The features are no longer available in conventional drive circuits.

FIG. 3 is a diagram showing an example of an IC of a conventional liquid crystal drive circuit. In the figure, 1 is a transmission gate, and when n liquid crystal segments are provided, for example, 80 output signals are provided when 80 liquid crystal segments are provided. With lines, use 2 or 2 × n gates for each segment. Reference numeral 2 is an inverter, 3 is a memory, and 4 is a shift register. Each of the inverters 2 to 4 is used for each segment, i.e., n pieces. As a method of driving the dot matrix type liquid crystal as described above, conventionally, a memory corresponding to the number of segments and a shift register are provided, and data for one line is given to the shift register in synchronization with a clock pulse. Then, the contents of the register are transferred to the memory at the end of one line to create the segment drive signal. However, in the large capacity matrix, the number of segments N is 640, that is, I shown in FIG.
There are 6 C chips, and it is necessary to transfer the 640 data within the time of (frame time) × (duty).
Now, assuming that the frame time is 16 msec and the duty is 1/256, the shift pulse width is 62.5 μsec / 640 = 0.09.
It becomes 7 μsec, and it is necessary to transfer with a shift clock of 10 MHz or more. Since it is necessary to apply the input signal of 10 MHz or more to all the shift registers, if the power required for the signal shift is P and the gate capacity of the clock input of the shift register is C, the power consumption becomes P = CV ² f × N, Since the number of segments is proportional to N and the frequency f is also proportional to N, power consumption increases in proportion to N ² . Now, in order to drive N segments with a segment driver having n outputs, N / n drivers are required, and these are connected to N / n (640/80 = 8 in the above example) series. Since the display signal is transferred, the number of shift registers to which the shift clock is input becomes N, and the power increases in proportion to N ² .

Purpose The present invention has been made in view of the above-mentioned circumstances,
In particular, the purpose is to reduce the power consumption of the liquid crystal drive circuit.

Structure In order to achieve the above object, the present invention includes a memory provided corresponding to a liquid crystal segment and a shift register connected to the memory, and synchronizes one line of data to the shift register with a shift clock. Then give and transfer 1
In a plurality of liquid crystal segment drive ICs that transfer the contents of the shift register to the memory at the end of the line to generate the liquid crystal segment drive signal, the shift counter connected to the shift register and the shift clock are counted by the shift counter. And a gate circuit for preventing the shift clock from being input to the shift register based on the count value, and one liquid crystal segment drive IC
Other liquid crystal segment drive IC
It is characterized by not driving.
Hereinafter, description will be given based on examples of the present invention.

The present invention aims to reduce the use of shift registers used only for signal transfer, and to reduce the power consumption at the input gates of the registers due to on / off of transfer signals. That is, of the display signals, only the register that needs the signal is driven, and the shift signal is not given to the other registers that do not need it, thereby reducing the power consumption of the gate.

FIG. 1 is an electric circuit diagram showing an example of an IC chip for explaining an embodiment of the present invention, and FIG. 2 shows a plurality of ICs shown in FIG. 1 (eight in the above example). FIG. 1 is a diagram showing an example in the case of doing so. In FIG. 1, 10 is a transmission gate circuit, 11 is an inverter, 12 is a memory, 13 is a shift register, 14 is a shift counter, 15 is a gate circuit, and 16 is an SR flip-flop. A circuit, 17 is a timing generation circuit, and a plurality of ICs configured in this way are cascaded as shown in FIG. Thus, in the present invention, the shift clock is counted by the shift counter 14, and the shift clock input gate 15 is closed when the number of output segments reaches n, thereby making it possible to perform other, that is, the remaining (in the above-mentioned example, (7 pieces) When data is input to the drive circuit, unnecessary shift clocks are prevented from being input to the register 13 to reduce power consumption due to the gate capacity of the register. That is, in the present invention, the power consumption of the gate of the shift register 13 is P = fCV ² × n even when the number of segments is N, and the power consumption of the conventional n / N can be obtained. N
When the / n number of drivers are connected and the control gate of the first circuit ((I) in FIG. 2) is set to H (high level), the data from all shift registers are displayed by the strobe input St. The F / F set in the counter input gate is reset by the timing generation circuit while being latched in the memory. At this time, the first
Since the second control gate is at H,
A signal is output from the timing generation circuit so that the gate is opened only in this circuit. However, in the second circuit (II),
Since the control signal is connected to the L (low level) signal of the F / F, a timing signal for closing the gate is generated. Next, when only the first circuit (I) is transferred with the shift clock and the counter reaches n,
The F / F is set by the count-up signal, the input gate is closed, the control signal becomes "H", and the data is transferred to the next circuit. Data is sent to the circuits one after another, and when the data is sent to all the circuits, the contents of the register are latched in the memory by the strobe signal and the process returns to the first circuit.

Effect As is clear from the above description, according to the present invention, it is possible to provide a liquid crystal segment drive circuit with low power consumption, and it is possible to further improve the effect of using the liquid crystal display device.

[Brief description of drawings]

FIG. 1 is an electrical block diagram for explaining an embodiment of an IC liquid crystal segment drive circuit according to the present invention.
FIG. 1 is an electrical block diagram when a plurality of ICs shown in FIG. 1 are connected in cascade, and FIG. 3 is an electrical block diagram showing an example of a conventional liquid crystal segment drive circuit. 10 ... Transmission gate circuit, 11 ... Inverter, 12 ... Memory, 13 ... Shift register, 1
4 ... Shift counter, 15 ... Gate circuit, 16 ...
Flip-flop circuit, 17 ... Timing generation circuit.

Claims (1)

[Claims] 1. A memory provided corresponding to a liquid crystal segment, and a shift register connected to the memory,
A plurality of liquid crystal segment drives for applying data for one line to the shift register in synchronization with a shift clock and transferring the data, and transferring the contents of the shift register to the memory at the end of one line to generate the liquid crystal segment drive signal. IC
A shift counter connected to the shift register, and a gate circuit that counts a shift clock by the shift counter and prevents the shift clock from being input to the shift register based on the count value.
A liquid crystal segment drive circuit, characterized in that, when one liquid crystal segment drive IC is being driven, the other liquid crystal segment drive ICs are not driven.