JPH0634163B2 - Luminance interpolator for CRT waveform display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention sequentially samples input signal waveforms to create sampling dot data corresponding to the amplitude of each time-axis address on the display surface, and to generate adjacent time-axis addresses. The present invention relates to a luminance interpolating device for displaying a cathode ray tube waveform, which linearly interpolates between the sampling dot data of the above with a bright line, and further complements the luminance at the joint portion of the bright line.

[Problems to be solved by conventional technology and invention]

In this type of dot-type waveform display device, normally, the dot display data is stored in a dot pattern in a RAM with a capacity equivalent to the time axis address x amplitude address of the display surface. The full amplitude address is read and scanned to generate a dot display signal. Therefore, there is a problem that the capacity of RAM naturally increases.

Therefore, it is an object of the present invention to provide a luminance interpolating device for cathode ray tube waveform display of the kind described at the beginning to reduce the storage capacity of RAM for storing dot display signals and obtain a smooth display screen. .

[Means for solving problems]

In order to achieve this object, the present invention provides, as shown in FIG. 1, a time axis address N immediately before or after a lower amplitude level with respect to the linear interpolation data (D _N ) of each time axis address N.
-1 or N + 1 bottom side Bottom side that defines the span between the seam interpolation start dot position (Ds) corresponding to the bottom dot position of the linear interpolation data and the bottom dot position (D _N b) of the linear interpolation data (D _N ). Top dot of the seam interpolation end dot position (Df) and linear interpolation data (D _N ) corresponding to the top dot position of the top side linear interpolation data of the time axis address immediately after or immediately before the span data (Sb) and higher amplitude level position (D _N t) top side span data defining the span between (S
t) for creating the seam interpolation data, and the first latch circuit 2 for holding the seam interpolation start dot position data (Ds)
A second latch circuit 3 for holding the bottom span data (Sb), a third latch circuit 4 for holding the top dot position data (D _N t) of the linear interpolation data (D _N ), and a top side A fourth latch circuit 5 that holds span data (St), a count value of an address counter 6 that counts a clock that advances the amplitude direction scan for each time axis address N, and a hold value of the first latch circuit 2. There is provided a first comparator 7 that generates an output signal when and match, and a second comparator 8 that generates an output signal when the count value of the address counter 6 and the held value of the third latch circuit 4 match. . By providing the ROM 9a that is stored in advance by comparing the seam luminance interpolation data that gradually changes between the zero luminance level and the predetermined luminance level over the span with the predetermined span data, the ROM 9a that responds to the output signal of the first comparator 7 is provided. Address based on the span data of the second latch circuit 3 and RO
The brightness interpolation data (Dsb) for gradually increasing brightness is output from M9a, and after completion of this output, the brightness interpolation data for a predetermined brightness level is output until the output signal of the second comparator 8 is generated,
After this output is completed, the luminance interpolation data for luminance gradual decrease from the ROM 9a is specified by addressing based on the span data of the fourth latch circuit.
The luminance interpolation data creating means 9 for outputting (Dst) is followed, and the video signal generating circuit 10 converts the luminance interpolation data into an analog signal to generate a video signal.

[Action]

In the seam interpolation data creation means 1, a straight line for sequentially sampling the input waveform signal and connecting the dot positions corresponding to the sampling dot data of each time axis address N and the adjacent time axis addresses N-1 and N + 1 with a bright line based on the interpolation data (D _N), as shown in FIG. 2, bottom defining the span between seam interpolation start dot position (Ds) and the bottom dot location of the linear interpolation data _{(D N) (D N b} ) Side span data (S
b), the seam interpolation end dot position (Df) and linear interpolation data
To create a top-side span data (St) which defines the span between top dot position (D _N t) of (D _N). Latch circuit 2
5 is seam interpolation start dot position data (Ds) and bottom side span data (S
b), top dot position data (D _N t) and top side span data (St) are held respectively. For each time axis address N, the address counter 6 counts the clock for amplitude scanning step, and the count value is the seam interpolation start dot position data (D
s), the comparator 7 generates an output signal, and the luminance interpolation data creating means 9 starts its operation.

That is, reading is carried out from the address of the ROM 9a corresponding to the bottom side span data (Sb) designated by the second latch circuit 3 and the luminance interpolation data for gradually increasing the luminance (Dsb) is obtained.
Supply to 0. When the bottom dot position of the linear brightness interpolation data (D _N ) is reached, the brightness interpolation data (Dsb) disappears, and the comparator 8 detects the coincidence between the count value of the address counter 6 and the top dot position (D _N t). Up to the predetermined brightness level, and then reads from the address of ROM9a corresponding to the top side span data (St) held by the fourth latch circuit 5, and outputs the brightness gradually decreasing brightness interpolation data (Dst). To do. As a result, as shown in FIG. 3, the video signal generation circuit 10 gradually increases the brightness from the joint interpolation start dot position (Ds) corresponding to the bottom dot position of the linear interpolation data of the adjacent time axis address of a lower level. The bright line is displayed while increasing the value, the brightness is kept constant in the original linear interpolation data part, and then the seam interpolation corresponding to the top dot position (D _N t) of the seam linear interpolation data of the next higher time level address is added. The brightness is gradually reduced toward the end dot position (Df). That is, not only can the seam portion be smoothed in the rising or falling region of the waveform, but also the luminance distribution in the direction orthogonal to the amplitude scanning line can be made constant at any bright line position.

Example of Invention

In FIG. 4, the interpolation data creation circuit 20 uses a CPU to sequentially sample the input waveform signal as in the prior art, and connects each time axis address and sampling dot data of adjacent time axis addresses with a bright line. The linear interpolation data (D _N ) of (1) is created and stored, and the seam interpolation data (Ds), (Sb), (D _N t), (St) according to the present invention are based on these data.
Also create. 21 to 24 are digital latch circuits,
The first latch circuit 21 uses the dot position data (D
s), the second latch circuit 22 outputs bottom side span data (Sb)
The third latch circuit 23 outputs the top dot position data (D
The _N t), a fourth latch circuit 24 of the top-side span data (S
hold t) respectively. The clock generation circuit 25 includes a time axis scanning clock, an amplitude direction scanning clock, and a high-speed RO
M Generates a read clock. The address counter 26 counts clocks for scanning in the amplitude direction, and the count values for the first and second comparators 27 and 28 are joint interpolation start dot position data (Ds) and top dot position data (D _N t).
An output signal is generated when the output signals are matched with.

The brightness interpolation data generation means 30 stores joint brightness interpolation data for dividing the predetermined brightness level into four steps and gradually changing the same for the bottom side and top side span data by the number of bytes corresponding to the span. A ROM 31 and a counter 32 for repeatedly generating an address signal for rapidly reading out data of each byte of the ROM 31 when the output signal of the comparator 27 or 28 is output, every time 8 amplitude scanning clocks are input. , A multiplexer 33 for alternately selecting the bottom side and top side span data (Sb) and (St) held by the second latch circuit 22 and the fourth latch circuit 24 and designating an address to be read from the ROM 9a, It comprises a shift register 34 for converting 1 byte of parallel data sequentially output from the ROM 31 into serial data. Reference numeral 35 is a video signal generation circuit that outputs an analog video signal to a cathode ray tube, and has a built-in shift register 35a that changes the brightness level in an analog manner according to input digital brightness interpolation data. Reference numeral 36 denotes a sweep circuit that sequentially shifts in the time axis direction each time the time axis scanning clock is input, and advances by the amplitude direction scanning clock to generate a raster sweep signal.

The ROM 31 has "0" at each time when the luminance signal is changed to the area designated by the span data and the output of the counter 32.
Or, the information of "1" is included. The shift register 34 is
The signal read from the ROM 31 is converted from parallel to serial as the counter 32 advances. Further, the shift register 35a is configured to add signals for each signal indicating a time point of luminance change input serially and generate a stepwise luminance signal.

Next, the operation of the luminance interpolating device for displaying a cathode ray tube waveform thus configured will be described with reference to FIG.

The interpolation data creation circuit 20 creates the linear interpolation data (D _N ) shown in FIG. 5A, and further creates the seam interpolation data, and the latch circuits 21 to 24 are described above each time the time axis address is shifted. 4 kinds of data (Ds), (Sb), (D _N t), (St)
To hold. When the amplitude scanning position reaches the joint interpolation start dot position data (Ds) at each time axis address N, the comparator 27 responds to the count value of the address counter 26 at that time.
Generates an output signal, and the counter 32 starts generating an address signal for repeatedly reading the ROM 31 byte by byte. As a result, the brightness interpolation data (Dsb) of the ROM 31 at the address corresponding to the bottom side span data (Sb) selected by the multiplexer 33 is read byte by byte, and when this read is completed, the counter 32 continues to read 0 level data. Let the output continue. When the amplitude scanning position reaches the top dot position data (D _N t), the comparator 28 is reset, the counting operation is performed again, and the top side span data (St) switched by the multiplexer 33 is read.

In this way, the parallel luminance interpolation data shown in FIG. 5b read from the ROM 31 for each time-axis address N.
(Dsb), (D _N ), and (Dst) are converted by the shift register 34 into serial 0, 1 level luminance interpolation data shown in FIG. In response to this, in the shift register 35a, every time the logic level is inverted, the output level of the associated stage becomes 1, and these are added to generate the analog luminance signal shown in FIG. It is amplified and supplied to the CRT circuit. That is, a luminance interpolation signal that gradually increases in a stepwise manner is generated first, and then a 0 level continues in the linear interpolation area to reach a predetermined luminance level. Thereafter, each time the logical level changes, the output level of the associated stage of the shift register 35a. When 0 becomes 0, a luminance signal that gradually decreases is output. In this way, for each time axis address,
As shown in FIG. 5E, waveform drawing is performed in which the seams of the bright lines with respect to the preceding and following time axis addresses are smoothly luminance interpolated.

Incidentally, in the luminance interpolation data generating means according to the above-mentioned embodiment,
The ROM is configured to store common data for the same amount of span regardless of gradual increase or decrease, but the circuit configuration is based on the assumption that gradual increase or decrease slope information is stored. Can also be considered. Although the peripheral circuit of the ROM is configured as a hard logic circuit, the data in the ROM can be serially output using the CPU.
The brightness change level is set to four steps, but the number of steps can be increased or decreased, and a smooth slope waveform can be obtained by smoothing step waves or using a sawtooth wave generation circuit.

〔The invention's effect〕

As described above, according to the present invention, the storage capacity of the video signal RAM can be greatly increased because the video signals accompanied by the brightness interpolation can be sequentially generated at the time of display only by storing the sampling data of each time axis address in the RAM. Further, since the luminance interpolation of the seam can be performed in a state where the luminance is constant at any bright line position by the video signal whose level is gradually changed, a smoother bright line display is possible.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a luminance interpolating device for displaying a cathode ray tube waveform according to the present invention, FIGS. 2 and 3 are diagrams for explaining its operation, and FIG. 4 is a luminance for displaying a cathode ray tube waveform according to an embodiment of the present invention. FIG. 5 and FIG. 5 are diagrams for explaining the operation of the circuit configuration of the interpolator.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location G09G 1/00 T 9060-5G 1/16 A 9060-5G

Claims (1)

[Claims] 1. An input signal waveform is sequentially sampled to create sampling dot data corresponding to the amplitude for each time axis address on the display surface of a cathode ray tube, and a bright line is drawn between areas corresponding to the sampling dot positions of adjacent time axis addresses. In the luminance interpolator for CRT waveform display, which is used to perform complementary luminance interpolation at the joints of bright lines when performing linear interpolation and displaying waveforms, the adjacent time axis address for the linear interpolation data of each time axis address The bottom side span data (Sb) and the bottom side span data (Sb) that define the span between the bottom dot position (D _N b) of the linear interpolation data and the seam interpolation start dot position corresponding to the bottom dot position (Ds) of the bottom side linear interpolation data of Top dot position of top side linear interpolation data of adjacent time axis address
(Df) seam interpolation end dot position and seam interpolation data creating means for creating top side span data (St) that defines the span between the top dot position (D _N t) of the linear interpolation data, and the seam A first latch circuit that holds the interpolation start dot position data (Ds), a second latch circuit that holds the bottom side span data (Sb), and the top dot position data (D _N t) of the linear interpolation data. ), A fourth latch circuit for holding the top side span data (St), and an address counter for counting a clock for advancing the amplitude direction scan for each time axis address. A first comparator that generates an output signal when the count value and the holding value of the first latch circuit match, and a first comparator that generates an output signal when the count value and the holding value of the third latch circuit match. And a ROM that stores joint luminance interpolation data that gradually changes between a zero luminance level and a predetermined luminance level corresponding to the span in order to compare with the span data.
In response to the output signal of the first comparator, the joint luminance interpolation data corresponding to the span data held in the second latch circuit is read from the ROM to output luminance incremental data for luminance increase, After this output is finished, the luminance interpolation data for the predetermined luminance level is output until the output signal of the second comparator is generated, and after this output is finished, the seam corresponding to the span data held in the fourth latch circuit. It is provided with a brightness interpolation data generating means for reading the brightness interpolation data from the ROM and outputting the brightness interpolation data for gradually decreasing brightness, and a video signal generating circuit for analogizing the brightness interpolation data to generate a video signal. Luminance interpolator for CRT waveform display.