JPH0634206B2 - Incremental data transfer device for linear interpolator - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an incremental data transfer device for a linear interpolator, and more specifically, it obtains incremental data by a divider based on given coordinate values of two points. In a linear interpolator that performs linear interpolation between two points by cumulatively adding the increment data to the coordinate value data of any one point by the adder, the increment data obtained by the divider is added to the adder. The present invention relates to an incremental data transfer device for transferring a linear interpolator.

<Prior Art> Conventionally, a linear interpolator used in a graphic display device or the like includes a divider for obtaining increment data and an adder for cumulatively adding increment data to predetermined reference data. The thing of the structure is adopted.
Recently, the divider and the adder are provided as separate ICs.
Then, a linear interpolator having a structure in which both ICs are connected by a parallel data bus has come to be provided.

More specifically, as shown in FIG. 3, the divider IC (5) has a quotient register (51) for storing the division result and a register (52) for storing other data. In addition, the data stored in both registers (51) and (52) is output to the parallel data bus (6) through the buffer (53), and the adder side IC (7) has the parallel The data transferred through the data bus (6) is input through the buffer (71) to the reference register (72) that stores predetermined reference data and the increment register (73) that stores incremental data to be cumulatively added. I am trying.

<Problems to be Solved by the Invention> In the above-described conventional linear interpolator, for example, predetermined increment data is calculated by a divider based on the coordinate values of two points and the number of intermediate points to be interpolated, and the addition is performed. With the instrument, incremental data can be cumulatively added to the coordinate value of one point to perform linear interpolation between two points.

More specifically, the divider-side IC (5) obtains the division result by performing the necessary number of subtraction trials, and stores the division result in the quotient register (51) provided in the divider-side IC (5). The division result stored in the quotient register (51) is transferred to the adder side IC (7) by a predetermined number of bits by the parallel data bus (6).

Therefore, by performing a predetermined number of subtraction trials, the obtained data for each bit is only sequentially stored in the quotient register (51) until the division operation is completed, and the parallel operation is performed after the division operation is completed. The data bus (6) transfers the division result to the adder side IC (7). Then, after all the division results have been transferred, the adder-side IC
The cumulative addition operation according to (7) will be performed.

That is, the sum of the above operation times becomes the operation time of the linear interpolator, and when the division result can be transferred at a time by the parallel data bus (6), the operation for transferring the division result Although the time can be shortened, the number of pins on the IC (5) on the divider side and the IC (7) on the adder side increases, especially when the number of digits in the division result is large. There is a problem.

It is also possible to reduce the number of pins, but in this case, the division result must be transferred in multiple times for each predetermined number of bits determined by the number of pins. However, there is a problem that the operating time of is long.
Particularly in a graphic display device, since it is required to increase the speed of performing linear interpolation to increase the drawing speed, it is strongly desired to shorten the operation time for transferring the division result.

<Objects of the Invention> The present invention has been made in view of the above problems,
An object of the present invention is to provide an incremental data transfer device for a linear interpolator that can significantly reduce the operation time for transferring a division result as incremental data to an adder side IC without increasing the number of IC pins. .

<Means for Solving the Problems> In order to achieve the above object, an incremental data transfer device for a linear interpolator according to the present invention has a divider and an adder as separate ICs.
In addition, a quotient register in which the division result by the divider is sequentially stored in bit units is provided in the adder-side IC, and the division result stored in the quotient register by the internal transfer of the adder-side IC is used as incremental data. The data is transferred to the increment register.

<Operation> In the case of the linear interpolator incremental data transfer device having the above configuration, the subtraction circuit of the IC on the divider side performs a predetermined number of times of subtraction trials to obtain a division result of a predetermined number of digits,
This division result is stored in the quotient register of the IC on the adder side each time data of each digit is obtained by performing a subtraction trial, and when the division operation is completed, the division result stored in the quotient register is used as increment data. Transfer internally to the increment register. Then, the incremental data stored in the increment register is cumulatively added to predetermined reference data, so that linear interpolation between two points can be performed.

<Example> Hereinafter, detailed description will be given with reference to the accompanying drawings illustrating an example.

FIG. 1 is a block diagram showing a main part of an embodiment of a linear interpolator, which includes an IC (1) on a divider side and a parallel data bus (2).
And an adder side IC (3).

More specifically, the divider IC (1) includes a quotient register (11) in which a division result obtained by a division circuit (not shown) is stored for each bit, and data other than the division result (for example, a reference Data register (12) for storing the coordinate data of the
The data stored in (12) is selectively output to the parallel data bus (2) through the buffer (13). Then, the quotient register (11) is supplied with the clock signal and the division result which is sequentially sent bit by bit.

In addition, (14) and (15) are the above clock signal lines, 1 respectively.
It is a buffer inserted in the data line bit by bit.

The adder side IC (3) is the parallel data bus (2)
The data input via the buffer (31) is selectively input to the reference register (32) and the increment register (33). Further, it has a quotient register (34) to which data is input bit by bit in synchronization with the quotient register (11), and the division result stored in the quotient register (34) is internally transferred to an increment register (33). To be able to transfer to.

The linear interpolator having the above-described configuration calculates the increment value based on the coordinate values of the two points input by the input means (not shown) and the number of intermediate points to be interpolated between these two points. For example, a subtraction trial is performed a predetermined number of times to obtain a division result. The division result is stored bit by bit in the quotient register (11) of the divider IC (1), and at the same time, also stored in the quotient register (34) of the adder IC (3) bit by bit. . Therefore, when the total division result is stored in the quotient register (11) of the divider IC (1), the total division result is also stored in the quotient register (34) of the adder side IC (3) almost at the same time.

After that, all division results are temporarily transferred as incremental data by internal transfer from the quotient register (34) of the adder side IC (3) to the increment register (33), and the buffer (13) and parallel data bus (2) are transferred. , And the reference register (3
By performing the cumulative addition operation on the reference data stored in 2), linear interpolation between two points can be performed.

In summary, since the transfer of the reference data is performed by the parallel data bus even in the conventional device, there is no particular disadvantage. Specifically, in the above embodiment, for example, while the reference data is transferred in parallel, the division result serially transferred to the quotient register (34) of the adder side IC (3) in advance is added to the increment register.
Since it is stored in (33), the time required as a whole can be shortened.

Regarding the transfer of the division result, since the data obtained bit by bit can be sequentially stored in the quotient register (34) of the IC (3) on the adder side while performing the division operation, the division operation Compared to transferring the entire division result to the increment register (33) through the parallel data bus (2) after completion, the time required specially for the division result transfer can be significantly reduced, and Since the parallel data bus is not exclusively used, another data transfer can be performed during the above transfer operation. And, to shorten the time for transferring the division result, the number of pins of both ICs (1) and (3) is reduced to reduce the number of bits that can be transferred simultaneously by the parallel data bus (2). In particular, it becomes particularly noticeable.

In the above embodiment, since the IC (1) on the divider side has the quotient register (11), even if an IC on the adder side which does not have the quotient register (34) is used, there is no problem. Two
Linear interpolation between points can be performed. However, in this case, the reduction in time as described above cannot be achieved.

Further, when the required number of digits in the division operation is known in advance, the number of subtraction trials for division can be reduced and the time required for the division operation can be shortened.

When the required number of digits is smaller than the number of digits that can be stored in the quotient register (34), the time required to store data in the quotient register (34) can be shortened as follows.

FIG. 2 is an electric circuit diagram showing the configuration of the quotient register (34), and selectors (35a) (35b) ... (35) corresponding to the data of each digit.
n) and latch circuits (36a) (36b) ... (36n). The output data C from the division circuit (not shown) is passed through the buffer (37) to the selectors (35a) (35b) ... (35n).
One of the input terminals is input, and the output data from the upper digit latch circuit is input to the other input terminal of the selector. Further, the clock signal CLK is input to the clock input terminals of the respective latch circuits (36a) (36b) ... (36n) through the buffer (38), and the load signal LD is also transmitted through the buffer (39). 36a) (36
b) Inputting to the clear terminal of (36n). Further, a register (40) to which a store pointer SP determined by a divisor, a dividend, etc. is input by the load signal LD, and a decoder (41) to which the store pointer SP stored in this register (40) is input. By inputting the decode signal to the select input terminals of the selectors (35a) (35b) ... (35n), only one predetermined selector inputs the output data C to the corresponding latch circuit. There is.

Therefore, as compared with the case of the conventional quotient register which needs to store the output data C in order from the least significant digit or the most significant digit and perform the shift corresponding to the unnecessary digit,
The time required for storing the division result can be shortened.

Note that the present invention is not limited to the above-described embodiment, and for example, the quotient register of the divider side IC (1) can be omitted, and other various modifications are possible within the scope not changing the gist of the present invention. It is possible to change the design of.

<Effects of the Invention> As described above, the present invention suppresses an increase in the number of pins of the divider-side IC and the adder-side IC, and significantly shortens the time required to transfer the division result used as the increment data. Further, the processing speed of the linear interpolator can be increased, and when applied to a graphic display device, the drawing speed can be increased, which is a unique effect.

[Brief description of drawings]

FIG. 1 is a block diagram showing an essential part of an embodiment of a linear interpolator, FIG. 2 is an electric circuit diagram showing an example of a quotient register, and FIG. 3 is a block diagram showing an essential part of a conventional linear interpolator. (1) ... IC on divider side, (3) ... IC on adder side, (33) ... Incremental register, (34) ... Quotation register

Claims (1)

[Claims] 1. A linear interpolator having a divider for calculating incremental data for performing linear interpolation between two points and an adder for cumulatively adding the incremental data to the coordinate value of one point. , The divider and the adder are configured as separate ICs, and a quotient register in which the division result by the divider is sequentially stored in bit units is provided in the adder-side IC, and the internal transfer of the adder-side IC is performed. A data transfer device for a linear interpolator, wherein a division result stored in a quotient register is transferred to the increment register as incremental data.