JPH0634353B2 - Semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a signal voltage detection circuit that operates at high speed and occupies a small area.

[Prior art]

Conventionally, this type of semiconductor memory device has been configured as shown in FIG. 1 by taking a one-transistor dynamic MOSRAM as an example. In FIG. 1, 1 is a memory cell, 2 is a signal line, 3 is a signal amplifier circuit, 4 is a precharge circuit 4-1 of the signal line 2 and a refresh circuit 4-2 and 5 are data input / output circuits, 3 and The portion 4 constitutes a signal voltage detection circuit. The semiconductor memory device further includes an address circuit, various control circuits, and the like, which are omitted here.

In FIG. 1, the voltage of the signal line 2 can take two values, a high voltage state and a low voltage state, depending on the information of the selected memory cell.
By comparing these two states with the reference voltage V _R , the amplifier circuit 3 detects and amplifies the data, and the data is read out to the outside through the input / output circuit 5. Here, the difference between the high voltage and the low voltage of the signal line 2 will be referred to as a signal voltage. Clock φ in amplifier circuit 3
_The signal voltage is slowly amplified by _D1 , and then amplified at high speed by φ _D2 . In the 1-transistor type RAM, this signal voltage is the capacitance C _S of the memory cell 1 and the capacitance C _{B of the} signal line 2.
It is determined by the ratio C _B / C _S with C _B / C _S , and the smaller C _B / C _S is, the larger the signal voltage is obtained. Since C _S decreases and the memory cell area capacity progresses decreases, the signal voltage decreases. Therefore, the signal voltage detection circuit needs to be configured to be able to amplify a small signal voltage without malfunction. For the signal voltage detection circuit, it is required that the minimum detectable signal voltage is small and the operation speed is fast, but generally, these two are in a contradictory relationship. Therefore, the configuration shown in FIG. 1 has a problem that the minimum signal voltage that can be detected becomes small as the capacity increases, and the operation time becomes extremely long.

In order to solve this, conventionally, a configuration has been considered in which a signal line is divided and a signal voltage detection circuit is provided for each.
FIG. 2 shows an example of the configuration, which is an example in which the signal line 2 is divided into four. In FIG. 2, which signal line is selected is controlled by the switch circuit 6. In this configuration, C _B decreases, so the signal voltage increases, and the requirement for the minimum detectable voltage of the signal voltage detection circuit is relaxed.
A high-speed signal voltage detection circuit can be constructed. However, in this case, although the area of each signal voltage detection circuit is smaller than that in FIG. 1, as the number of signal voltage detection circuits increases, especially as the number of divisions increases due to the increase in capacity, There is a drawback that the number of transistors in the signal voltage detection circuit increases in proportion.

[Object of the Invention]

In order to eliminate these drawbacks, the present invention divides a signal line to provide a preamplifier for each division unit, and connects the divided signal lines in series with an electric switch to provide a main amplifier, a precharge circuit, The purpose is to share the refresh circuit and the like.

Example of Invention

FIG. 3 shows an embodiment of the present invention in which the signal line is divided into 2-1 to 2-5 and four repeating unit circuits 9 are connected. Each repeating unit circuit 9 is composed of a plurality of memory cells 1, an amplifier circuit (preamplifier) 3-1, and a switch 7 that connects and disconnects a signal line. 8 is a switch for transmitting the clock φ _D1 to one of the preamplifiers 3-1, φ _X
Is the control signal. 3-2 is a main amplifier,
The preamplifier 3-1 and the main amplifier correspond to the amplifier circuit 3 in FIG.

Next, the operation of FIG. 3 will be described with reference to the waveform chart of FIG. First, set φ _C to high level, and repeat each unit circuit 9
The switch 7 is turned on and each signal line 2-1 to 2-5
Are pre-charged by the common pre-charge circuit 4-1.
After that, φ _{C is set} to a low level and each switch 7 is turned off. Next, only one memory cell is selected from the memory cells 1 belonging to the four repeating unit circuits 9, a signal voltage appears on the signal line 2-i (where i = 1 to 4), and selected. The clock φ _D1 for driving the preamplifier 3-1 provided to the signal line 2-i to which the memory cell belongs is activated by the switch 8 to start the detection amplification operation. Next, each switch 7 is turned on, further amplified by the main amplifier 3-2, and data is read out through the input / output circuit 5.

In the configuration of FIG. 3, since the signal line is separated by the switch 7 during the detection / amplification operation of the signal voltage, the effective signal line capacitance C _B ′ becomes small, so that the signal voltage becomes large and the sensitivity is increased. Therefore, it is not necessary to take a complicated configuration for the purpose, and the operation speed can be increased. When the switch 7 is turned on, the effective signal line capacitance becomes as large as 4C _B ′, but at this time, the signal voltage is sufficiently amplified and the operation of the main amplifier 3-2 can be performed at high speed. Further, as shown in the drawing, the signal voltage detection circuit is partially arranged in a distributed manner, but the others are common, so that the area is smaller than that in the configuration of FIG. Therefore, a high-speed amplification operation can be realized with a circuit having a small area.

FIG. 5 shows another embodiment of the present invention, which is different from FIG. 3 in that a P-channel transistor is used in the preamplifier 3-1 'arranged in each repeating unit circuit 9 for presense operation and refresh. This is also used as an active restore operation (which is performed by the refresh circuit 4-2 in FIG. 3). In this case, φ _D1 is a clock with opposite polarity.

FIG. 6 shows another embodiment of the present invention, in which only the portion (9) 'corresponding to the repeat unit circuit 9 of FIG. 3 is shown. That is, FIG. 6 is two connected repeating unit circuit 9 ', by interchanging clock phi _C1 and phi _C2 of one repeating unit circuit, an example in which a 4-division constituting the signal line. In this configuration, two memory cell groups share one preamplifier 3-1 and therefore, there is an advantage that the number of preamplifiers 3-1 is half that in FIG. However, in this case, two clocks φ _C1 and φ _C2 are required instead of the clock corresponding to φ _C in FIG. FIG. 7 shows the waveform of the clock when a memory cell belonging to the memory cell group on the left side in FIG. 6 is selected. The operation is as follows after one of the memory cells 1 is selected.
φ _C rises to generate a signal voltage in the preamplifier 3-1, and φ _D1 amplifies the signal voltage. Then, after φ _C2 is started up, the amplification operation is completed by the main amplifier drive clock φ _D2 (not shown in FIG. 6).

Now, compare the number N of transistors in FIGS. 2 and 6. If the number of transistors of the switch 6 is 4, the number of transistors of the preamplifier selection switch 8'is 2, and the memory cell is excluded and the signal line is divided into n, in the conventional example of FIG. 2, N = 6n + 5, 6th In the illustrated embodiment, N = 3
n + 10 (including refresh circuit, precharge circuit, main amplifier), 53:34 at n = 8, and n = 16
It becomes 101 to 58. As a result, as the number of divisions increases, the number of elements is reduced to about 1/2, and it can be seen that the area can be significantly reduced compared to the conventional type.

〔The invention's effect〕

As described above, according to the semiconductor memory device of the present invention, since the plurality of memory cells are connected and the signal line for extracting the memory information of the selected memory cell as the signal voltage is divided, the effective signal line There is an advantage that the capacity becomes small and therefore the signal voltage becomes large and a high-speed signal voltage amplifying operation can be performed. Also, the amplifier circuit has a two-stage configuration of a preamplifier and a main amplifier, and only the preamplifier is provided for each divided signal line, and the main amplifier is shared, so high-speed amplification operation can be realized with a circuit with a small area as a whole. Becomes

[Brief description of drawings]

1 and 2 are diagrams showing a configuration example of a conventional semiconductor memory device, FIG. 3 is a diagram showing an embodiment of the present invention, and FIG. 4 is a signal waveform for explaining the operation of FIG. FIGS. 5, 5 and 6 are diagrams showing another embodiment of the present invention, and FIG. 7 is a signal waveform diagram for explaining the operation of FIG. 1 ... storage cell, 2 ... signal line, 3 ... amplification circuit, 3-
1 ... Preamplifier, 3-2 ... Main amplifier, 4-1 ...
… Precharge circuit, 4-2 …… Reflection circuit, 5
...... Input / output circuit, 6 ... Switch (signal line selection), 7 ...
Switch (divided signal line connection), 8 switch (preamplifier), 9 repeat unit circuit.

Claims (1)

[Claims] 1. A plurality of storage cells, a signal line connected to the plurality of storage cells and for extracting stored information of a selected storage cell as a signal voltage, and at least an amplifier circuit connected to the signal line. In a semiconductor memory device having a precharge circuit, the amplifier circuit has a two-stage configuration of a preamplifier and a main amplifier, the signal line is divided, and the preamplifier is provided for each memory cell group included in the divided signal line. A semiconductor memory device provided with the divided signal lines connected in series via a switch circuit, and the signal line connected to the main amplifier and precharge circuit common to the plurality of memory cells.