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JPH0634438B2 - Wiring electrode formation method - Google Patents
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JPH0634438B2 - Wiring electrode formation method - Google Patents

Wiring electrode formation method

Info

Publication number
JPH0634438B2
JPH0634438B2 JP61210200A JP21020086A JPH0634438B2 JP H0634438 B2 JPH0634438 B2 JP H0634438B2 JP 61210200 A JP61210200 A JP 61210200A JP 21020086 A JP21020086 A JP 21020086A JP H0634438 B2 JPH0634438 B2 JP H0634438B2
Authority
JP
Japan
Prior art keywords
wiring electrode
forming
conductive layer
resist
resist pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61210200A
Other languages
Japanese (ja)
Other versions
JPS6364081A (en
Inventor
祥治 市川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP61210200A priority Critical patent/JPH0634438B2/en
Publication of JPS6364081A publication Critical patent/JPS6364081A/en
Publication of JPH0634438B2 publication Critical patent/JPH0634438B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Manufacturing Of Printed Wiring (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は配線電極の形成方法に関し、特にアクティブマ
トリクスアレイ等に使用する断線が起こりにくい配線電
極の形成方法に関する。
Description: TECHNICAL FIELD The present invention relates to a method for forming a wiring electrode, and more particularly to a method for forming a wiring electrode used in an active matrix array or the like, in which disconnection does not easily occur.

〔従来の技術〕[Conventional technology]

近年オフィスオートメーションの進展に伴い、マンマシ
ンインターフェイスとしての平板表示デバイスの開発が
活発に進められている。液晶ディスプレイ装置において
もCRTと同等の高い表示情報量を得るためアクティブ
マトリクス基板の開発が盛んである。アクティブマトリ
クス基板では1画素に1つのアクティブ素子を使用する
ため、大面積にわたり細い配線電極を形成する必要があ
る。
With the progress of office automation in recent years, development of a flat panel display device as a man-machine interface has been actively promoted. Also in liquid crystal display devices, active matrix substrates are being actively developed in order to obtain a large amount of display information equivalent to that of CRTs. Since one active element is used for one pixel in the active matrix substrate, it is necessary to form thin wiring electrodes over a large area.

第2図(a)〜(c)は従来の配線電極の形成方法の一
例を工程順に示した模式的断面図である。第2図(a)
に示すように絶縁基板1上に第1の導電膜2と第2の導
電膜4を順々に形成する工程と、第2図(b)に示すよ
うに第2の導電膜4上にホトレジスト法により配線電極
用のレジストパターン3を形成する工程と、第2図
(c)に示すように第2および第1の導電膜4および2
を順々にエッチングした後レジストを除去する工程とか
らなっていた。この形成方法の場合、第1の導電膜2は
絶縁基板1との接着性の良いものを、第2の導電膜4は
電気的特性の良好なものを用いることが多いが、両者を
満たす導電膜があるときは当然1層のみの導電膜が用い
られる。
2A to 2C are schematic cross-sectional views showing an example of a conventional method of forming a wiring electrode in the order of steps. Fig. 2 (a)
As shown in FIG. 2B, a step of sequentially forming the first conductive film 2 and the second conductive film 4 on the insulating substrate 1, and a photoresist on the second conductive film 4 as shown in FIG. 2B. A step of forming a resist pattern 3 for a wiring electrode by a method, and second and first conductive films 4 and 2 as shown in FIG.
And the resist was removed in order. In the case of this forming method, the first conductive film 2 often has good adhesiveness to the insulating substrate 1, and the second conductive film 4 often has good electric characteristics. When there is a film, naturally only one conductive film is used.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

このような配線電極の形成方法を用いてアクティブマト
リクス基板を製造すると、レジストパターン3や第1,
第2の導電膜2,4に欠陥があると断線となるため歩留
まりが非常に悪いという欠点があった。
When an active matrix substrate is manufactured using such a wiring electrode forming method, the resist pattern 3
If there is a defect in the second conductive films 2 and 4, there is a drawback that the yield is very poor because the wire breaks.

本発明の目的は、このような従来の欠点を除去し、断線
が起こりにくい配線電極の形成方法を提供することにあ
る。
An object of the present invention is to eliminate such a conventional defect and provide a method for forming a wiring electrode in which disconnection does not easily occur.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の配線電極の形成方法は、絶縁基板上に第1の導
電層を形成する工程と、この第1の導電層上にホトレジ
スト法により第1の配線電極用レジストパターンを形成
する工程と、前記第1の導電層をエッチングによりパタ
ーニングした後レジストを除去する工程と、第2の導電
層を形成する工程と、この第2の導電層上にホトレジス
ト法により前記第1の配線電極と形状は同じでわずかに
幅の違う第2の配線電極用レジストパターンを形成する
工程と、前記第1の導電層はほとんどエッチングしない
エッチャントを用いて前記第2の導電層をエッチングに
よりパターニングした後レジストを除去する工程を備え
ている。
A method of forming a wiring electrode according to the present invention comprises a step of forming a first conductive layer on an insulating substrate, a step of forming a first wiring electrode resist pattern on the first conductive layer by a photoresist method, The step of removing the resist after patterning the first conductive layer by etching, the step of forming the second conductive layer, and the step of forming the first wiring electrode and shape on the second conductive layer by the photoresist method are performed. Forming a second wiring electrode resist pattern having the same width but slightly different width; and etching the second conductive layer using an etchant that hardly etches the first conductive layer, and then removing the resist It has a process to do.

〔作用〕[Action]

本発明の配線電極の形成方法を用いれば、第1の導電層
と第2の導電層を2回に分けてパターニングし、しかも
第2の導電層のパターンエッチングのとき第1の導電層
はエッチングされない。このため第1回目のレジストパ
ターンや第1の導電層に欠陥があっても第2回目のレジ
ストパターンや第2の導電層の欠陥が前者と同一の場所
にない限り断線とはならない。前者と後者で同一の場所
に欠陥が発生する確立は極めて低く、したがって配線電
極の断線はほとんど起こらない。なお欠陥としては導電
層が部分的に残る場合もあるが、液晶ディスプレイに用
いるアクティブマトリクスアレイでは配線電極幅に比べ
て1画素のピッチは10倍程度あるため、導電層の残り
がディスプレイとしての欠陥となることはほとんどな
い。
If the method for forming a wiring electrode of the present invention is used, the first conductive layer and the second conductive layer are patterned in two steps, and the first conductive layer is etched when the second conductive layer is pattern-etched. Not done. Therefore, even if there is a defect in the first resist pattern or the first conductive layer, the disconnection does not occur unless the defect in the second resist pattern or the second conductive layer is in the same place as the former. The probability that defects will occur at the same location in the former and the latter is extremely low, and therefore, the wiring electrodes are hardly broken. Although the conductive layer may partially remain as a defect, since the pitch of one pixel is about 10 times the wiring electrode width in the active matrix array used for a liquid crystal display, the rest of the conductive layer is a defect as a display. Is rarely.

〔実施例〕 次に、本発明について実施例をもって詳細に説明する。EXAMPLES Next, the present invention will be described in detail with examples.

素子数400×640,表示面積180mm×240mmの
液晶表示装置用薄膜トランジスタアレイのゲート電極配
線に本発明の配線電極の形成方法を実施した場合と従来
の配線電極の形成方法を実施した場合とを比較して説明
する。
Comparison between the case where the method of forming the wiring electrode of the present invention is applied to the gate electrode wiring of the thin film transistor array for a liquid crystal display device having the number of elements of 400 × 640 and the display area of 180 mm × 240 mm, and the case where the conventional method of forming the wiring electrode is performed. And explain.

第1図(a)〜(f)は本発明の配線電極の形成方法の
一実施例を工程順に示した模式的断面図である。
1 (a) to 1 (f) are schematic cross-sectional views showing an embodiment of a method of forming a wiring electrode according to the present invention in the order of steps.

本実施例は、第1図(a)に示すように絶縁基板1とし
てソーダガラスを用い、この上に第1の導電層2として
クロムを400Åの厚さに直流アルゴンスパッタ法によ
り形成し、第1図(b)に示すようにポジ型ホトレジス
ト法により15μm幅の配線電極のレジストパターン3
を形成した。次に第1図(c)に示すようにクロムを硝
酸セリウムアンモニウム塩を主成分とするエッチング液
でパターンエッチングしたあとレジストを除去した。そ
して第1図(d)に示すように第2の導電層4としてア
ルミニウムを600Åの厚さに蒸着法により形成し、第
1図(e)に示すようにポジ型ホトレジスト法により2
5μm幅の配線電極のレジストパターン3を形成した。
最後に第1図(f)に示すようにアルミニウムをリン酸
を主成分とするエッチング液でパターンエッチングした
後レジストを除去してゲート配線電極を形成した。この
ときゲート配線電極の断線は全く見られなかった。導電
層の残りは5〜25μmφのものが23個、25μmφ
以上のものが2個あったが、ゲート配線電極のピッチは
375μmであるためほとんど問題とならなかった。
In this embodiment, as shown in FIG. 1A, soda glass is used as the insulating substrate 1, and chromium is formed as the first conductive layer 2 on the insulating substrate 1 to a thickness of 400 Å by the direct current argon sputtering method. As shown in FIG. 1B, the resist pattern 3 of the wiring electrode having a width of 15 μm is formed by the positive photoresist method.
Was formed. Next, as shown in FIG. 1 (c), chromium was pattern-etched with an etching solution containing cerium ammonium nitrate as a main component, and then the resist was removed. Then, as shown in FIG. 1 (d), aluminum is formed as the second conductive layer 4 to a thickness of 600 Å by vapor deposition, and as shown in FIG. 1 (e), aluminum is formed by a positive photoresist method.
A resist pattern 3 of a wiring electrode having a width of 5 μm was formed.
Finally, as shown in FIG. 1F, aluminum was pattern-etched with an etching solution containing phosphoric acid as a main component, and then the resist was removed to form a gate wiring electrode. At this time, no disconnection of the gate wiring electrode was observed. The rest of the conductive layers are 5 to 25 μmφ, 25 μmφ
There were two of the above, but there was almost no problem because the pitch of the gate wiring electrodes was 375 μm.

一方、第2図(a)〜(c)に示した従来の配線電極の
形成方法を用いると、ゲート配線電極の断線が2本存在
し、この基板を使用して薄膜トランジスタアレイを形成
し液晶ディスプレイとした場合には断線欠陥となってし
まった。
On the other hand, when the conventional method of forming a wiring electrode shown in FIGS. 2A to 2C is used, there are two disconnections of the gate wiring electrode, and a thin film transistor array is formed using this substrate to form a liquid crystal display. In that case, a disconnection defect has occurred.

〔発明の効果〕〔The invention's effect〕

以上説明したように本発明の配線電極の形成方法は、第
1,第2の導電層の形成工程および第1,第2の配線電
極用レジストパターンの形成工程のどの工程で欠陥であ
っても同一の場所で起こる確率が極めて低いため断線と
はならず、極めて断線が起こりにくい配線電極を形成す
ることができるという効果を有する。
As described above, the method of forming a wiring electrode according to the present invention can be performed in any of the steps of forming the first and second conductive layers and the step of forming the resist patterns for the first and second wiring electrodes. Since the probability of occurrence at the same place is extremely low, disconnection does not occur, and it is possible to form a wiring electrode in which disconnection does not occur easily.

【図面の簡単な説明】[Brief description of drawings]

第1図(a)〜(f)は本発明の配線電極の形成方法の
一実施例を工程順に示した模式的断面図、第2図(a)
〜(c)は従来の配線電極の形成方法の一例を工程順に
示した模式的断面図である。 1……絶縁基板、2……第1の導電層、3……レジスト
パターン、4……第2の導電層。
1 (a) to 1 (f) are schematic cross-sectional views showing one embodiment of the method for forming a wiring electrode of the present invention in the order of steps, and FIG. 2 (a).
8A to 8C are schematic cross-sectional views showing an example of a conventional method of forming a wiring electrode in the order of steps. 1 ... Insulating substrate, 2 ... First conductive layer, 3 ... Resist pattern, 4 ... Second conductive layer.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】絶縁基板上に第1の導電層を形成する工程
と、この第1の導電層上にホトレジスト法により第1の
配線電極用レジストパターンを形成する工程と、前記第
1の導電層をエッチングによりパターニングした後レジ
ストを除去する工程と、第2の導電層を形成する工程
と、この第2の導電層上にホトレジスト法により前記第
1の配線電極と形状は同じでわずかに幅の違う第2の配
線電極用レジストパターンを形成する工程と、前記第1
の導電層はほとんどエッチングしないエッチャントを用
いて前記第2の導電層をエッチングによりパターニング
した後レジストを除去する工程を含むことを特徴とする
配線電極の形成方法。
1. A step of forming a first conductive layer on an insulating substrate, a step of forming a resist pattern for a first wiring electrode on the first conductive layer by a photoresist method, and the first conductive layer. A step of patterning the layer by etching and then removing the resist; a step of forming a second conductive layer; and a step of forming a second conductive layer on the second conductive layer by a photoresist method, which has the same shape as the first wiring electrode and is slightly wide. Forming a resist pattern for a second wiring electrode having a different pattern;
The method of forming a wiring electrode according to claim 1, further comprising the step of removing the resist after patterning the second conductive layer by etching using an etchant that hardly etches.
JP61210200A 1986-09-05 1986-09-05 Wiring electrode formation method Expired - Lifetime JPH0634438B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61210200A JPH0634438B2 (en) 1986-09-05 1986-09-05 Wiring electrode formation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61210200A JPH0634438B2 (en) 1986-09-05 1986-09-05 Wiring electrode formation method

Publications (2)

Publication Number Publication Date
JPS6364081A JPS6364081A (en) 1988-03-22
JPH0634438B2 true JPH0634438B2 (en) 1994-05-02

Family

ID=16585443

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61210200A Expired - Lifetime JPH0634438B2 (en) 1986-09-05 1986-09-05 Wiring electrode formation method

Country Status (1)

Country Link
JP (1) JPH0634438B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0814668B2 (en) * 1988-02-16 1996-02-14 シャープ株式会社 Matrix type liquid crystal display panel
JP2015076470A (en) * 2013-10-08 2015-04-20 トヨタ自動車株式会社 Semiconductor device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6143449A (en) * 1984-08-08 1986-03-03 Hitachi Ltd Forming process of wiring pattern
JPS6230396A (en) * 1985-07-31 1987-02-09 ソニー株式会社 Circuit pattern formation
JPS62111494A (en) * 1985-11-11 1987-05-22 株式会社日立製作所 Manufacture of printed circuit board

Also Published As

Publication number Publication date
JPS6364081A (en) 1988-03-22

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