JPH0635992B2 - Trigger generation circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a trigger generation circuit, and more specifically,
In a measuring instrument having a built-in memory for recording or observing an input waveform of an analog signal or a logic signal, a trigger generation circuit for storing the input waveform in a memory at a desired time or stopping the storage operation at the desired time Is.

[Prior Art] In a high-speed recorder or observation device that draws both analog and logic input signal waveforms on recording paper or displays them on a cathode ray tube, detailed analysis is added to a part of the input waveform. Often, the waveform data of a desired portion is stored in a memory so that it can be reproduced later. In this case, the writing of the waveform data to the memory is usually performed by a microcomputer (hereinafter, "CP
U ”. ), These instruments are provided with a trigger generation circuit for instructing the CPU to start writing or for stopping the operation during writing.

In this trigger generation circuit, for example, a writing condition is preset by a measurer, and when the input signal waveform matches the condition, the trigger generation circuit detects it and issues a command pulse for starting or stopping writing to the CPU. ing.

FIG. 4 shows an example of this type of trigger generation circuit applied to a recorder, for example.

That is, the recorder main body 30 is provided with a trigger generation circuit 40 as shown by a dotted frame, for example. Here, assuming that a signal of one of a plurality of analog channels to be measured is applied to the analog channel input terminal 31, the input waveform is provided with a sampling circuit via a buffer amplifier 32, for example. The digital-converted waveform data input to the A / D converter 33 is sent to the recording unit 35 via the CPU 34 including a memory,
The waveform is drawn on recording paper or the like.

In this case, the output from the buffer amplifier 32 is, for example, branched so as to be applied to one input end of an analog comparator 41 provided in the trigger generation circuit 40. A voltage from, for example, a reference voltage source 42 is applied to the other input terminal of the comparator 41 to set its threshold level. The branch output from the buffer amplifier 32 is compared with the threshold voltage here, and when it exceeds the threshold voltage, the comparator 41 outputs a step-like signal rising from the L level to the H level, for example. Further, when the branch output exceeds the threshold voltage and drops below the threshold voltage, the comparator 41 outputs a step-like signal that falls from the H level to the L level, for example. These signals are input to the edge detection circuit 43 via, for example, the analog channel contact A of the switch SW, and a pulse-shaped trigger signal corresponding to the rising (or falling) point is formed.

These trigger signals are applied from the edge detection circuit 43 to the CPU 34 of the recorder main body 30. In the CPU 34, the trigger signal formed at the rising (or falling) time of the output of the comparator 41 is regarded as, for example, a write start command signal, and the waveform data to be sent to the recording unit 35 is also written in the memory. .

For the inputs from the logic channels: For convenience of explanation, it is assumed that the number of channels is four, and logic signals from these channels are applied in parallel to the logic channel input terminal 44. in this case,
The switch SW is switched to the logic channel contact L side as shown by a dotted line, for example. On the other hand, each logic signal applied to the terminal 44 is C for waveform recording.
The waveform data that is added to the PU 34 and sampled at a predetermined timing is sent to the recording unit 35.

For the logic signal applied to the input terminal 44, the logic of the required channel bit is inverted by the logic inverting circuit 45, for example. This is so that the trigger signal can be formed with an arbitrary bit pattern. Next, in order to trigger the logic signal of the desired channel at a desired timing, for example, the required channel is selected by the channel bit selection circuit 46 and added to the AND / OR setting circuit 47. This AND / OR setting circuit 47
Is set to either AND or OR according to the input channel signal pattern, and a square wave signal is sent from the output side thereof and added to the edge detection circuit 43. Thereafter, a desired logic signal is written in the memory in the same manner as in the case of the analog channel.

This conventional device has an advantage that the front stage part of the edge detection circuit 43 can be configured by separate circuits for the analog system and the logic system, but on the other hand, this advantage is also a drawback. For example, if the analog input signal contains some noise, so-called chattering occurs at the rising or falling edge of the step signal output from the comparator 41, and the trigger pulse sent from the edge detection circuit 43 becomes unstable. Become. If a hysteresis comparator is used, the influence of noise can be reduced, but it is difficult to make an adjustment to accurately obtain the trigger pulse transmission time point, which is not preferable in any case.

The present invention has been made in view of the above points, and an object thereof is a highly accurate trigger in which an input signal from an analog channel and an input signal from a logic channel can be digitally triggered by the same circuit. It is to realize the generation circuit.

[Structure of the Invention] Referring to FIG. 1 showing an embodiment of the present invention, this trigger generation circuit 1 generates a desired trigger pulse for the number of constituent bits of a digitally converted signal under measurement. The bit number setting number 5 for setting the number of bits required to generate and the bit selection circuit 7 including the gate circuit 6 and the timing condition for trigger generation are set to logical 1, 0.
The reference value setting circuit 8 and the bit selection circuit 7
And a digital comparator 9 for comparing the logical level of each bit of the signal under measurement transmitted from the digital signal with the logical level of each bit of the reference value setting circuit 8, and the desired timing is determined by the comparison output of the magnitude or the coincidence. It has a trigger pulse forming circuit 10 for generating a trigger pulse.

[Operation] The logic level of the lower bit of the digital-converted signal under measurement may be unstable due to, for example, noise. When a desired number of bits excluding the unstable lower bits are set in the bit number setting circuit 5, relatively stable high-order logic information of the signal under measurement is obtained at the output side of the gate circuit 6.

Therefore, in the reference value setting circuit 8, a desired trigger generation condition is given to the bit corresponding to the selected bit of the signal under measurement with a logic 1 or 0, and this and the logical level of each bit of the signal under measurement are digitalized. Comparing with the comparator 9, if the signal under measurement is an analog signal, a magnitude comparison output of the digital conversion data with respect to the trigger condition can be obtained. When the signal under measurement is a logic signal, a comparison output indicating whether the logic level of each bit and the above trigger condition are matched or not is obtained. In the trigger pulse shape circuit 10, a trigger pulse is formed at a desired timing by these comparison outputs.

[Embodiment] Hereinafter, the present invention will be described in detail with reference to an embodiment shown in the accompanying drawings.

In FIG. 1, a recorder main body 30 is a device similar to the conventional recorder main body illustrated in FIG. 4, and the trigger generation circuit 1 according to the present invention combined with the recorder main body 30 has an analog channel input terminal 31. And an analog / logic switching device 4 for selectively switching between an analog input system connecting terminal 2 including an A / D converter 33 for converting its analog input into digital data and a logic input system having a plurality of logic signal input terminals 3. A bit selection circuit 7 including a bit number setting circuit 5 and a gate circuit 6 is provided. For example, a reference value setting circuit 8 and a digital comparator 9 are provided in the subsequent stage of the bit selection circuit 7, and the comparison output of the digital comparator 9 is added to the trigger pulse forming circuit 10. The trigger pulse forming circuit 10 includes, for example, a latch circuit 11 composed of a D-type flip-flop and a flip-flop circuit 1.
2, switch 13, polarity reversing circuit 14, and edge detection circuit 15
The trigger pulse is formed here and is sent to the CPU 34 of the recorder main body 30.

The respective parts will be described below. The input signal from the analog channel is digitally converted by, for example, the 8-bit A / D converter 33 of the recorder main body 30 and applied to the analog / logic switching device 4 via the terminal 2. The analog / logic switch 4 may be an analog switch or a mechanical switch. For example, when "analog measurement" is designated in the function setting device (not shown), the analog switch is switched to the analog side, and the 8-bit waveform data from the A / D converter 33 is , The gate circuit 6 composed of, for example, eight AND elements is applied to one input terminal of each corresponding AND element.

To the other input terminal of each of the AND elements constituting the gate circuit 6, there is connected a bit number setting circuit 5 consisting of an 8-output register constituted by, for example, a D-type flip-flop. Circuit 5 and gate circuit 6
By the bit selection circuit 7 consisting of, the comparison accuracy of the digital comparator 9 provided in the subsequent stage can be determined. For example, when the comparison bit number is designated as 8 by a function setting device (not shown), the CPU 34 gives the bit number setting circuit 5 data such that all eight output bits from the MSB to the LSB become logical ones. As a result, a signal of logic 1 is applied from the bit number setting circuit 5 to each of the other input terminals of the gate circuit 6. Therefore, the 8-bit waveform data applied from the analog / logic switch 4 to the one input terminal of the gate circuit 6 is input to the digital comparator 9 in the same bit pattern as the reference data from the reference value setting circuit 8. Compared to. In this case, the measurer sets a desired reference value in advance in the function setting device (not shown) in decimal, for example. The CPU 34 converts this into an 8-bit binary signal, and supplies it to a reference value setting circuit 8 having 8 outputs, which is constructed in substantially the same manner as the bit number setting circuit 5, for example. As a result, 8-bit reference data for comparison can be obtained. The bit number setting circuit 5 and the reference value setting circuit 8 may be replaced with, for example, manual operation switches that output logic 1 and 0.

In this embodiment, since the conversion bit number of the A / D converter 33 used in the recorder main body 30 is 8, the comparison bit number of the input waveform data and the reference data in the digital comparator 9 is also 8 or less, The highest accuracy is 1/2 ⁸ (0.4%), but it goes without saying that it is not limited to this.

In the above embodiment, if the comparison accuracy happens to be 1%, the number of comparison bits is designated as 7 (accuracy 0.8%) in the function setting device (not shown). The CPU 34 provides the bit number setting circuit 5 with data such that the upper 7 bits are logical 1 and the lower 1 bit is logical 0, that is, the LSB is logical 0, and the reference value setting circuit 8 is logical that the lower 1 bit is logical LSB. 8-bit binary reference data is given so that it becomes zero. As a result, the LSB of the waveform data from the gate circuit 6 and the reference data from the reference value setting circuit 8 input to the digital comparator 9
Are both 0, and data comparison is performed with the upper 7 bits. Therefore, whether the actual data of the lower 1 bit output from the A / D converter 33 is 1 or 0 is a dead zone irrelevant to the comparison result. It can be easily understood that if the number of comparison bits is designated as 6, for example, 2 bits of LSB and bit 1 become a dead zone. Although the digital comparator has higher stability against noise and the like than the analog comparator, it can be further stabilized by utilizing this dead zone. When comparing the waveform data and the reference data with 8 effective bits as described above and providing a dead zone of 1 or 2 bits in addition to the above, the A / D converter 33, the bit number setting circuit 5, the gate The circuit 6, the reference value setting circuit 8 and the like may have a 10-bit configuration, for example.

Here, each part of the trigger pulse forming circuit 10 provided at the subsequent stage of the digital comparator 9 will be described with reference to FIG.

It is assumed that the waveform data applied from the gate circuit 6 to the digital comparator 9 is A, the reference data given from the reference value setting circuit 8 is B, and the lower n bits of this reference data B are set to a dead band with a logic 0. If the data of is expressed in analog form in an easy-to-understand manner, it will be as shown in (a) of the same figure. Here, α represents the n-bit dead band width which is set to the logic 0, and the level obtained by adding the dead band width α to the reference data B is represented by B ′. When the waveform data A exceeds this level B'in FIG. 9A, the X output of the digital comparator 9 becomes as shown in FIG. 9B, and when it falls below the reference data B, its Y output. Is as shown in FIG. Correspondingly, the Q ₁ output and Q ₂ output of the latch circuit 11 are (c) and (c) ′, respectively.
As shown in. Therefore, the flip-flop circuit 12
As shown in (d), the Q output has a waveform that rises at the rising time t ₁ of the output of (c) and falls at the rising time t ₂ of the output of (c) ′.

In this case, assuming that the switch 13 is connected to the analog input side J as shown by the solid line by the analog / logic switching signal from the function setter (not shown), its L output is shown in FIG. As shown in, the waveform has the same shape as that of (d), and is applied to one input terminal of the polarity inverting circuit 14.

At the other input terminal of the polarity inverting circuit 14, for example, a logic 0 or a logic 1 from a function setter (not shown) is also provided.
The rising / falling selection signal of is added. When a signal of logic 0 is added, a signal waveform of the same polarity as the input waveform is output as shown in (f), and a signal of logic 1 is added. Then, a signal waveform with inverted polarity is output as shown in (g). In this case, assuming that the edge detection circuit 15 is adapted to detect the rising edge of the input signal, the signals (f) and (g) are shown in (h) and (h), respectively. Although such a detection output is issued, the detection output of (i) corresponds to the falling time t ₂ when viewed from the original signal of (d) or (e). These detection outputs are used as trigger pulses, for example, in the recorder main body 30.
Is sent to the CPU.

Next, the case of logic input will be described. For example, “logic measurement” is designated in the function setting device (not shown). As a result, the switch of the trigger pulse forming circuit 10
13 is connected to the logic input K side indicated by the dotted line, and the output of the digital comparator 9 is Z output (A = B)
Are used for trigger pulse formation. In this embodiment, 8-channel logic signals can be input, but for the sake of clarity, the case where 4-channel logic signals from channel 1 to channel 4 are input will be described with reference to FIG.

(1) When the trigger condition is the time when the logic levels of the logic patterns of all channels match the comparison reference value (1, 0, 0, 1).

By operating a function setting device (not shown), the CPU
The upper 4 bits of the bit number setting circuit 5 (MS
The output of B, bits 6, 5, and 4) is set to 1, and the output of the lower 4 bits (bit 3, 2, 1, LSB) not used is set to 0.

Similarly, the upper 4 bits of the reference value setting circuit 8 (Q ₇ ,
The outputs of Q ₆ , Q ₅ , and Q ₄ are set to 1 (1, 0, 0,
1) and the lower 4 bits not used (Q ₃ , Q ₂ , Q ₁ ,
Set the output of LSB) to 0.

The logic pattern of each input signal is, for example, as shown in FIG.
If it is as shown in (a), the above
The timing that matches the comparison reference value of (1) is from t ₁ to t ₂ . From the output terminal Z of the digital comparator 9
The match signal as shown in (b) is issued and the latch circuit
11 inputs D ₃ are added. Thereafter, as in the case of the analog channel, the latch output is added from the output end Q ₃ to the input end K of the switch 13 as shown in (c),
The output from the output terminal L is input to the polarity reversing circuit 14. In this case, if the edge detection circuit 15 is, for example, a circuit that detects a rising edge of the input as described above, in order to generate a trigger pulse at time t ₁ that satisfies the above trigger condition, the polarity inversion circuit 14 outputs As shown in (d) above
It is necessary to add a rising signal of the same polarity as (c). Therefore, the rising / falling selection signal of the polarity reversing circuit 14 is set to rising and, for example, "rising" is designated in a function setting device (not shown). This allows
A signal of logic 0 is applied to the other input terminal of the polarity inverting circuit 14, and the output shown in the above (d) is applied to the edge detecting circuit 15. The edge detection circuit 15 detects the rising edge of this input and outputs a trigger pulse at a predetermined time point t ₁ as shown in (e).

(2) From the state where the logic level of the logic pattern of all channels matches the comparison reference value (1, 0, 0, 1), 1
When a trigger is issued when there is a mismatch for more than one channel.

Referring again to FIG. 3A, the time when this condition is satisfied is the falling time t ₂ of the Z output of the comparator 9. Therefore, in this case, the rising / falling selection signal of the polarity reversing circuit 14 is set to the falling signal, and a signal of logic 1 is added to the other input terminal by operating a function setting device (not shown), for example. ) ′, The output polarity of the polarity inverting circuit 14 is inverted. As a result, a desired trigger pulse is issued from the edge detection circuit 15 at time t ₂ as shown in (e) ′.

(3) When the trigger is issued when the logic levels of the logic patterns of all channels are different from the comparison reference value (1, 0, 0, 1) and match one or more channels.

An example of the logic input is shown in (a) of FIG. 3 (B), but at the time when the above trigger condition is satisfied, as shown in (b) of FIG. It is a falling time point t ₃ . Therefore, in this case, for example, the higher 4 bits Q ₇ , Q ₆ , Q ₅ , Q ₄ of the reference value setting circuit 8 have a signal 0, which is obtained by inverting the logic level of the comparison reference values 1, 0, 0, 1
1, 1, 0 are applied, and the rising / falling selection signal of the polarity inverting circuit 14 is a falling signal, that is, a logic 1. As a result, the output polarity of the polarity reversing circuit 14 is inverted as shown in FIG.
At t ₃ , the desired trigger pulse is issued as shown in FIG.

(4) Trigger when all channels become different from the comparison reference value after the logic level of the logic pattern of one or more channels matches the comparison reference value (1, 0, 0, 1). When you issue.

Referring to FIG. 3 (B) above, the time when this trigger condition is satisfied is the time t ₄ when the Z output of the comparator 9 rises.
Is. Therefore, in this case, for the upper 4 bits Q ₇ , Q ₆ , Q ₅ , Q ₄ of the reference value setting circuit 8, for example, logical levels 0, 1, 1, 0 are used as the proportional reference as in the case of the above (3). As a value, the rising / falling selection signal of the polarity inverting circuit 14 is a rising signal, that is, a logic 0. As a result, the output of the polarity inverting circuit 14 has the same logical pattern as the Z output of the comparator 9 as shown in (d) ', and the edge detection circuit 15 outputs the time t ₄ as shown in (e)'. Then, a desired trigger pulse is emitted.

The trigger condition is not limited to the above example, and a desired trigger condition can be arbitrarily set by combining logic patterns.

In the case of an analog channel, the trigger pulse forming circuit 10 in the embodiment of FIG. 1 is a signal indicating that the output of the digital comparator 9 has changed from the state of A> B to the state of A <B, or vice versa. It suffices if a signal indicating a change in direction can be detected, and a signal indicating a state of A = B is ignored. On the contrary, in the case of the logic channel, the signal indicating the state of A = B is detected, and the signals indicating the other states are ignored.
Therefore, another circuit may be used as long as these functions are satisfied.

Further, although an example using an AND element is shown in the gate circuit 6 of the bit selection circuit 7, another gate element may be used. For example, when an OR element is used, the bit number setting circuit 5 sets a logical 0 for a bit to be compared and a logical 1 for a bit that is not compared. Similarly, for the data supplied to the reference value setting circuit 8, the bits not compared are set to logic 1.

[Effects of the Invention] As described in detail above, the trigger generation circuit 1 according to the present invention has the bit selection circuit 7 having the bit number setting circuit 5 and the gate circuit 6, and the digital conversion data of the analog channel signal or A multi-channel logic signal is switched and input to the bit selection circuit 7. In the bit selection circuit 7, the bit number setting circuit 5 specifies the number of bits for trigger condition setting for the digital conversion data of the analog signal, and the number of channels for trigger condition setting for the logic signal. It is specified.

The designated bit signal or the logic signal of each designated channel is applied to one input end of the digital comparator 9 through the gate circuit 6, and the other input end is triggered by the reference value setting circuit 8 as a trigger condition for comparison. The reference data of is given.

The output signal of the digital comparator 9 is input to the trigger pulse forming circuit 10, and the input signal from the analog channel is detected at the time when the level changes with respect to the reference data. The input signal from the logic channel is designed to detect when the level of the reference data matches (or when it does not match), and a trigger pulse is generated by these detection signals and output to the recorder main body 30. It is supposed to do.

Therefore, according to the trigger generating circuit 1, since the trigger condition including the dead zone can be digitally set by the binary signal as necessary, there is almost no interference due to noise or the like,
It is possible to generate a trigger pulse with high precision timing. Also, both analog and logic can be compared, and at that time, it is possible to specify and compare arbitrary bits.
In the case of logic, it can be used regardless of the position of the input channel. Furthermore, the trigger condition can be easily set, and the condition can be arbitrarily selected from a wide variety of applications, so that the application range is wide.

[Brief description of drawings]

1 to 3 relate to an embodiment of a trigger generating circuit according to the present invention, FIG. 1 is a block diagram showing an example of the circuit configuration, FIG. 2 is a timing diagram for explaining an operation for an analog signal, 3 (A) and 3 (B) are timing diagrams for explaining the operation with respect to the logic signal, and FIG. 4 is a block diagram of the conventional device. In the figure, 1 is a trigger generation circuit, 5 is a bit number setting circuit, 6
Is a gate circuit, 8 is a reference value setting circuit, 9 is a digital comparator, and 10 is a trigger pulse forming circuit.

Claims (1)

[Claims] 1. An analog input system including an analog signal input terminal and an A / D converter for converting an analog signal to be measured input from the analog signal into digital data, and a logic input system having a plurality of logic signal input terminals. An analog / logic switch that selects either the A / D output of the analog input section or the logic input section, and the number of bits corresponding to the data output from the analog / logic switch or a bit number less than that. And a bit number setting circuit for setting a desired bit to a predetermined logic level so as to make the desired bit valid, a bit setting signal from the same bit number setting circuit, and data output from the analog logic switching device. And the bit number setting circuit that sends the data specified by the same bit setting signal. A reference value setting circuit having a number of bits corresponding to the set bits and outputting a reference value of a desired trigger condition by the bits, data from the gate circuit and reference value data from the reference value setting circuit In response to the above, the level comparison or coincidence / non-coincidence of the levels is detected, and the digital comparator having three output forms corresponding thereto and the comparison signal from the digital comparator are used to determine the above reference value in the case of an analog input system. And a trigger pulse forming circuit that detects the time when the input level with respect to the data changes and, in the case of a logic input system, detects the time when the logic level matches (or does not match) with the reference value data and sends a trigger pulse. A trigger generation circuit characterized in that.