JPH0636312B2 - Word line floating prevention circuit - Google Patents

Description

The present invention relates to a word line floating prevention circuit, and more particularly to a MO
The present invention relates to a word line floating prevention circuit in a semiconductor memory circuit composed of S-type field effect transistors.

[Prior Art] Dynamic Random
In an access memory (DRAM), address information for identifying any one of a large number of memory cells configured in one chip is activated by a row address activation signal ▲ ▼ and a column address activation signal ▲ ▼. It

Of these, the word line is specified by the selection signal activated by the row address activation signal. In a circuit using one transistor type memory cell, the switching MOS connected to the memory cell is connected to this word line. The gate of the field effect transistor is connected. Then, the switching MOSFET is turned on by raising the level of the selected word line to the level of the power supply voltage side or higher, and the information stored in the memory cell is transmitted to the bit line.

At this time, a non-selected word line is transiently at a floating level and may be charged up due to noise such as crosstalk, so that a prevention circuit is required.

FIG. 2 shows a conventional circuit diagram for preventing the above charge-up.

In FIG. 2, a NOR type address decoder driver circuit 5 (hereinafter referred to as a decoder) decodes address information to specify a word line W, and a word line driving voltage supply circuit (hereinafter referred to as a voltage supply circuit) 6 It is provided as a pair with the decoder 5. Further, the MOSFETs Q ₅ and Q ₆ are word lines W
It is provided for each.

The decoder 5 outputs a high level (power supply voltage side level) when the row address activation signal () is activated and becomes active, and all the outputs of the decoder 5 are reset to a high level during standby.

The output of this decoder 5 is an N-channel MOSFET
MOSFET Q ₆ driving word line 9 via Q ₅
Applied to the gate of. The MOSFET Q ₆ is a source follower N-channel MOS whose drain is connected to the voltage supply circuit 6 and whose gate is MOSFET.
It is connected to the source of Q ₅ .

In the active, the output of the MOSFET Q ₅ selected by the decoder 5, the corresponding MOSFET
The Q ₆ is turned on state, it was turned on MOSFET
Only the word line W connected to the source of Q ₆ goes high and is selected.

At reset, all word lines are MOSF.
Since ET Q ₆ is on, each MOSFE
It is maintained at the ground potential by the voltage supply circuit ₆ through T Q ₆ .

Reference numeral 7 denotes a 1-transistor type memory cell, which is composed of an N-channel type MOSFET Q ₇ and a storage capacitor C ₂ . The counter electrode of the storage capacity C ₂ of each memory cell 7 is
It is connected to the output node of the low voltage supply circuit 9 and kept at a low potential.

N-channel type MOSFET Q ₈ is provided between the word line W and the ground, it is intended to prevent the charge-up caused by noise such as crosstalk of the word lines W in a floating state.

One MOSFET Q ₈ is attached to every word line W, and a low voltage equal to or higher than the threshold voltage formed by the low voltage supply circuit 8 is applied to its gate. Accordingly, since the MOSFET Q ₈ is always ON state, that the non-selected word line becomes a floating completely prevented.

However, since the same applies to the selected word line, MO
SFET Q ₆ and Q ₈ are both in the ON state and the voltage supply circuit 6
Since the word line W is supplied with the power supply voltage by, the so-called ON-ON current flows during the active period, which may cause the potential drop of the word line W. Therefore, the size of the MOSFET Q ₈ is changed to the MOSFET Q ₆
By applying an intermediate voltage between the power supply and the ground line to the gate by the low voltage supply circuit 8, the capacity of the MOSFET Q ₈ is greatly reduced and the voltage drop of the word line W is suppressed. There is.

As explained above, between the word line W and the ground line,
By being configured the discharge path provided MOSFET Q ₈ of the always-on state, the charge-up of the non-selected word line can reliably prevent possible malfunction to be prevented completely.

[Problems to be solved by the invention]

In the above-described conventional configuration, a low voltage supply circuit for fixing the counter electrode of the storage capacitor of the memory cell to a low potential and a low voltage supply circuit for applying to the gate of the transistor attached to prevent word line floating And 2
Two low voltage supply circuits were needed. Therefore, the number of elements increases and two separate sharp wires are required,
There is a drawback in that it is inconvenient for creating a mask layout.

If the former low-voltage supply circuit is made to be an earth line, the above-mentioned drawbacks will be solved, but the number of elements will increase as the memory capacity increases,
Therefore, as the miniaturization of each element has progressed, the withstand voltage limit of each element is decreasing, so the potential change of the storage capacity can be changed by setting the counter electrode of the storage capacity of the memory cell to the intermediate potential between the power supply and ground. It is necessary to make it small, and therefore, a low voltage supply circuit for setting the counter electrode of the storage capacitor of the memory cell to an intermediate potential between the power supply and the ground is necessary.

In contrast to the conventional word line floating prevention circuit described above, the present invention connects the counter electrode of the storage capacity of the memory cell and the gate of the MOSFET provided between the word line and the ground, and uses the node as a power source. It has the original content of connecting to the output contact of an intermediate voltage supply circuit that maintains an intermediate potential with respect to the ground potential.

[Means for solving problems]

The circuit of the present invention includes a field effect transistor for each word line, the drain of which is connected to the word line, the source of which is connected to the ground, the gate of which is held at an intermediate potential between the power supply and the ground and which has a lower capability than the word line driving transistor. And a counter electrode on the non-driving side of the storage capacitor of the memory cell is connected to the intermediate potential.

〔Example〕

 The present invention will now be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

3 is a one-transistor type memory cell, and Q ₃ is N
The channel type MOSFET C ₁ represents a storage capacitor. The MOSFET Q _{3 has} a gate connected to the word line W, a source connected to the digit line B, and a drain connected to the storage capacitor C ₁ .

The counter electrode of the storage capacitor C ₁ is connected to the counter electrodes of the storage capacitors of all the remaining memory cells, and this contact has an N channel whose source is connected to the word line W and whose drain is grounded. Type MOSFET Q ₄ and is connected to the output contact of an intermediate voltage supply circuit 4 which supplies an intermediate potential between the power supply and ground.

The MOSFET Q ₄ is provided in each word line. That is, the counter electrode of the storage capacitor C ₁ of each memory cell 3 and the gate of the MOSFET Q ₄ provided between each word line, ground line, and ground are all connected, and the contact point is the output of the intermediate voltage supply circuit 4. By connecting to the node, it is kept at the intermediate potential between the power supply and ground.

Next, the decoder 1, the voltage supply circuit 2, and the gate are provided with MO.
SFET Q ₁ is applied the output voltage of the decoder 1 via the addition, the source is connected to the output node of the voltage supply circuit 2, the drain of the source follower N-channel type the word line W is connected to MOSFET Q ₂ Mix
The operation of this embodiment will be described below.

When the memory chips are in the standby mode, all the decoders 1 apply the high level to the gates of the respective MOSFETs Q ₂ , but when the active period starts, only the selected decoder maintains the high level, and the other The output of the selected decoder changes from high level to low level (ground voltage side level). That is, the selected MOSFET Q ₂
Remains on and unselected MOSFET Q ₂
Is turned off.

After that, when the output of the voltage supply circuit 2 changes from the low level to the high level, the selected word line W is raised from the low level to the high level because the selected MOSFET Q ₂ is in the ON state. because MOSFET Q ₄ which is provided between the ground even in the on state, these two MOSFET so-called on - kept on, so that the lifting selected word line W to the high level.

However, the size of MOSFET Q ₄ is
Since the intermediate potential between the power supply and the ground is applied to the gate by the intermediate voltage supply circuit 4 which is significantly smaller than that of ET Q ₂ , the selected word line W is set to the high level because its ability is greatly suppressed. Can be maintained.

At this time, the MOSFET Q _{2 of} the non-selected word line W is off, but the MOSFET Q ₄ is on, so that the word line W does not float and is kept at the ground level. The charge-up is completely prevented, and malfunctions can be reliably prevented. Further, since the counter electrode of the storage capacitor C ₁ of the memory cell 3 is also connected to the same intermediate voltage supply circuit 4, there is little potential fluctuation between the two electrodes of the storage capacitor C ₁ , and the breakdown voltage is deteriorated due to the miniaturization of the element. It is possible to prevent the destruction of the element due to.

〔The invention's effect〕

The present invention takes the fact that the difference between the two conventional low voltages is narrowing with the progress of miniaturization of the element, and adopts the configuration as described above, so that two are conventionally required. Instead of the low voltage generation circuit, the intermediate voltage generation circuit that generates the intermediate potential between the power supply and the ground is sufficient. Therefore, the number of elements is reduced and therefore the wiring is reduced. It became convenient.

[Brief description of drawings]

FIG. 1 shows an embodiment of the present invention, and FIG. 2 shows a conventional example. Q _{1 to} Q ₈ N-channel type transistor (MOSF
ET), C ₁ , C ₂ ... storage capacity, N ₁ , N ₁ ... nodes, 1, 5 ... NOR type address decoder driver circuit (decoder), 2, 6 ... word line driving voltage supply circuit (Voltage supply circuit), 3, 7 ... memory cell, 4 ... intermediate voltage supply circuit, 8, 9 ... low voltage supply circuit.

Claims (1)

[Claims] 1. A field effect transistor having a drain connected to a word line, a source connected to a ground, a gate held at an intermediate potential between a power source and a ground, and having a capability lower than that of a word line driving transistor, for each word line. And a counter electrode on the non-driving side of the memory cell storage capacitor connected to the intermediate potential.