JPH0636518B2 - Reception control circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reception control circuit in a communication control device that controls data communication of a computer or a terminal device, and more particularly to control of a reception operation of start / stop synchronization / character synchronization method. Is.

(Prior Art) FIG. 5 is an example of a relatively large-scale system to which this type of reception control circuit is applied, and FIG. 6 is an example of a relatively small-scale device.

In the system shown in FIG. 5, a central processing unit (hereinafter referred to as CPU) 10 for controlling the entire system, a memory 11 and various input / output control devices are connected via a bus 12. Here, the input / output control device is the file control device 13 connected to the illustrated file unit 14, the FDD control device 15 connected to the FDD unit 16, and the communication control device connected to the line 18.
Although it refers to a large number of devices such as 17, it is not directly related to the present invention, and a detailed description thereof will be omitted. The present invention is concerned with the communication control device 17 for performing communication in the input / output control device. The communication control device 17 is, for example, as shown in FIG.
1, memory 22, communication control LSI 23, driver / receiver 24
Composed of. The microprocessor 20 is composed of a vertical microprocessor (for example, a 16-bit 1-chip microprocessor i8086 manufactured by Intel), a horizontal microprocessor (for example, a 4-bit slice microprocessor Am2901 manufactured by AMD), and the like. Communication control LSI 23 is a line
It is a circuit that converts serial data received from 18 into parallel data or vice versa, and the details thereof will be described later. In this specification, this circuit is called a communication control LSI for the sake of explanation in the form of actual hardware, but it is not necessarily an LSI and can naturally be realized by a circuit having an equivalent function. is there.

Fig. 6 shows an example of a small-scale device.
The memory 31 and the various input / output circuits are connected via the bus 32, and the CPU 30 directly controls the various input / output circuits. Here, the various input / output circuits are the DISK control LSI 33 connected to the illustrated file unit 35 via the driver / receiver 34, the FDD control LSI 36 connected to the FDD unit 38 via the driver / receiver 37, and the line.
Communication control connected to 41 via driver / receiver 40
Although many circuits including the LSI 39 are shown, the description of the parts not directly related to the present invention will be omitted as in the above. The present invention is concerned with the receiving circuit between the CPU 30 and the communication control LSI 39.

FIG. 7 is a block diagram showing an example of the configuration of a receiving unit of a conventional communication control device for start / stop synchronization / character synchronization. This receiving unit is a communication control device in the large-scale system illustrated in FIG.
It corresponds to a portion including a microprocessor 20, a memory 22, a communication control LSI 23, and a driver / receiver 24 inside 17 and, in the example of the small-scale device illustrated in FIG.
It corresponds to a portion including a CPU 30, a memory 31, a communication control LSI 39, and a driver / receiver 40. This reception control circuit is a microprocessor circuit 300, memory 301, communication control
It consists of an LSI 302 and a receiver 303 connected to the line 304.

Serial data received on line 304 is receiver 303
Is electrically level-converted (for example, an electric signal of ± 10 V is converted to a TTL signal) and input to the communication control LSI 302. Communication control LSI 302 is, for example, Intel i8251
This is a circuit realized by dividing serial data into appropriate units to create parallel data (hereinafter, this separated parallel data is called a character) and RX R
By turning on the DY signal 307, the completion of character reception is notified to the microprocessor circuit 300. The microprocessor circuit 300 reads the received character through the data bus 306 by turning on the I / O RD signal 308,
Stored in memory 301 after receiving processing. In this receiving process, it is judged whether the received message is the message addressed to the own station. It is judged whether the received message matches the protocol (communication procedure). It is judged whether the received character is the end of the message. Judgment as to whether it composes a message addressed to the partner station by the partner station or shows the response of the message sent from the partner station to the partner station Comprised of CRC calculation and error control such as comparison of calculation results.

Here, the operation of the communication control LSI 302 will be described in detail with reference to FIG. The communication control LSI 302 has a shift register 312 and a data register 313. The serial reception data 310 is input to the serial-in-parallel-out shift register 312 in synchronization with the reception clock 311. When a specified number of bits of data are input, the output of shift register 312 is written to data register 313, and at the same time RX RDY
Signal 315 turns on. Microprocessor circuit (8th
(Not shown in the figure) reads the contents of the data register 313 via the data bus 314 to turn off the RX RDY signal 315, but if the shift register 312 receives the next character before performing the read operation. , The data register 313 is overwritten with the new character and the old character disappears.

(Problems to be Solved by the Invention) However, the above-mentioned conventional technique has the following two problems.

It is necessary to interrupt the microprocessor circuit 300 once for each character.
00 has a heavy load.

The microprocessor circuit 300 has to read the received character within the time from the generation of the interrupt (RX RDY signal 307) by the communication control LSI 302 until the reception of the next character. Otherwise, the received character will be overwritten with the new character and the old character will disappear.

Due to these problems, in the communication control device 17 illustrated in FIG. 5, it is necessary to make the microprocessor 20 a dedicated and high-speed one, which makes it expensive, and a plurality of microprocessors under one microprocessor 20 are required. When attempting to perform multi-line control by accommodating the communication control LSI 23, there were drawbacks such as the number of lines being limited. Further, in the device illustrated in FIG. 6, it is impossible to control other input / output devices such as files when the communication operation starts, and there is a drawback that the specifications of the device are greatly restricted.

The present invention solves the above-mentioned problems of the load of the number of interruptions to the microprocessor circuit and the time constraint for its processing, and the price defect and the constraint of the number of lines and the device which have been conventionally caused by the problem. An object of the present invention is to provide a reception control circuit which removes the constraint imposed on the whole and which does not impose a constraint on the microprocessor circuit at a low cost.

(Means for Solving Problems) The present invention relates to a communication circuit for generating a character from received serial data, a memory for storing a character from the communication circuit, a communication circuit and a memory for accessing various controls. The present invention relates to a start-stop synchronization / character-synchronization type reception control circuit including a microprocessor. The gist of the present invention is that a direct memory access controller that directly stores a character in the above-mentioned memory each time a character is generated by a communication circuit, and interrupt control information and latch control information according to the content of the character are stored. The interrupt control information is output to the microprocessor by accessing the value corresponding to each character stored in the memory as an address, and the latch control information is output when the specific character necessary for the processing of the microprocessor is received. A character determination memory for outputting to the address latch, and a storage address of the memory for the above-mentioned specific character are stored in response to the latch control information from the character determination memory, and the stored storage address can be read from the microprocessor. Address configured to In that a pitch.

(Operation) When the communication circuit receives serial data via the line, it divides it into appropriate units and generates a character that is parallel data. When a character is generated in the communication circuit, the direct memory access controller transfers the character to the memory for writing without the trouble of the microprocessor. The character determination memory stores interrupt control information and latch control information according to the content of the character, and each character code stored in the memory or a value corresponding to this code is used as an address to access the character. The interrupt control information according to the contents of is output to generate an interrupt to the microprocessor,
Also, when a specific character required for the processing of the microprocessor is received, latch control information is output to control the latch operation of the address latch. The address latch responds to the latch control information from the character determination memory,
The memory address of a specific character necessary for the processing of the microprocessor, such as a character indicating the end of the message or a character indicating the start of the beginning of the text in the message, is stored. Moreover, the stored address can be read from the microprocessor.

In this way, in the reception control circuit of the start-stop synchronization / character synchronization method, a specific character such as a character indicating the end of a message or a character indicating the start of the beginning of text in a message is automatically determined and stored. The address on the memory being stored is stored in the address latch. Therefore, the microprocessor does not need to be involved each time in order to discriminate such a specific character, and its contents can be easily known only by accessing this address latch, and the load on the microprocessor is greatly increased. Is reduced to.

Of course, characters other than a specific character are automatically stored in the memory without involvement of the microprocessor, and in that sense, the load on the microprocessor is significantly reduced. Moreover, there is no inconvenience that the received data disappears even if the response time to the interruption of the microprocessor becomes long.

(Example) Hereinafter, the Example of this invention is described in detail.

FIG. 1 is a block diagram showing the configuration of the present embodiment, and the main components are a microprocessor circuit 100 and a memory 1
01, communication control LSI 102, receiver 103, direct memory access controller (hereinafter referred to as DMAC) 112, character latch 115, character determination memory 116, and address latch 121. In the figure, 123 to 125 are gates. The microprocessor circuit 100 includes a memory 101 and a communication control LSI 10 via an address bus 105 and a data bus 106.
2 and are connected to memory read signal 110, memory write signal 111, I / O read signal 108, I / O write signal
The memory 101 and the communication control LSI 102 are accessed by 109. The memory 101 stores the received character under the control of the DMAC 112. The communication control LSI 102 generates a character from the serial data received from the line 104 via the receiver 103. DMAC 112 is a communication control LSI that is an I / O device
A character latch 115, which controls data transfer between the memory 102 and the memory 101, latches the received character on the data bus 106, and uses the output as the address of the character determination memory 116. The character judgment memory 116 is a ROM in this example.
Comprised of, the interrupt control payment and address latch control information is stored in advance, and the microprocessor circuit 1
Controls interrupt to 00 and address storage to address latch 121. The address latch 121 is configured to store the address of the character stored in the memory 101 and read the stored content from the microprocessor circuit 100.

Next, the operation of this embodiment will be described with reference to the operation time chart of FIG.

First, the serial data from the line 104 is level-converted by the receiver 103 and input to the communication control LSI 102 (FIG. 2). In the communication control LSI 102, a character is assembled from serial data, and RX R
The DY signal 119 turns on (Fig. 2). RX RDY signal 119
Is input as the DMA RQ signal of the DMAC 112, and the DMA operation is started by this signal (Fig. 2). DMAC 112
Turns on the HOLD RQ signal 113 and sends the bus (address bus 105, data bus 1
06 and other control signals) are required to be released. In response to this, the microprocessor circuit 100 responds by the HOLD ACK signal 114 (notification of bus release) (FIG. 2). HO
The DMAC 112 that received the LD ACK signal 114 receives the I / O read signal 118.
By turning on, the communication control LSI 102 is requested to send the received character to the data bus 106 (FIG. 2). At this time, when there are a plurality of registers in the communication control LSI 102 and it is necessary to select them by an address, an appropriate value is given to the communication control LSI 102 by the address switching gate 120. When the received character is sent out on the data bus 106, the DMAC 112 gives the memory 101 an address to store the character via the address bus 105 and a memory write signal.
117 is sent to write to the memory 101 (Fig. 2). At the same time as the operation of FIG. 2, the received character on the data bus 106 is latched in the character latch 115 (FIG. 2). The output of the character latch 115 is the address of the character determination memory 116 (FIG. 2).

The output of the character determination memory 116 is the interrupt signal 107 of the microprocessor circuit 100 and the latch control signal 122 of the address latch 121. When the latch control signal 122 turns on, the gate 123 ANDs the timing signal and the address output of the DMAC 112 is transferred to the address latch 121.
Memorized in.

As shown in FIG. 3, the character determination memory 116 is composed of two bits, that is, an interrupt control bit and an address latch control bit, and a 2-bit value is written in advance in a portion corresponding to a required character. There is. In the example of FIG. 3, “11” (interrupt instruction = on, address latch instruction = on) is written in the address (address 17) corresponding to the “ETB” character that is the character indicating the end of the electronic message ( (Fig. 3). Therefore, the character judgment memory
When the 116 receives the "ETB" character, it generates an interrupt to the microprocessor circuit 100, notifies the microprocessor circuit 100 of the completion of the reception of the message, and sends "ETB".
The address of the memory 101 storing the character is stored in the address latch 121. This stored address can be read from the microprocessor circuit 100 via the data bus 106.

Interrupt instruction to the microprocessor circuit 100 written in the character judgment memory 116 and address latch 1
The number of "1" s instructing the address storage in 21 is arbitrary, and the combination of the interrupt instruction and the storage instruction is also free. For example, when the "ETX" character indicating the end of the message is received as in the case of the "ETB" character described above, an interrupt is generated (Fig. 3), and the termination of the message is terminated by the microprocessor circuit 1
You can notify 00. When the "STX" character indicating the start of the beginning of the text in the message is received, the storage address of the memory 101 storing the "STX" character is stored in the address latch 121 although no interrupt occurs (Fig. 3). Then, the microprocessor circuit 100 can read the value of the latch 121 later to easily know the address where STX is stored, that is, the text start address in the message.

Further, since characters other than the predetermined character are automatically stored in the memory 101 in order, the microprocessor circuit 100 does not need to take any part in the receiving operation during that time. That is, the number of interruptions to the microprocessor circuit 100 is greatly reduced, and the load is very light. Further, when a specific character is received and an interrupt occurs, the microprocessor circuit 100 performs the above-described receiving operation (operations (1) to (2) in FIG. 2), but the specific character necessary for processing (for example, text in a message) Since the storage position of "STX" character indicating the start of the) is stored in the address latch 121, the DMA transfer from the communication control LSI 102 to the memory 101 can be continued after the interrupt occurs. Therefore, even if the response time of the microprocessor circuit 100 to the interrupt is long, the received data is not lost, and the restriction on the response time of the microprocessor circuit 100 is relaxed. Also, since the address of the memory where the special character required for processing is stored can be known from the address latch 121, for example, the storage position of the station address (SA) in the received message or the character that needs to be calculated by CRC. It becomes possible to easily know the storage position and so on, and the receiving operation can be performed efficiently.

In the above embodiment, the character determination memory 216 is
Although the case where it is configured by a ROM is illustrated, according to the present invention, a RAM can be used as the memory for character determination 216 and a structure that can be freely rewritten from the microprocessor circuit 100 is also possible. The use of this RAM has the following advantages.

It is possible to dynamically change the type of characters that generate interrupts and storage addresses, and generate only the minimum necessary interrupts at each communication step, or know the storage address of the most necessary character. As a result, the processing efficiency of the microprocessor circuit can be further improved.

Maintenance is easy because there is no need to prepare a ROM for each procedure.

Further, in the above embodiment, the circuit having only one address latch 121 is illustrated, but this portion is constituted by a plurality of latches 121a, 121b, 121c as shown as a modified example of FIG. It is also possible to select the latch to be stored by the output of the memory 116. Furthermore, it is also possible to configure a plurality of latches with a FIFO (first in first out) memory and store the storage positions of a plurality of characters. By having a plurality of latches in this way, it becomes possible to store all the information necessary for the processing of the microprocessor circuit 100, and to further improve the efficiency of the processing of the microprocessor circuit 100.

(Effects of the Invention) As described in detail above, in the present invention, the operation of character determination and storage in the memory, which has conventionally been performed by the microprocessor within a certain time, is performed without depending on the microprocessor. Be seen. Then, only when the content of the character requires the microprocessor circuit to start a new operation, an interrupt is generated to the microprocessor circuit, and the start of a new operation is prompted.
Further, in the present invention, the address of the memory in which a specific character is stored is stored as the information necessary for the operation. Therefore, according to the present invention, the load on the microprocessor can be significantly reduced.

Further, according to the present invention, even if the response time to the interruption of the microprocessor is long, the received data is not lost, so that the software on the microprocessor can be made much more freely.

These eliminate the need to specialize the microprocessor, enable the use of low-priced general-purpose microprocessors, increase the number of lines that can be accommodated when accommodating multiple lines, and peripheral devices other than communications. There is an advantage such as removing the restriction on the control of.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG.
FIG. 4 is a time chart of the circuit of FIG. 1, FIG. 3 is a block diagram of a character judging memory, FIG. 4 is a diagram showing a modification of the present invention, and FIG. 5 is a comparatively large size to which a reception control circuit is applied. FIG. 6 is a block diagram of a large-scale system example, FIG. 6 is a diagram showing a comparative small-scale device example to which a reception control circuit is applied, FIG. 7 is a block diagram of a receiver of a conventional communication control circuit, and FIG. Is communication control
It is an operation | movement explanatory drawing of LSI. 100 ... Microprocessor circuit, 101 ... Memory, 102 ... Communication control LSI, 103 ... Receiver, 112 ... Direct memory access controller (DMA
C), 115 ... Character latch, 116 ... Character judgment memory, 121 ... Address latch.

Claims (1)

[Claims] 1. A communication circuit for generating a character from received serial data, a memory for storing a character from the communication circuit, and a microprocessor for accessing the communication circuit and the memory to perform various controls. In a start / stop synchronization / character synchronization type reception control circuit, a direct memory access controller for directly storing the character in the memory every time the character is generated by the communication circuit, and interrupt control information and latch control according to the content of the character Information is stored, the interrupt control information is output to the microprocessor by accessing a value corresponding to each character stored in the memory as an address, and a specific character required for the processing of the microprocessor is displayed. Outputs latch control information to address latch when received And character determination memory, in response to the latch control information from said character judgment memory,
A reception control circuit, comprising: a storage address of the memory for the specific character; and the address latch configured so that the stored storage address can be read by a microprocessor.