JPH0638092B2 - Capacitor disconnection short circuit detector - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for detecting a short circuit in a capacitor, and more particularly, to a capacitor in a shock test and a vibration test of a capacitor among the test items specified in MIL standard and JIS standard. The present invention relates to a device for conducting a large amount and a high accuracy of the quality judgment test of disconnection and short circuit.

2. Description of the Related Art Conventionally, when inspecting a capacitor for a momentary disconnection or short circuit in a shock test or vibration test, the impedance value is used to balance the capacitance value and loss angle of the measured capacitor. Anyway,
Rectify the AC balanced voltage output of the impedance bridge,
After converting to DC voltage, visually observe if momentary disconnection or short circuit occurs during the test when shock or vibration is applied to the capacitor to be measured using an oscilloscope, pulse detector, etc. Alternatively, the phenomenon is observed using a memory circuit.

At that time, it is difficult to judge the occurrence time of the momentary disconnection or short-circuit condition with the judgment time stipulated in MIL standard and JIS standard. It is necessary to prepare impedance bridges, oscilloscopes, pulse detectors, etc., in an amount corresponding to the test quantity of the capacitor to be measured, and accordingly, a lot of man-hours and a lot of cost are required.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention Accordingly, in the above-mentioned conventional capacitor disconnection short-circuit detection device, (1), in order to perform a test, an impedance bridge,
Special equipment such as an oscilloscope, pulse detector, etc. must be prepared, (2), detection accuracy is poor for making judgments based on the absolute values specified by the MIL standard and JIS standard, (3), a large amount of Testing a capacitor to be measured requires a great deal of cost and a great number of man-hours.

There were drawbacks such as.

The present invention has been made in view of the above-mentioned conventional circumstances,
Therefore, it is an object of the present invention to provide a novel open-circuit short-circuit detection system for a capacitor, which makes it possible to eliminate the above-mentioned drawbacks inherent in the prior art.

Means for Solving the Problems In order to achieve the above object, in the capacitor disconnection short-circuit detection device according to the present invention, an oscillator that emits an AC signal is connected to the primary side winding terminal, and the secondary side winding terminal is connected to the DC side. It is equipped with a superposition transformer in which one end of the test power source and the capacitor to be measured is connected, and the other end of the capacitor to be measured is connected to the integral type current-voltage conversion amplifier via the protection resistor and the primary winding of the detection transformer. A secondary comparison winding terminal of the detection transformer is provided with a first comparison amplifier having a first threshold value setting unit via an AC amplifier and an AC-DC conversion amplifier, and the output of the first comparison amplifier. Is provided with a first 3-input AND gate serving as a signal suppression gate, and a clock signal generator is also connected to the first 3-input AND gate. The clock signal is sent out only when the wire is disconnected. The disconnection circuit counts the disconnection time, the disconnection time and the disconnection determination time set value are compared by the first digital comparator unit, and the comparison result is output. Only when the disconnection failure is determined for the first time, the first counter circuit is provided. Data is displayed on the disconnection time display section, data is displayed as disconnection failure on the disconnection failure display section, and the output of the integrating type current-voltage converter is the second
A second 3-input AND gate, which is connected to a second comparator having a threshold value of, and serves as a signal suppression gate from the output of the second comparator,
The clock signal generator is connected to the 3-input AND gate of, and the clock signal is sent out only during the short circuit time, and the second counter circuit counts the short circuit time, and this short circuit time is set as the short circuit judgment time set value. The second digital comparator section compares and outputs the comparison result, and holds the data of the second counter circuit and displays the data on the short-circuit time display section only when the first short-circuit failure determination is made, and the short-circuit failure display section displays the data. Is configured to indicate a short circuit failure.

Originality of the Invention In the above-described conventional capacitor disconnection and short-circuit detection device, performing a large amount of detection at one time is very expensive, the detection device becomes large in size, and the workability is significantly deteriorated. On the other hand, according to the present invention, the circuit can be easily modularized, the size can be reduced, and the detected disconnection time and short circuit time can be digitally displayed and stored. It will be possible. Further, it has an original content that it is possible to detect disconnection and short circuit of a large number of capacitors accurately and easily at a low cost.

EXAMPLES Hereinafter, the present invention will be specifically described with reference to the drawings with respect to a preferred example thereof.

FIG. 1 is a block diagram showing an embodiment of a capacitor disconnection and short circuit detection device according to the present invention.

In FIG. 1, the output terminal on the high impedance side of the oscillator 1 is connected to one input terminal of the buffer amplifier 2, and the other input terminal of the buffer amplifier 2 is grounded and the oscillator 1
Connected to the ground terminal side of.

Next, the output terminal of the buffer amplifier 2 is connected to one terminal of the primary side of the superposition transformer 3, and the other terminal of the primary side of the superposition transformer 3 is grounded. One terminal on the secondary side of the superposition transformer 3 is connected to one terminal side of the measured capacitor 5 (when the measured capacitor 5 has polarity, it is connected to the + side terminal of the measured capacitor 5). ). The other terminal of the secondary side terminal of the superposition transformer 3 is connected to the + side output terminal of the DC test power supply 4, and the − side output terminal of the DC test power supply 4 is grounded.

The other terminal side of the measured capacitor 5 (one side terminal of the measured capacitor 5 when the measured capacitor 5 has polarity)
Is connected to one terminal of the protection resistor 6, the other terminal of the protection resistor 6 is connected to one terminal of the primary side of the detection transformer 7, and the other terminal of the primary side of the detection transformer 7 is an integral type. It is connected to one input terminal of the current-voltage conversion amplifier 26, and the other input terminal of the integration type current-voltage conversion amplifier 26 is grounded. One terminal on the secondary side of the detection transformer 7 is connected to one input terminal of the AC voltage amplifier 8, and the other terminal on the secondary side of the detection transformer 7 is connected to the other input terminal of the AC voltage amplifier 8. Connected and grounded.

Next, the output terminal of the AC voltage amplifier 8 is connected to one input terminal of the AC-DC conversion amplifier 9, and the other input terminal of the AC-DC conversion amplifier 9 is grounded. The output terminal of the AC-DC conversion amplifier 9 is connected to one input terminal of the comparison amplifier A11, and the other input terminal of the comparison amplifier A11 is connected to the threshold value setting unit A10. Comparative amplifier A11
Is connected to the input terminal of the monostable multivibrator A17, and is also connected to the second input terminal of an AND gate-A (hereinafter abbreviated as AND-A) 13. AND-
The first input terminal of A13 is connected to the output terminal of flip-flop-B (hereinafter abbreviated as FF-B) 22 and AND
The third input terminal of -A13 is connected to the third input terminal of AND-E29 which will be described later, and the clock signal generating circuit 12
Connected to.

The input terminal C of the counter circuit A14 is connected to the output terminal of the AND-A13, and the input terminal R of the counter circuit A14 is connected to the output terminal of an OR gate-A (hereinafter abbreviated as OR-A) 18. The output terminal of the counter circuit A14 is the disconnection time display unit 24
In addition, it is connected to the input terminal A of the digital comparator section A15.

Next, the input terminal B of the digital comparator section A15 is connected to the disconnection determination time setting section 16, and the output terminal of the digital comparator section A15 has a flip-flop-A (abbreviation FF-).
A) Connected to the input terminal CK of 20. The input terminal R of the FF-A20 is connected to the reset signal 42, and the output terminal Q of the FF-A20.
Is an upper AND gate-C (abbreviation AND-C) 21 connected to one input terminal of an AND gate-D (abbreviation AND-D) 23.
Connected to one of the input terminals. The output terminal of the FF-A 20 is connected to one input terminal of an AND gate-H (abbreviation AND-H) 39 described later and the AND gate-B (abbreviation AND-H).
B) Connected to one input terminal of 19. The other input terminal of AND-B19 is connected to the output terminal of monostable multivibrator A17, the output terminal of AND-B19 is connected to the other input terminal of AND-C21, and one input terminal of OR-A18 Connected with. The other terminal of OR-A18 is reset signal 42
Connected to. The input terminal R of the monostable multivibrator A17 is connected to the reset signal 42.

The input terminal CK of FF-B22 is connected to the output terminal of AND-C21, and the input terminal R of FF-B22 is connected to the reset signal 42.

Next, the other input terminal of the AND-D23 is connected to one input terminal of an AND gate-F (abbreviated as AND-F) 35 which will be described later, and the output terminal of the AND-D23 is connected to the disconnection defect display portion 25.

On the other hand, one input terminal of the comparison amplifier B27 has an integrated current −
Connected to the output terminal of the voltage conversion amplifier 26, the comparison amplifier B
The other input terminal of 27 is the threshold value setting section B28.
Connected with. The output terminal of the comparison amplifier B27 is connected to the input terminal of the monostable multivibrator B33, and is also connected to the second input terminal of an AND gate-E (abbreviation AND-E) 29. The first input terminal of AND-E29 is connected to the output terminal of flip-flop-D (abbreviation FF-D) 38, and the third input terminal of AND-E29 is AND-A13 described above.
Is connected to the clock signal generating circuit 12 as well as being connected to the third input terminal.

Next, the input terminal C of the counter circuit B30 is connected to the output terminal of the AND-E29, and the input terminal R of the counter circuit B30 is connected to the output terminal of the OR gate-B (abbreviation OR-B) 34. The output terminal of the counter circuit B30 is connected to the short-circuit time display section 40, and is also connected to the input terminal A of the digital comparator section B31. The input terminal B of the digital comparator section B31 is connected to the short-circuit determination time setting section 32, and the output terminal of the digital comparator section B31 is flip-flop.
It is connected to the input terminal CK of C (abbreviation FF-C) 36.

The input terminal R of the FF-C36 is connected to the reset signal 42,
The output terminal Q of -C36 is connected to one input terminal of AND-H39 and is also connected to one input terminal of AND gate-G (abbreviated as AND-G) 37. The output terminal of FF-C36 is connected to the other input terminal of AND-D23 described above, and AND
-Connected to one input terminal of F35.

The other input terminal of AND-F35 is connected to the output terminal of monostable multivibrator B33, and the output terminal of AND-F35 is A
In addition to being connected to the other input terminal of ND-G37, it is also connected to one input terminal of OR-B34. The other input terminal of the OR-B 34 is connected to the reset signal 42. The input terminal R of the monostable multivibrator B33 is connected to the reset signal 42.

Next, the operation of the capacitor disconnection short-circuit detecting device configured as described above will be described with reference to FIGS. 2, 3, 4, and 5.
This will be described with reference to FIGS. 6, 6 and 7.

FIG. 2 is a timing chart showing the reset signal 42 for operating the circuit of FIG. 1 of the present invention and the measurement and stop states on the time axis.

Referring to FIG. 1 and FIG. 2, first, the counter circuit A14, the counter circuits B30, FF-A20, FF-C36, and the counter circuit B30 are set in accordance with the rising timing of the reset signal 42 from "0" to "1".
Each of the monostable multivibrator A17, the monostable multivibrator B33, FF-B22, and FF-D38 is reset to the initial state.

“Stop” in the measurement / stop state means that all the operations of the circuit in FIG. 1 are in an invalid state, and “measurement” means that the operation is valid. Therefore, the operation of applying the DC applied voltage E by the DC test voltage 4 to the capacitor to be measured 5 is executed at the time of "stop" before the "measurement", and the operation of discharging the charge charged in the capacitor to be measured 5 is "measurement". It shall be executed at the time of "Stop" later.

Next, the case where the measured capacitor 5 is normal will be described with reference to FIG.

First, when an AC voltage is supplied from the oscillator 1 to the primary side of the superimposition transformer 3 via the buffer amplifier 2, an AC voltage corresponding to the primary and secondary turns ratio of the superimposition transformer 3 is supplied to the secondary side of the superimposition transformer 3. An applied voltage e is generated (Fig. 3 (a)). Furthermore, in order to apply a DC voltage to the measured capacitor 5, the superposition transformer 3
DC applied voltage E (Fig. 3 (b)) is supplied from the DC test power supply 4 connected in series to the secondary side of the capacitor, and the AC applied voltage e is superimposed on the DC applied voltage E on the measured capacitor 5. The generated signal is applied via the protection resistor 6.

Here, since the measured capacitor 5 is normal, the impedance of the measured capacitor 5 is:
It is expressed by the following equation (1).

However, Zc: impedance of measured capacitor 5 (Ω) f: frequency of AC applied voltage (Hz) c: capacitance value of measured capacitor 5 (F) Here, in the present invention, frequency f of AC applied voltage ( Hz) to 20 (K
Hz), and the capacitance value C of the measured capacitor 5
The applicable range of (F) was set to 0.01 (μF) to 1000 (μF).

Applying the above conditions to the equation (1), the equation (1) is expressed by the following equation (2).

Zc≈0 (Ω) (2) Next, an AC voltage e ₀ (FIG. 3 (c)) represented by the following equation (3) is generated on the secondary side of the detection transformer 7.

e ₀ ∝e (3) Continuing, in terms of direct current, the leakage current of the measured capacitor 5 is expressed by the following equation (4).

However, I _L : DC current value flowing through the measured capacitor 5
(A) Rc: Insulation resistance value of the measured capacitor 5 (Ω) R: Resistance value of the protection resistor 6 (Ω) E: DC applied voltage (V) Here, in the present invention, the resistance value of the protection resistor 6 is 1 (KΩ) and the maximum direct current applied voltage E (V) was 150 (V). Furthermore, the insulation resistance value Rc (Ω) of the measured capacitor 5 is usually
(MΩ) to several 10,000 (MΩ).

Applying the above conditions to the equation (4), the equation (4) is expressed by the following equation (5).

I _L ≈0 (A) (5) The AC voltage e ₀ generated on the secondary side of the detection transformer 7 is amplified by the amplification factor set by the AC voltage amplifier 8,
The AC-DC conversion amplifier 9 converts the AC into the DC, and the voltage is amplified by the set amplification factor. The output voltage E ₀ (FIG. 3 (d)) of the AC-DC conversion amplifier 9 is represented by the equation (6) having the following relationship.

E ₀ ∝e ₀ (6) Next, the output voltage E ₀ is compared with the output voltage Vref−A of the threshold value setting unit A 10 by the comparison amplifier A 11, and E ₀ >
It becomes Vref-A, and the output of the comparison amplifier A11 becomes "0" as shown in FIG. 3 (e). Next, in the 3-input AND gate of AND-A13, the AND of the output of the comparison amplifier A11, the output () of the FF-B22 and the output of the clock signal generation circuit 12 is not formed, and the output of the AND-A13 is "0". ", And the disconnection failure display unit 25 displays the result of" non-defective product "(Fig. 3 (f)).

On the other hand, at the input terminal of the integral type current-voltage conversion amplifier 26,
DC current I _L (A) according to the above equation (5) is input, and current −
The voltage is converted and integrated, the voltage is amplified by the set amplification factor, the AC component is integrated and is not output, and the output terminal of the integral type current-voltage conversion amplifier 26 is expressed by the equation (7) having the following relationship. The output voltage Es (Fig. 3 (g)) is output.

Es∝I _L (7) The output voltage Es is compared with the output voltage Vref−B of the threshold value setting unit B28 by the comparison amplifier B27, and Es <Vref
-B, and as shown in FIG. 3 (h), the comparison amplifier B27
Output becomes "0". The AND-E29 three-input AND gate does not form a logical product for the output of the comparison amplifier B27, the output of the FF-D (), and the output of the clock signal generation circuit 12.
The output of AND-E29 is "0", and the short-circuit defect display portion 41 displays the result of "non-defective product" (Fig. 3 (i)).

Next, a case will be described with reference to FIG. 4 in which the capacitor 5 to be measured has a momentary disconnection state that is less than the set value for the disconnection determination time, but is determined to be a good product.

First, when the measured capacitor 5 is in the T ₁ (SEC) disconnection state, the secondary output e of the detection transformer 7 as shown in FIG. 4 (c).
₀ becomes a level close to almost no output only during T ₁ (SEC), and the output E ₀ of the AC-DC conversion amplifier 9 as shown in FIG. 4 (d).
Is E ₀ ≈0.

Next, the output voltage E ₀ is compared with the output voltage Vref-A of the threshold value setting unit A 10 by the comparison amplifier A 11, and E ₀ <
It becomes Vref-A, and as shown in FIG. 4 (e), the output of the comparison amplifier A11 becomes "1" during T ₁ (SEC). Therefore, AND-A
In the 3-input AND gate of 13, the output of the comparison amplifier A11 is "1", the output of () of the FF-B22 is "1", and the output of the clock signal generation circuit 12 is "0" → "1" → "0" → "1". Only between T ₁ (SEC) where the logical product of the continuous signal (Fig. 4 (f)) is configured.
A clock signal is output to the output of AND-A13 (Fig. 4).
(g)).

Next, the counter circuit A14 counts and adds each time the output signal of the AND-A13 rises from "0" to "1".

Here, one cycle period Tc of the clock signal generation circuit 12 is
It is expressed by equation (8).

However, Tc: 1 cycle time of the clock signal generation circuit 12 (SE
C) fc: Oscillation frequency (Hz) of the clock signal generation circuit 12 Next, in the digital comparator section A15, the output of the counter circuit A14 is set to the "set time" t _{1 of the} disconnection determination time setting section 16
Compare (SEC) (Fig. 4 (h)).

Here, the count value of the counter circuit A14 and the "disconnection state" time
The relationship of T ₁ (SEC) is expressed by the following equation (9).

However, N _A : Count value of the counter circuit A14 T ₁ : "Disconnection state" time (SEC) of the measured capacitor 5 Tc: One cycle time of the clock signal generation circuit 12 (SEC) As a result of comparison by the digital comparator unit A15, Since T ₁ <t ₁ , the output of the digital comparator A15 becomes “0” (FIG. 4 (i)). Next, the output timing of the comparison amplifier A11 falls from "1" to "0" (Fig. 4 (e)).
Then, the monostable multivibrator A17 operates and "0" →
A pulse signal of "1" → "0" is generated (Fig. 4).
(j)). When the output signal of the monostable multivibrator A17 falls from "0" to "1", FF-A20
(1) of the output of () and AND-B19 are taken and the logical product is taken.
Input of counter circuit A14 via R-A18 (Fig. 4 (k))
(R) signal, and the counter circuit A14 is reset to the initial state.

Next, the AND-D23 does not have a logical product, and the display of the disconnection defect display section 25 is "non-defective" as shown in FIG. 4 (l).

On the other hand, the display of the disconnection time display section 24 is not displayed because the counter circuit A14 is reset and is in the initial state.

Next, a case will be described with reference to FIG. 5 in which the measured capacitor 5 has a disconnection state that is equal to or greater than the disconnection determination time set value and is determined to be a disconnection defect.

First, when the measured capacitor 5 is in the T ₁ (SEC) disconnection state, as shown in FIG. 5 (c), the secondary output e of the detection transformer 7
₀ is a level close to almost no output only during T ₁ (SEC),
As shown in the figure (d), the output E ₀ of the AC-DC conversion amplifier 9 is E
₀ ≈ 0.

The output voltage E ₀ is compared with the output voltage Vref−A of the threshold value setting unit A 10 by the comparison amplifier A 11 and E ₀ <Vr
ef-A, as shown in FIG. 5 (e), the comparison amplifier A11
Output is "1".

Accordance connexion, the output of the comparison amplifier A11 is a 3-input AND gate of the AND-A13, of FF-B22 () output is configured output the logical product of the clock signal generating circuit 12, T ₁ (SEC) between only AND-
A clock signal is output to the output of A13 (Fig. 5)
(g)). The counter circuit A14 counts and adds by the clock signal of the output of the AND-A13.

Next, in the digital comparator section A15, the counter circuit A
14 output and disconnection determination time setting section 16 “setting time” t ₁ (SE
Compare C). As a result of the comparison, T ₁ ≧ t _{1 and} the output of the digital comparator A15 becomes “1” (see FIG. 5).
(i)). The output of digital comparator A15 is "0".
→ The (Q) output of FF-A20 changes from "0" to "1" at the rising timing of "1" and holds "1" until reset signal 42 is input (Fig. 5 (j)), and FF -(20) output of A20 holds "0" (Fig. 5 (k)).

On the other hand, when the output of the comparison amplifier A11 falls from "1" to "0" (Fig. 5 (e)), the monostable multivibrator A17 operates to pulse "0" → "1" → "0". A signal is generated (Fig. 5 (l)). The output signal of the monostable multivibrator A17 rises from "0" to "1" and FF-
The AND of the (Q) output of A20 and "1" is ANDed in the AND-C21, and the FF-B22 operates by the rising signal of the output of the AND-C21 from "0" to "1". Output is "1" →
Set it to "0" (Fig. 5 (n)), prohibit it so that the AND-A13 logical AND configuration cannot be taken, and cause the next capacitor to be measured 5
The measurement for the disconnection state is prohibited, and the FF-B22 holds it until the reset signal 42 is input.

On the other hand, the output of monostable multivibrator A17 and FF-A20
(-) Output does not form a logical product with AND-B19, and OR-
The output of A18 is "0" (FIG. 5 (m)), and the counter circuit A14 holds the counted state until the reset signal 42 is input.

Next, AND-A23 outputs the (Q) output "1" of FF-A20 and FF-
The logical sum is formed by the () output of C36 and "1", and the display of the disconnection defect display section 25 indicates "disconnection defect".

On the other hand, the display of the disconnection time display unit 24 displays the value T ₁ (SEC) of the output of the counter circuit A14 and indicates that the time of the disconnection state of the measured capacitor 5 is T ₁ (SEC). .

Next, the case in which the measured capacitor 5 has a momentary short-circuit state of less than the short-circuit time set value but is judged to be non-defective
Description will be made with reference to the drawings.

First, as shown in FIG. 6 (c), when the short circuit current Is flows through the measured capacitor 5 for T ₂ (SEC), the output of the integral type current-voltage conversion amplifier 26 is output as shown in FIG. 6 (d). The voltage is Es,
The output voltage Vref-B of the threshold value setting unit B28 is compared by the comparison amplifier B27, and since Es> Vref-B, the output of the comparison amplifier B27 becomes "1" during T ₂ (SEC) (first). Figure 6 (e)).

Next, in the 3-input AND gate of AND-E29, the logical product of the output "1" of the comparison amplifier B27, the output "1" of FF-D38 and the output of the clock signal generation circuit 12 (Fig. 6 (f)). Then, the counter circuit B30 counts and adds by the output of the AND-E29 (Fig. 6 (g)).

Here, the count value of the counter circuit B30 and the "short-circuit state" time
The relationship of T ₂ (SEC) is expressed by the following equation (10).

However, N _B: counter circuit B30 count value T _2: the measured capacitor 5 "short circuit condition" Time (SEC) Tc: 1 cycle time of the clock signal generating circuit 12 (SEC) in digital comparator unit B31 of the counter circuit B30 The output is compared with the “set time” t ₂ (SEC) (FIG. 6 (h)) of the short circuit determination time setting unit 32, and T ₂ <t ₂ , so the output of the digital comparator unit B31 is “0”. (Fig. 6
(i)).

Next, the monostable multivibrator B33 operates at the falling timing (Fig. 6 (e)) of the output of the comparison amplifier B27 from "1" to "0", and "0" → "1" → "0". A pulse signal is generated (Fig. 6 (j)). When the output signal of the monostable multivibrator B33 rises from "0" to "1", the AND of "1" of () output of FF-C is taken by AND-F35, and it is output through OR-B34. (FIG. 6 (k)), it becomes an input (R) signal of the counter circuit B30, and the counter circuit B30 is reset to the initial state.

The AND-H39 does not form a logical sum, and the display of the short-circuit defect display section 41 is "non-defective" as shown in FIG. 6 (l).

On the other hand, the display of the short circuit time display section 40 is not displayed because the counter circuit B is reset and is in the initial state.

Next, in the case where the measured capacitor 5 has a short circuit condition of the short circuit judgment time set value or more and is judged to be a short circuit defect,
It will be described with reference to the drawings.

First, when the capacitor 5 to be measured is short-circuited to T ₂ (SEC), as shown in FIG. 7 (c), when the short-circuit current Is flows through the capacitor 5 to be measured for T ₂ (SEC), as shown in FIG. As shown in d), the output voltage of the integration type current-voltage conversion amplifier 26 becomes Es,
In the comparison amplifier B27, the output voltage Vref-B of the threshold value setting unit B28 is compared with Es> Vref-B, so that the output of the comparison amplifier B27 becomes "1" during T ₂ (SEC) (seventh). (Figure (e)).

Then, in the AND-E29 three-input AND gate, the output of the comparison amplifier B27, the () output of the FF-D38, and the output of the clock signal generation circuit 12 (FIG. 7 (f)) are ANDed, and AND- E29
The counter circuit B30 counts and adds the output.

The digital comparator B31 compares the output of the counter circuit B30 with the "set time" t ₂ (SEC) (Fig. 7 (h)) of the short circuit determination time setting unit 32, and since T ₂ ≥t ₂ , the digital comparator The output of section B31 becomes "1" (Fig. 7).
(i)).

Next, the output of the digital comparator section B31 is "0" →
At the rising timing of "1", the (Q) output of FF-C36 changes from "0" to "1" and holds "1" until reset signal 42 is input (Fig. 7 (j)), and FF-C36. The () output of is held at "0" (Fig. 7 (k)).

On the other hand, the monostable multivibrator B33 operates at the timing of the output of the comparison amplifier B27 falling from "1" to "0" (Fig. 7 (e)), and pulses "0" → "1" → "0". A signal is generated (Fig. 7 (l)). The rising signal of the output signal of the monostable multivibrator B33 from "0" to "1" and FF
AND-G37 ANDs with (1) of (Q) output of -C36, and FF-D38 operates by rising signal of output of AND-G37 from "0" to "1" ( ) Output is "1" →
Set it to "0" (Fig. 7 (n)), and prohibit it so that the AND-E29 logical AND structure cannot be taken.
The FF-D38 holds the reset signal 42 until the reset signal 42 is input.

On the other hand, the output of monostable multivibrator B33 and FF-C36
(-) Output of AND-F35 does not form a logical product, and OR-
The output of B34 is "0" (FIG. 7 (m)), and the counter circuit B30 holds the counted state until the reset signal 42 is input.

Next, AND-H39 outputs FF-C36 (Q) output "1" and FF-A20.
() Output "1" forms a logical product, and the short-circuit defect display section 41 displays "short-circuit defect".

On the other hand, the display of the short circuit time display section 40 displays the value T ₂ (SEC) of the output of the counter circuit B30, indicating that the time of the short circuit state of the measured capacitor 5 is T ₂ (SEC). .

As explained above, when a disconnection or short circuit occurs in the capacitor to be measured, the specified time is compared with the digital value for judgment, and each detected disconnection or short circuit time is displayed and stored as a digital value. You can Also, oscillator, buffer amplifier, superposition transformer, DC test power supply,
A large amount of detection can be performed at the same time by making the clock signal generation circuit common and adding another circuit corresponding to the number of tested capacitors to be measured.

Further, the disconnection time display section and the short circuit time display section are commonly used, and the output data of the counter circuit A and the counter circuit B are made to correspond to each capacitor to be measured by a signal switching IC or the like, so that it is easy and inexpensive. It is possible to provide a device capable of simultaneously performing a large amount of detection.

EFFECTS OF THE INVENTION As described above, the capacitor disconnection short-circuit detection device according to the present invention has the following effects.

(1) There is no need to prepare special equipment.

(2) The judgment can be made by the absolute value, and the detection accuracy is high.

(3) A lot of capacitors can be inspected at one time.

(4) It is possible to provide an inexpensive device that is easy to maintain.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a capacitor disconnection short-circuit detection device according to the present invention, and FIG. 2 is a diagram showing signals for operating the circuit shown in FIG. Fig. 3 is a signal waveform diagram of each part when the capacitor to be measured is normal, and Fig. 4 is a signal waveform diagram of each part when the capacitor to be measured has an instantaneous disconnection state that is less than the set value for the disconnection determination time, but is judged to be a good product. Fig. 5 is a signal waveform diagram of each part when the measured capacitor has a disconnection state that is equal to or greater than the set value for the disconnection determination time and determines disconnection failure. Fig. 6 shows the measured capacitor's instantaneous value below the short circuit determination time setting. A signal waveform diagram of each part when a short circuit occurs but a good product is judged,
FIG. 7 is a signal waveform diagram of each part in the case where the capacitor to be measured has a short circuit state of the short circuit determination time set value or more and it is determined that there is a short circuit failure. 1 ... Oscillator, 2 ... Buffer amplifier, 3 ... Superposition transformer,
4 ... DC test power supply, 5 ... Capacitor to be measured, 6 ...
Protective resistance, 7 ... Detection transformer, 8 ... AC voltage amplifier,
9 ... AC-DC conversion amplifier, 10 ... Threshold value setting unit A, 11 ... Comparison amplifier A, 12 ... Clock signal generation circuit, 13 ... AND-A, 14 ... Counter circuit A, 1
5 …… Digital comparator A, 16 …… Disconnection judgment time setting unit, 17 …… Monostable multivibrator A, 18 ……
OR-A, 19 …… AND-B, 20 …… FF-A, 21 …… AND-
C, 22 ... FF-B, 23 ... AND-D, 24 ... disconnection time display section, 25 ... disconnection failure display section, 26 ... integral type current-voltage conversion amplifier, 27 ... comparison amplifier B, 28: Threshold value setting section B, 29 ... AND-E, 30 ... Counter circuit B, 31 ... Digital comparator section B, 32 ... Short circuit judgment time setting section, 33 ... Monostable multivibrator B ,
34 …… OR-B, 35 …… AND-F, 36 …… FF-C, 37 …… A
ND-G, 38 ... FF-D, 39 ... AND-H, 40 ... Short circuit time display section, 41 ... Short circuit failure display section, 42 ... Reset signal, e ... AC applied voltage, E ... DC applied voltage, e ₀ ...
The secondary side of the output voltage of the detector transformer 7, E ₀ ...... AC - output voltage of the DC converter amplifier 9, Is ...... current during short-circuit of the measuring capacitor 5, leakage current I _L ...... measured capacitor 5 , Es
The output voltage of the integral-type current-voltage conversion amplifier 26, Vref-
A: Output voltage of threshold value setting unit A10, Vr
ef−B …… Output voltage of threshold value setting section B28

Claims (1)

[Claims] 1. An oscillator for generating an AC signal is connected to a primary winding terminal, and a secondary winding is provided with a superposition transformer in which a DC test power source and one end of a capacitor to be measured are connected to the terminal. The other end is connected to an integral type current-voltage conversion amplifier via a protection resistor and a primary winding of the detection transformer, and an AC amplifier and an AC-AC are connected to a secondary winding terminal of the detection transformer.
A first comparison amplifier having a first threshold value setting unit is provided via a DC conversion amplifier, and a first 3-input AND gate serving as a signal suppression gate is provided from the output of the first comparison amplifier. A clock signal generator for sending a clock signal only in the disconnection state is connected to the 3-input AND gate 1 and a first counter circuit for counting the disconnection time is connected to the output of the first 3-input AND gate. A first digital comparator section is provided for comparing the set value of the judgment time with the disconnection time output from the first counter circuit and outputting a comparison result. The first counter circuit is provided only when the first disconnection defect is judged. Data is displayed on the disconnection time display section, data is displayed on the disconnection failure display section as disconnection failure, and the output of the integral type current-voltage converter is set to the second switch. It is connected to a second comparator amplifier having Tsushuhorudo value, provided the second 3-input AND gate composed signal suppression gate from the output of the comparison amplifier, the second
To the 3-input AND gate of the above-mentioned clock signal generator which outputs a clock signal only in the case of a short circuit, and to the output of the second 3-input AND gate of the second counter circuit for counting the short-circuit time, A second digital comparator section is provided which compares the time set value with the short circuit time output from the second counter circuit and outputs a comparison result, and the second digital comparator section of the second counter circuit is provided only when the first short circuit failure is determined. A capacitor disconnection short-circuit detection device, which holds data and displays the data on a short-circuit time display unit and displays a short-circuit defect on the short-circuit defect display unit.