JPH0638472B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing an integrated circuit device in which a silicon gate MOS field effect transistor and a bipolar transistor are formed on the same substrate.

[Conventional technology]

Integrated circuit (hereinafter referred to as Bi-CMOS IC) in which a bipolar transistor and a complementary field effect transistor (hereinafter referred to as CMOS transistor) are formed on the same substrate.
In recent years, many attempts have been reported because the low power consumption operation of the CMOS transistor and the high speed operation and high driving capability of the bipolar transistor can be realized at the same time.

FIG. 3 shows a cross-sectional view of a Bi-CMOS device formed by an example of a manufacturing process of a Bi-CMOS IC that has been conventionally reported. The manufacturing process will be described step by step with reference to FIG. 3. The N ⁺ type buried region 2 and the P ⁺ type buried region 3 are formed on the P type substrate I, and then the N type epitaxial layer 4 is grown to form the NchMOSFFT. A P-type region 5 is formed in the formation region and the bipolar isolation region, an N-type well region 6 is formed in the PchMOSFFT formation region, and an element isolation oxide film 8 is formed. Next, after forming the gate oxide film, the gate polycrystalline silicon layer 9 and the bipolar base region 10 are formed, and after opening the emitter diffusion window of the bipolar transistor, the second polycrystalline silicon layer 13 is covered with the emitter diffusion window. To form. The source / drain region of the Nch MOSFET and the emitter region 15 of the bipolar transistor are simultaneously formed, and the base contact region 17 of the bipolar transistor of the source / drain region of the Pch MOSFET is formed.

As described above, an example of the Bi-CMOS process corresponding to the recent speeding up is shown. According to this process, a second layer is formed on the emitter diffusion window for speeding up the bipolar transistor.
By forming the polycrystalline silicon layer of, it is not necessary to consider the mask misalignment of the contact that is opened when the electrode wiring is drawn out, the emitter area can be made small, and the emitter of the bipolar transistor and the Nch MOSFET can be formed.
Since the source / drain region, the base contact region of the bipolar transistor, and the source / drain region of the Pch MOSFET are simultaneously formed, there is an advantage that the process is simplified. However, between the second polycrystalline silicon layer formed so as to cover the emitter diffusion window and the base region, there is only the gate oxide film or the patterned oxide film having the same thickness as that of the gate oxide film. The capacity is increasing more than necessary. In addition, the diffusion layer tends to become shallower as the bipolar transistor becomes faster and the CMOSFET becomes finer. However, in the conventional process, emitter pushing (h _FE control) and Nch MOSFET source / drain formation are performed simultaneously. If the emitter push-in time is shortened to increase the speed of the bipolar transistor, N
The source / drain regions of the chMOSFET also become shallow,
There are drawbacks such as problems such as hot electrons that cannot be applied to miniaturization.

[Problems to be solved by the invention]

As described above, in the Bi-CMOS process according to the conventional method, the second polycrystalline silicon layer is used and the emitter region can be made small in order to increase the speed. However, the second polycrystalline silicon layer and the base region can be reduced. In spite of the gate oxide film or the patterned oxide film having a fine emitter region having the same thickness as the gate oxide film, a sufficient speedup cannot be obtained. In addition, the emitter region of the bipolar transistor and the NchMOSFE
Since the source / drain region of T is formed at the same time, if the emitter is made shallow to increase the speed of the bipolar transistor, the source / drain region of the Nch MOSFET is
The drain region also becomes shallower, causing problems such as hot electrons, which is a drawback that it cannot be applied to miniaturization.

An object of the present invention is to provide a method for manufacturing a semiconductor device capable of manufacturing a Bi-CMOS IC, which enables miniaturization of a MOSFET without deterioration of characteristics of a bipolar transistor as described above.

[Means for solving problems]

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device including a silicon gate MOS field effect transistor and a bipolar transistor on one semiconductor substrate, wherein a gate polycrystalline silicon layer of the silicon gate MOS field effect transistor is provided. And the N-type source
A step of forming a drain region, a step of forming a silicon oxide film having a predetermined thickness on the entire surface of the semiconductor substrate,
Opening the emitter diffusion layer of the bipolar transistor, forming a second polycrystalline silicon layer thinner than the gate polycrystalline silicon layer so as to cover the emitter diffusion window of the bipolar transistor, and the second polycrystalline Anisotropically dry etching the silicon layer and the silicon oxide film to leave the second polycrystalline silicon layer in the emitter region of the bipolar transistor and to leave the silicon oxide film on the side wall of the gate polycrystalline silicon; It comprises a step of forming N ⁺ source / drain regions of the emitter and the MOS field effect transistor, and a step of forming base contact regions and P ⁺ source / drain regions of the bipolar transistor.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings. 1A to 1D are cross-sectional views of a semiconductor device shown in the order of steps for explaining an embodiment of the present invention.

First, as shown in FIG. 1A, the N ⁺ type buried layer 2 and the P ⁺ buried layer 3 are formed on the P type substrate 1, and the N type epitaxial layer 4 is grown. A P-type well region 5 is formed in the NMOSFET forming region and the bipolar isolation region, and the PMOSF
The N-type well region 6 is formed in the ET formation region. Next, an N ⁺ region 7 is formed in the collector portion of the bipolar transistor, an isolation oxide film 8 is selectively formed, and a gate polycrystalline silicon 9 of the MOSFET and a base region 10 of the bipolar transistor are formed.

Next, as shown in FIG. 1B, the n-type source / drain region 12 of the NMOSFET is formed, and the silicon oxide film layer 19 is formed by, for example, the CVD method.

Next, as shown in FIG. 1C, the emitter diffusion window 11 of the bipolar transistor is opened, and the second polycrystalline silicon layer 13 is formed so as to cover the emitter diffusion window. At this time, the minimum dimension is 2 μm. When using the above process, the mask misalignment at the time of contact opening when drawing out the wiring is 2 μm
The width of the second polycrystalline silicon layer is
6 μm or more is required. According to the conventional method, a thin oxide film (50) is formed between the second polycrystalline silicon layer and the base region.
Since there is only 0 Å), the capacitance between the emitter and the base will be the MOS type capacitance in addition to the junction capacitance. Now, for example, when a silicon oxide film is grown to about 2500 Å, the oxide film thickness between the emitter and the base becomes 3000 Å, and the MOS type capacitance is reduced to 1/6. After the formation of the second polycrystalline silicon layer, anisotropic dry etching is performed to leave the second polycrystalline silicon on the emitter region of the bipolar transistor and the oxide film layer 18 on the side surface of the gate polycrystalline silicon layer. Next, the N ⁺ type source / drain region 14 of the NMOSFET and the emitter region 15 of the bipolar transistor are simultaneously formed.

Next, as shown in FIG. 1D, the source / drain region 16 of the PMOSFET and the base contact region 17 of the bipolar transistor are simultaneously formed.

FIG. 2 is a sectional view of a semiconductor device formed according to the second embodiment of the present invention. The second embodiment is an example in which, in addition to the first embodiment, the respective diffusion layers and polycrystalline silicon are metallized with a high melting point.

In this embodiment, since an oxide film region is added between the second polycrystalline silicon layer and the base region, a problem such as a short circuit between the emitter and the base occurs when silicidation is performed in a self-aligned manner. Disappear. Further, since the oxide film layer is formed on the side surface of the gate polycrystalline silicon layer, there is an advantage that the silicidation of the gate polycrystalline silicon layer and the source / drain regions can be performed in a self-aligned manner.

〔The invention's effect〕

As described above, according to the present invention, the gate-polycrystalline silicon layer is formed and then the silicon oxide film layer is formed, whereby the capacitance between the emitter and the base can be reduced, the speed of the bipolar transistor can be increased, and a MOSFET can be formed. On the other hand, there is an effect that the shape becomes an LDD structure and it can cope with miniaturization.

In addition, since the oxide film between the emitter and the base can be made sufficiently thicker than before and the oxide film layer is on the side surface of the gate polycrystalline silicon layer, the surface of the diffusion layer and the polycrystalline silicon layer are self-aligned to form a refractory metal silicide. Therefore, there is also an advantage that the speed can be increased in both bipolar and CMOS.

[Brief description of drawings]

1 (a) to 1 (d) are cross-sectional views of a semiconductor device shown in order of steps for explaining an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a semiconductor device for explaining another embodiment. , FIG. 3 is a sectional view of a semiconductor device for explaining the prior art. 1 ... P-type semiconductor substrate, 2 ... N ⁺ buried region, 3 ... P
⁺ Type buried region, 4 ... N type epi region, 5 ... P type well region, 6 ... N type well region, 7 ... N ⁺ type collector region, 8 ... Isolation oxide film, 9 ... Gate Polycrystalline silicon,
10 ... P-type base region, 11 ... Emitter diffusion window, 1
2 ... N-type source / drain region, 13 ... second polycrystalline silicon layer, 14 ... N ⁺ -type source / drain region, 15
...... Emitter region, 16 ・ ・ ・ P ⁺ type source / drain region, 17 ・ ・ ・ Base contact region, 18 ・ ・ ・ Side oxide film region, 19 ・ ・ ・ Silicon oxide film layer, 20 ・ ・ ・ High melting point silicide layer.

Claims (1)

[Claims] 1. A silicon gate MOS on one semiconductor substrate.
Type semiconductor device including a field effect transistor and a bipolar transistor
Forming a gate polycrystalline silicon layer of an OS type field effect transistor, forming N type source / drain regions, and forming a silicon oxide film thicker than at least a gate oxide film or a pattern oxide film on the entire surface of the semiconductor substrate. A step of forming an emitter diffusion window of the bipolar transistor, a step of forming a second polycrystalline silicon layer thinner than the gate polycrystalline silicon layer so as to cover the emitter diffusion window of the bipolar transistor, Anisotropic dry etching is performed on the second polycrystalline silicon layer and the silicon oxide film to leave the second polycrystalline silicon layer in the emitter region of the bipolar transistor and to leave the silicon oxide film on the side wall of the gate polycrystalline silicon. Process, emitter of the bipolar transistor and the M The method of manufacturing a semiconductor device which comprises forming a N ⁺ source and drain regions of the S-type field effect transistor, and forming a base contact region and the P ⁺ source and drain regions of said bipolar transistor.