JPH0638484B2 - Semiconductor memory device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor memory device which is extremely reliable in an ultra-high speed bipolar memory without malfunction due to α rays.

[Conventional technology]

FIG. 3 is a diagram showing a bipolar memory cell circuit. In FIG. 3, R ₁ and R ₂ are resistors, D ₁ and D ₂ are diodes, Q ₁ and Q ₂ are multi-emitter transistors (hereinafter simply referred to as transistors), and C _T1 and C _T2 are the transistors Q ₁ and collector-base parasitic capacitance of Q _2, I 1 ~I ₃ is a current source.

Retention of information in this bipolar memory cell circuit is
This is done by the stable state of the flipper flop circuit. However, information inversion may occur due to α rays emitted from the package or the like. That is, when the transistor Q ₁ is turned on, the transistor Q ₂ is turned off, and although the collector potential V _C2 of the transistor Q ₂ is at a high potential than the collector potential V _C1 of the transistor Q _1, alpha rays incident generated Among the generated electron hole pairs, those generated in the collector-base depletion layer region flow through the collector-base parasitic capacitance C _T2 and generate noise current. As a result, information inversion occurs in which the collector potential V _C2 of the transistor Q ₂ is lowered.

Next, referring to FIGS. 4 (a) to 4 (f), the transistors Q ₁ , which form the bipolar memory cell circuit shown in FIG.
The manufacturing process of Q ₂ will be described.

In these figures, 1 is a silicon substrate, 2 is an n ⁺ type floating collector region, and 3 is a collector region.
Type epitaxial layer, 4 an underlying oxide film layer, 5 a nitride film layer, 6 a resist, 7 a p-type channel cut layer, 8 a field oxide film, 9 an n ⁺ type collector wall region, 1
0 is a p-type base region, 11 is an n ⁺ -type emitter region, 12
Is a base electrode, 13 is an emitter electrode, and 14 is a collector electrode.

First, as shown in FIG.
^{After the +} type floating collector region 2 is formed by diffusion, an n type epitaxial layer 3 to be a collector region is formed, and further an underlying oxide film layer 4, a nitride film layer 5 and a resist 6 are formed and isolation patterning is performed. . Next, as shown in FIG. 4B, after etching the n-type epitaxial layer 3, channel-cutting boron is implanted to form the p-type channel-cutting layer 7. Next, as shown in FIG. 4C, after removing the resist 6, field oxidation is performed using the nitride film layer 5 as a mask to form a field oxide film 8. Next, as shown in FIG. 4D, the n ⁺ type collector wall region 9 and the p type base region 10 are formed. Then, as shown in FIG. 4 (e), n
^{A +} type emitter region 11 and contact holes for the base, the emitter and the collector are formed. Finally, as shown in FIG. 4 (f), the base electrode 12 and the emitter electrode 1
3, the collector electrode 14 is formed.

[Problems to be solved by the invention]

In the conventional bipolar memory as described above, in order to prevent the information from being inverted by the noise current caused by α rays,
The collector-base parasitic capacitances C _T1 and C _T2 may be increased to improve the critical charge amount, but the collector-base parasitic capacitances C _T1 and C _T2 are limited because they are proportional to the base area. The method of increasing the concentration of the n-type epitaxial layer 3 makes it difficult to control the grounded emitter forward current amplification factor h _FE . Further, there is a problem that the collector-base parasitic capacitances C _T1 and C _T2 must be reduced in order to increase the speed of the bipolar memory.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a semiconductor memory device which does not malfunction due to a noise current caused by α rays.

[Means for solving problems]

A semiconductor memory device according to the present invention includes a first-conductivity-type floating collector region formed on a semiconductor substrate, a first-conductivity-type collector wall region partially formed on the floating-collector region, and a collector. A first conductivity type collector region formed on a part of the floating collector region adjacent to the wall region through a field oxide film; a second conductivity type base region formed on the collector region; In a flip-flop type semiconductor memory device composed of a bipolar transistor including a first conductivity type emitter region formed on a base region, a collector is provided on a lower surface of a field oxide film provided between a collector wall region and a base region. High impurities formed in contact with the wall region and connected to the base region Those having a semiconductor region of a second conductivity type in degrees.

[Action]

In the present invention, the collector-base capacitance can be increased without changing the concentration of the collector region and the effective base width.

〔Example〕

FIG. 1 is a diagram showing an embodiment of a semiconductor memory device of the present invention. In FIG. 1, the same symbols as those in FIGS. 4A to 4F indicate the same portions, and 15 is a p ⁺ -type region which becomes a second conductivity type semiconductor region with a high impurity concentration.

In the semiconductor memory device of the present invention, the field oxide film 8 between the n ⁺ type collector wall region 9 and the p type base region 10 is formed.
High impurity concentration p ⁺ type region 15 formed along the lower surface of the
However, since a pn junction having a high impurity concentration is formed with the n ⁺ type collector wall region 9 and the n ⁺ type floating collector region 2, the collector-base parasitic capacitance C _T becomes extremely large. Further, since the p ⁺ type region 15 is the external base of the npn transistor and the effective base width of the npn transistor does not change, it is easy to suppress the grounded emitter forward current amplification factor h _FE . Therefore, the amount of critical charge increases and the information retention capability increases. Further, the transistors forming the peripheral circuit do not have such a structure so that the high speed is not impaired.

Next, the manufacturing process will be described with reference to FIGS. In these figures, the same reference numerals as those in FIG. 1 indicate the same or corresponding parts.

First, as shown in FIG.
^{After the +} type floating collector region 2 is formed by diffusion, an n type epitaxial layer 3 to be a collector region is formed. Then, as shown in FIG. 2B, the underlying oxide film layer 4 and the nitride film layer 5 are formed. Then, FIG. 2 (c)
As shown in, a resist 6 is formed and separation patterning is performed. Next, as shown in FIG. 2D, the nitride film layer 5 is etched, and boron is implanted through the underlying oxide film layer 4. Then, as shown in FIG.
The field portion between the collectors is covered with a resist 6, and the underlying oxide film layer 4 is etched. Then, as shown in FIG. 2F, the n-type epitaxial layer 3 is etched, and thereafter, boron is implanted for channel cutting to form the p-type epitaxial cut layer 7. Then, as shown in FIG. 2 (g), the resist 6 is removed. Next, as shown in FIG. 2H, field oxidation is performed using the nitride film layer 5 as a mask to form a field oxide film 8. At this time, a high impurity concentration p ⁺ type region 15 is formed along the lower surface of the field oxide film 8 between the base and the collector. Next, as shown in FIG. 2I, the n ⁺ type collector wall region 9 is formed, but at this time, the p ⁺ type region 15 is reduced.

Next, when the p-type base region 10 is formed, the p-type base region 10 and the p ⁺ -type region 15 are connected as shown in FIG. 2 (j). Next, as shown in FIG. 2 (k), n ⁺ type emitter regions 11 and base, emitter, and collector contact holes are formed. Finally, as shown in FIG. 2 (l), a base electrode 12, an emitter electrode 13, and a collector electrode 14 are formed.

The field oxide film 8 between the core and base may be formed at the same time as the isolation oxide film, or may be formed separately from the isolation oxide film.

〔The invention's effect〕

As described above, the present invention has the first conductive type floating collector region formed on the semiconductor substrate and the first conductive type first portion formed on the floating collector region.
A conductive type collector wall region, a first conductive type collector region formed on a part of the floating collector region adjacent to the collector wall region via a field oxide film, and a first conductive type collector region formed on the collector region. In a flip-flop type semiconductor memory device constituted by a bipolar transistor having a two-conductivity type base region and a first-conductivity type emitter region formed on the base region, the flip-flop type semiconductor memory device is provided between the collector wall region and the base region. Since the second conductivity type semiconductor region having a high impurity concentration is formed on the lower surface of the field oxide film and in contact with the collector wall region and connected to the base region,
It is possible to obtain a semiconductor memory device that does not malfunction due to noise current caused by lines. Further, at the time of manufacturing, since the second conductivity type semiconductor region can be formed with a high impurity concentration by self-alignment of the mask for the oxide film separation step, it is not necessary to add a mask, and the effective base width is equal to that of the memory cell and the peripheral transistor. Therefore, there is an advantage that it is easy to match the characteristics of the bipolar transistors in the memory cell section.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of a semiconductor memory device of the present invention, and FIGS. 2 (a) to (l) are diagrams showing the same manufacturing process.
FIG. 3 is a diagram showing a bipolar memory cell circuit, and FIGS. 4 (a) to 4 (f) are diagrams showing a manufacturing process of a conventional bipolar transistor. In the figure, 1 is a silicon substrate, 2 is an n ⁺ type floating collector region, 3 is an n type epitaxial layer, 4 is an underlying oxide film layer, 5 is a nitride film layer, 6 is a resist, 7 is a p-type channel cut layer, 8 Is a field oxide film, 9 is an n ⁺ -type collector wall region, 10 is a p-type base region, and 11 is n.
^{A +} type emitter region, 12 is a base electrode, 13 is an emitter electrode, 14 is a collector electrode, and 15 is ap ⁺ type region. The same reference numerals in each drawing indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A first conductive type floating collector region formed on a semiconductor substrate, a first conductive type collector wall region formed on a part of the floating collector region, and the collector wall region. A first conductivity type collector region formed on a part of the floating collector region adjacent to each other via a field oxide film, a second conductivity type base region formed on the collector region, and a base region on the base region. In a flip-flop type semiconductor memory device formed by a bipolar transistor having a first conductivity type emitter region formed in a collector region, the collector is located below the field oxide film provided between the collector wall region and the base region. Of high impurity concentration formed in contact with the wall region and connected to the base region The semiconductor memory device characterized by comprising a second conductivity type semiconductor region.