JPH0638497B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device having a field effect transistor.

[Background of the Invention]

A field effect transistor (FET) is a transistor that controls the current by changing the conductivity of a current path between two electrodes (source and drain) with a third electrode (gate). A conventional field effect transistor (for example, Japanese Patent Publication No. 51-740)
See No. 35. 2), impurities are introduced at a high concentration near the surface of the semiconductor substrate, which serves as a current path, by, for example, an ion implantation technique. The main purpose of introducing the impurities is to set the threshold voltage of the device to a desired value. However, in the conventional field effect transistor, due to the presence of this high-concentration impurity layer, carriers (electrons / holes)
However, there is a problem that the mobility of the device is lowered and the improvement of the transfer conductance gm of the device is hindered.

[Object of the Invention]

An object of the present invention is to provide a method of manufacturing a semiconductor device having a field-effect transistor, which can obtain a desired threshold voltage, reduce a decrease in carrier mobility, and improve transfer conductance. Especially.

[Outline of Invention]

In a field effect transistor (for example, a MOSFET formed on a Si substrate), an inversion layer near the Si substrate surface, which is a current path, is generally about 100 Å from the Si substrate surface.
With a thickness of. The threshold voltage of a MOSFET is generally
It is determined by the concentration of impurities from the surface of the Si substrate to a depth of about 1 μm. From the above two points, the carrier mobility is high by reducing only the impurity concentration in the extremely thin region of about 100 to 300 Å on the Si substrate surface (reducing the impurity concentration in the carrier, that is, the portion through which the current flows).
That is, it is possible to realize a field effect transistor having a large transfer conductance gm and a desired threshold voltage V _{TH of the} element.

That is, the present invention relates to a semiconductor device having a field effect transistor formed on the surface of a semiconductor substrate (including a semiconductor layer formed on another substrate), in which a region in which a current flows (a current passage region). Of the desired threshold voltage value by controlling the total impurity concentration (which means the sum of the p-type impurity concentration and the N-type impurity concentration) below the total impurity concentration of other regions of the semiconductor layer. When,
The present invention provides a method of manufacturing a semiconductor device that simultaneously realizes a high transfer conductance gm.

That is, according to the method of manufacturing a semiconductor device of the present invention, the surface of the semiconductor substrate is oxidized on the surface region of the semiconductor substrate which becomes the current passage region of the MOS field effect transistor containing the impurity of the first conductivity type having a predetermined impurity concentration. To form an oxide film, the impurities are absorbed in the oxide film,
Forming a current passage region having an impurity concentration lower than that of the surface region in the surface region; removing the oxide film; and forming a gate electrode on the current passage region via a gate insulating film. And forming a source / drain region of a second conductivity type opposite to the first conductivity type on the surface region of the semiconductor substrate on both sides of the gate electrode.

Example of Invention

FIG. 1 shows n manufactured by the method for manufacturing a semiconductor device of the present invention.
It is sectional drawing of a channel MOSFET. In the figure, 1
Is a p-type Si substrate doped with p-type impurities, and 2 and 3 are n
Source and drain regions comprised of the high concentration impurity layer of the mold, 4 is a gate electrode, 5 denotes a gate oxide film 6 is less total impurity concentration N _T formed in the current path region near the surface of the Si substrate 1 Low A concentration impurity layer, 7 indicates a depletion layer when the gate electrode is just biased to the threshold voltage.

The threshold voltage V _{TH of the} MOSFET is expressed by the following equation.

Here, φ _MS is the work function difference between the gate electrode material and the substrate Si, φ _F is the Fermi voltage, C _O is the unit gate capacitance, and E _s
Is the dielectric constant of Si, q is the unit charge amount, N _A is the impurity concentration of the p-type Si substrate 1, to be exact, p-type Si immediately below the gate electrode 4.
It is the impurity concentration of the portion in the depletion layer 7 of the substrate 1.

In the MOSFET of FIG. 1, when polycrystalline Si containing N-type impurities, which is often used in integrated circuit technology, is used as the gate electrode material, φ of formula (1) is used.
_Since the value of _MS is -0.9V and 2φ _F is about 0.6V, the impurity concentration of the Si substrate 1 is set to realize an enhancement type element (V _TH > 0.5V) capable of switching operation in the n-channel MOSFET. N _A should be chosen to satisfy the following equation:

Here, _assuming that the gate oxide film thickness T _OX is 25 nm, equation (2)
Therefore, it is necessary to use a Si substrate containing p-type impurities with a very high concentration of N _A > 6.12 × 10 ¹⁶ (cm ⁻³ ).

FIG. 2 shows the relationship between the gate oxide film thickness T _OX and the value of the impurity concentration N _A of the Si substrate 1 for making the threshold voltage V _{TH of the} device 0.5 V from the equation (2). As is clear from the figure, when the film thickness T _ox is reduced in order to improve the performance of the MOSFET, the value of N _A increases rapidly in proportion to (T _ox ) ⁻² . That is, in order to realize a high performance integrated circuit device, it is necessary to use a Si substrate having a large N _A value.

Here, the low-concentration impurity layer 6 in FIG. 1 has a small effect on the threshold voltage of the element because the amount of impurities contained in the layer is small. Therefore, it can be considered that the threshold voltage of the element is almost determined by the equation (2).

On the other hand, the mobility μe of carriers (electrons in the case of an n-channel MOSFET) that determines the transfer conductance gm of the MOSFET has a value shown in FIG. 3 in relation to the total impurity concentration N _{T in the} vicinity of the Si substrate surface ( However, at room temperature). Therefore, in the conventional MOSFET, N _{T in the} vicinity of the Si substrate surface where carriers flow is the N _T of the Si substrate.
_{In a} device larger than (or almost the same as) _A , for example, the value of N _{A in} the other region of the Si substrate when T _OX = 25 nm is 6.12.
Considering × 10 ¹⁶ cm ^-3 , μe becomes 700 cm ² / V ・ sec or less, and when N _T = 10 ¹⁵ cm ^-3 (μe = 1300 cm ² / V ・ sec)
As compared with the above, the value of μe is reduced to about 1/2, and as described above, there is a problem that the transfer conductance gm of the element is reduced.

As described above, according to the MOSFET shown in FIG. 1, by providing the low-concentration impurity layer 6 having a low total impurity concentration N _{T on} the surface of the Si substrate through which carriers flow, the mobility μe of carriers is large, that is, Transfer conductance g
We were able to realize an enhancement-type MOSFET with a large m and capable of switching operation.

As described in the description of FIG. 1, the impurity concentration N _A of the Si substrate 1 which determines the threshold voltage of the device, N inside the depletion layer 7 of the portion under the gate electrode 4 is exactly _A of a value, it remains unchanged at all the above discussion, even if the N _a of the depletion layer inside the depletion layer outside are different is evident.

FIG. 4 shows p manufactured by the method for manufacturing a semiconductor device of the present invention.
It is sectional drawing of a channel MOSFET. This MOSFET
, 1'is an n-type Si substrate, 2'and 3'is p
Source / drain regions 4'of high-concentration impurity layers
Is, for example, a gate electrode formed of n-type polycrystalline Si,
5'is a gate oxide film, 6'is an enhancement type MOS
This is a p-type low-concentration impurity layer provided to form an FET. In this embodiment, when n-type polycrystalline Si is used for the gate electrode material in order to obtain a desired threshold voltage value (for example, V _TH = −0.5V), the n-type Si substrate 1 ′ is used. It is well known that it is necessary to make the surface of p-type. As shown in FIG. 5, the present MOSFET is characterized in that the p-type impurity layer formed on the surface of the Si substrate cancels the impurity concentration N _D of the n-type substrate Si, and has a larger N _A than the value of N _D. Unlike the conventional structure in which the surface of the substrate is doped with the above-mentioned impurities, the impurity layer having a desired N _A is formed on the Si substrate surface not containing N _D. In this MOSFET, the effective p-type impurity concentration N on the Si substrate surface
_Ae is the same as that of the conventional element, and therefore the threshold voltage value of the element is the same as that of the conventional element. However, the value of the total impurity concentration N _{T in} the current path through which carriers (holes in this embodiment) on the surface of the Si substrate flow is as shown in the following equation between the conventional element and this MOSFET.

N _T (conventional device) = 2N _D + N _Ae N _T (this embodiment) = N _Ae Obviously, in this MOSFET, N _T is low, and thus an enhancement p-channel MOSFET having a large transfer conductance can be realized.

FIGS. 6A to 6C are process cross-sectional views showing an embodiment of the method for manufacturing a semiconductor device of the present invention.

First, as shown in FIG. 6A, the MOSFE is formed in a portion where a MOSFET of a p-type Si substrate 1 (including a p-type impurity having an impurity concentration of about 10 ¹⁵ cm ⁻³ , for example, B (boron)) is formed.
A p-type impurity layer 8 for controlling the threshold voltage of T is formed by, for example, an ion implantation technique. After that, when the surface of the Si substrate 1 is subjected to wet oxidation in a water vapor atmosphere at 920 ° C. and 6 atmospheres for 30 minutes, an oxide film 9 having a thickness of about 100 nm is formed. As is well known, the oxide film 9 formed by this wet oxidation absorbs p-type impurities (boron) in the vicinity of the surface of the Si substrate 1 that is in contact with the oxide film 9, and thus in the vicinity of the surface of the Si substrate 1. The impurity concentration of boron is
The concentration is rapidly reduced (about 1/10 of the concentration), and the low concentration impurity layer 6 is formed in a shallow region of about 70 nm from the surface (FIG. 6 (b)).

Next, the oxide film 9 is removed by a chemical etching method or the like, and then a gate oxide film 5 to be a gate insulating film of the MOSFET is newly formed by oxidation. A gate electrode material having good conductivity, for example, an n-type polycrystalline Si layer is deposited on the gate oxide film 5 and removed by etching to leave only a portion to be a gate electrode, thereby forming a gate electrode 4 of MOSFET.
Then, using the gate electrode 4 as a mask for ion implantation, n
Type impurities are introduced to form n-type source / drain regions 2 and 3 (FIG. 6 (c)).

FIGS. 7 (a) and 7 (b) are diagrams showing the results of measuring the current characteristics of the n-channel MOSFET formed according to the embodiment of FIG. 6 in comparison with the conventional one. MOSFET conditions are
In both the conventional and the present invention, the gate oxide film thickness is 8.4 nm, the distance between the source and drain regions is 0.95 μm, and the impurity concentration near the surface is 10 ¹⁷ cm ^{-3 in the} prior art and 10 ¹⁵ cm ^-3 in the present invention. . From this figure, it can be seen that the element embodying the present invention has a transfer conductance more than twice that of the conventional element.

8A to 8C are process cross-sectional views showing the manufacturing method of the first reference example of the present invention.

First, as shown in FIG. 8A, a Si layer 6 ″ containing p-type impurities is formed on the surface of a Si substrate 1 ′ containing n-type impurities.
Are deposited by, for example, a molecular beam epitaxial method. When this Si layer 6 ″ is formed, the normal n-type impurity in the Si substrate 1 ′ is diffused into the epitaxial layer 6 ″ by using a normal epitaxial technique requiring a high temperature treatment of 1100 ° C., for example. Therefore, it is desirable to form it by a low temperature method such as molecular beam epitaxy. For example, the substrate temperature should be kept at 500-600 ℃, and S under vacuum condition of about 10 ^-9 Torr.
When i is grown, it can be grown at a rate of 0.1 to 1 nm / sec.

Next, as shown in FIG.
An oxide film or an insulating film 5'is formed as a gate insulating film on the surface of the layer 6 ". The gate insulating film 5'is also preferably formed at a low temperature in order to suppress the movement of impurities in the Si substrate 1 '. An oxide film can be easily formed even at a low temperature by performing the oxidation in a pressurized atmosphere.Hereinafter, the gate electrode 4 ', the source and drain regions 2', 3 are formed in the same manner as in the embodiment of FIG. ′ (In the present reference example, since it is a p-channel MOSFET, a p-type impurity layer) is formed.

9 (a) to 9 (d) are complementary MOS (C-MO) using the molecular beam epitaxial method performed in the reference example of FIG.
It is process sectional drawing which shows the 2nd reference example which formed S).

First, as shown in Fig. 9 (a), the impurity concentration is 10 ¹⁵ cm ^-3.
An n-type well 22 having a depth of about 3 μm is formed on the p-type Si substrate 21. After that, p-type impurities are selectively introduced by ion implantation for element isolation, and p-type impurity layers 24, 24 ',
24 ″ is formed, and then thick oxide films 23, 23 ′, 23 ″ having a thickness of about 1 μm are formed in the element isolation region.

Next, as shown in FIG. 9B, an n-channel MOSF
In order to control the threshold voltage V _TH of the ET and p-channel MOSFETs, for example, p-type impurity layers (impurity concentration 10 ¹⁶ to 10 ¹⁷ cm ⁻³ ) 25 and 26 are formed by ion implantation. After that, the substrate temperature is kept at about 600 ° C., and the Si layer 27, 2 containing no impurities is formed by the molecular beam epitaxial method.
7'is grown to a thickness of 15 nm on the Si substrate 21 at a rate of about 1 Å / sec.

Next, as shown in FIG. 9 (c), in an oxygen atmosphere, 920
When oxidized at 6 ° C. for 30 minutes, the gate oxide films 28 and 28 ′ having a thickness of about 10 nm are formed on the Si layers 27 and 27 ′, and the thickness of the Si layers 27 and 27 ′ is this oxidation. Is about 10 nm. After that, for example, a polycrystalline Si film having a thickness of 300 nm is selectively formed on the oxide films 28 and 28 'to form gate electrodes 29 and 29'.

Next, as shown in FIG. 9D, an n-channel MOSF
N ⁺ type source and drain regions 30 and 31 are provided in the ET portion 33,
The p-channel MOSFET portion 34 has a p ⁺ type source,
Drain regions 30 'and 31' are formed by ion implantation using the gate electrodes 29 and 29 'as masks, respectively. After that, an interlayer insulating film 32 is deposited, holes for electrode extraction are selectively opened at desired positions of the gate or drain of the interlayer insulating film 32, and interconnects (not shown) are formed by a conductive material such as Al. ) Is provided to form a C-MOS. Also in the C-MOS created in this reference example, the transfer conductance can be improved.

〔The invention's effect〕

As described above, according to the method for manufacturing a semiconductor device of the present invention, a high-performance semiconductor device capable of obtaining a desired threshold voltage, reducing a decrease in carrier mobility, and improving transfer conductance can be obtained. Can be easily realized by applying a conventional manufacturing method without complicating the manufacturing process.

[Brief description of drawings]

FIG. 1 shows n manufactured by the method for manufacturing a semiconductor device of the present invention.
FIG. 3 is a cross-sectional view of the channel MOSFET, FIG. 2 is a diagram showing the relationship between the gate oxide film thickness and the impurity concentration of the Si substrate, and FIG.
FIG. 4 is a diagram showing the relationship between carrier mobility and the total impurity concentration of the Si substrate, FIG. 4 is a sectional view of a p-channel MOSFET manufactured by the method for manufacturing a semiconductor device of the present invention, and FIG. FIGS. 6 (a) to 6 (c) are views for explaining the MOSFET of FIG. 4, and FIGS. 7 (a) and 7 (b) are process cross-sectional views showing an embodiment of the method for manufacturing a semiconductor device of the present invention. 8A to 8C are diagrams showing the results of measuring the current characteristics of the conventional example and the example of FIG. 6, respectively, and FIGS. 8A to 8C show the first example of the present invention.
9A to 9C are process cross-sectional views showing the manufacturing method of the reference example of FIG.
6D is a process sectional view showing the manufacturing method of the C-MOS of the second reference example of the present invention. FIG. 1, 21 ... p-type Si substrate 1 '... n-type Si substrate 2, 3 ... n-type source / drain regions 2', 3 '... p-type source / drain regions 4, 4' ... gate electrode 5 5 ', 29, 29' ... Gate oxide film 6, 6 ', 6 "... Low-concentration impurity layer 7 ... Depletion layer 8 ... P-type impurity layer 9 ... Oxide film 22 ... N-type well 23 , 23 ', 23 "... oxide film for element isolation 24, 24', 24" ... p-type impurity layer 25, 26 ... p-type impurity layer 27, 27 '... Si layer 28, 28' ... oxidation Membranes 30, 31 ... n ⁺ type source / drain regions 30 ′, 31 ′ …… p ⁺ type source / drain regions 32 …… Interlayer insulating film 33 …… n channel MOSFET part 34 …… p channel MOSFET part

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masao Aoki 1-280, Higashi Koigakubo, Kokubunji, Tokyo (72) Central Research Laboratory, Hitachi, Ltd. (72) Hitoshi Kume 1-280, Higashi Koigakubo, Kokubunji, Tokyo Hitachi, Ltd. In the Central Research Laboratory (72) Inventor, Chisato Kadota, No. 1448, Kamimizuhonmachi, Kodaira-shi, Tokyo In-house Hitachi Ultra Engineering Engineering Co., Ltd. (56) Reference JP-A-56-33881 (JP, A) Opened 59-151464 (JP, A)

Claims (1)

[Claims] 1. An oxide film is formed by oxidizing the surface of the semiconductor substrate on a surface region of the semiconductor substrate which becomes a current passage region of a MOS field effect transistor containing a first conductivity type impurity having a predetermined impurity concentration. The oxide film absorbs the impurities to form a current passage region having an impurity concentration lower than that of the surface region in the surface region, the step of removing the oxide film, and the current passage A gate electrode is formed on the region via a gate insulating film, and a source / drain region of a second conductivity type opposite to the first conductivity type is formed in a surface region of the semiconductor substrate on both sides of the gate electrode. A method of manufacturing a semiconductor device, comprising the steps of: