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JPH0638647B2 - Input circuit of synchronization judgment device - Google Patents
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JPH0638647B2 - Input circuit of synchronization judgment device - Google Patents

Input circuit of synchronization judgment device

Info

Publication number
JPH0638647B2
JPH0638647B2 JP62294719A JP29471987A JPH0638647B2 JP H0638647 B2 JPH0638647 B2 JP H0638647B2 JP 62294719 A JP62294719 A JP 62294719A JP 29471987 A JP29471987 A JP 29471987A JP H0638647 B2 JPH0638647 B2 JP H0638647B2
Authority
JP
Japan
Prior art keywords
signal
synchronization
input circuit
circuit
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62294719A
Other languages
Japanese (ja)
Other versions
JPH01136481A (en
Inventor
裕 米田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP62294719A priority Critical patent/JPH0638647B2/en
Publication of JPH01136481A publication Critical patent/JPH01136481A/en
Publication of JPH0638647B2 publication Critical patent/JPH0638647B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Synchronizing For Television (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明はテレビジョン受像機に設けられる同期判定装置
の入力回路に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input circuit of a synchronization determination device provided in a television receiver.

従来の技術 テレビジョン受像機において、オートサーチ選局を行う
場合に選局回路はチューナに加える同調電圧をアップ方
向又はダウン方向へ順次可変していくが、選局ポジショ
ンでその可変を停止させる(従ってオートサーチを停止
させる)ためにはストップ制御信号が必要である。この
ようなステップ制御信号としては一般に受信テレビ信号
の同期信号が使用されるのが普通である。即ち、オート
サーチ動作が2つの放送チャンネルの間にあるときは同
期信号は得られないが、放送チャンネルに至ると同期信
号が得られるからである。この場合、同期判定装置は選
局回路内に設けられるが、一般にその同期判定回路に同
期分離回路の出力である同期信号は入力回路を通して与
えられる。
2. Description of the Related Art In a television receiver, when performing automatic search tuning, a tuning circuit sequentially changes a tuning voltage applied to a tuner in an up direction or a down direction, but the tuning voltage is stopped at a tuning position ( Therefore, a stop control signal is required to stop the automatic search. As such a step control signal, a synchronizing signal of a received television signal is generally used. That is, the synchronization signal cannot be obtained when the automatic search operation is between the two broadcasting channels, but the synchronization signal can be obtained when the broadcasting channel is reached. In this case, the synchronization determination device is provided in the channel selection circuit, but generally, the synchronization determination circuit outputs the synchronization signal output from the synchronization separation circuit to the input circuit.

発明が解決しようとする問題点 ところで、同期分離回路の出力は通常の電界強度では第
3図の受信ビデオ信号(A)から同期信号(B)を正常に出力
するが、弱電界時にはノイズ(N)等の影響により第4図
のように恰も同期信号が沢山あるかの如く出力する場合
がある。この場合、同期判定装置が一定時間当たりの同
期信号パルスをカウントする形式の場合には特に誤判定
が生じることになる。
Problems to be Solved by the Invention By the way, the output of the sync separation circuit normally outputs the sync signal (B) from the received video signal (A) of FIG. 3 under normal electric field strength, but when the electric field is weak, noise (N In some cases, as shown in FIG. 4, due to the influence of), etc., the synchronization signals are output as if there were many synchronization signals. In this case, an erroneous determination occurs especially when the synchronization determination device is of a type in which the synchronization signal pulses are counted per fixed time.

本発明はこのような点に鑑みなされたものであって、弱
電界であっても同期信号を正しく与えることができるよ
うにした同期判定装置の入力回路を提供することを目的
とする。
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an input circuit of a synchronization determination device capable of correctly supplying a synchronization signal even in a weak electric field.

問題点を解決するための手段 上記の目的を達成するため本発明では、受信テレビ信号
の同期信号を判定する同期判定装置の入力回路におい
て、同期分離回路の出力としての同期信号の期間をフラ
イバックパルスの積分出力信号によって狭く限定する手
段を設けた構成としている。
Means for Solving the Problems In order to achieve the above object, in the present invention, in the input circuit of the synchronization determination device for determining the synchronization signal of the received television signal, the period of the synchronization signal as the output of the synchronization separation circuit is flybacked. A configuration is provided in which means for narrowing the limit by the integrated output signal of the pulse is provided.

作用 このような構成によると、ノイズの影響を可及的に減少
できるので、ノイズ自身による擬似同期信号の発生を抑
制できる。
Effect With such a configuration, the influence of noise can be reduced as much as possible, so that it is possible to suppress generation of a pseudo sync signal due to noise itself.

実施例 第1図において、(イ)点には第2図(a)に示すサンド
キャスル(Sand Castle)が波が印加される。このサンド
キャスル波はビデオ・クロマ処理ICから出力されるよ
うになっているものであって、そのICの出力を利用す
る場合には、点線で示す如き回路(1)を付加して(ロ)
点に第2図(b)に示す同期信号を得る。尚、通常の同期
分離回路の出力を利用する場合には直線前記同期信号
(b)が与えられるので、前記回路(1)は不要である。とこ
ろで、前記回路(1)はサンドキャスル波を抵抗(R1)を介
してエミッタフォロワトランジスタ(Q1)のベースに入力
し、その出力をツェナーダイオード(ZD)及び抵抗(R3)に
よって一定レベルでスライスすることによって前記同期
信号(b)を出力するように構成されている。
Example In FIG. 1, a wave is applied to a sand castle shown in FIG. 2 (a) at a point (a). This sandcastle wave is output from the video / chroma processing IC. When using the output of the IC, the circuit (1) shown by the dotted line is added (b).
At that point, the synchronizing signal shown in FIG. 2 (b) is obtained. When using the output of a normal sync separation circuit, the straight line
Since circuit (b) is given, the circuit (1) is unnecessary. By the way, the circuit (1) inputs the sandcastle wave to the base of the emitter follower transistor (Q 1 ) via the resistor (R 1 ), and outputs its output at a constant level by the Zener diode (ZD) and the resistor (R 3 ). The synchronization signal (b) is output by slicing with.

第1図において、(ハ)点にはフライバックパルス(FP)
が印加される。このフライバックパルス(FP)は抵抗(R5)
(R6)(R7)及びトランジスタ(Q2)によって第2図(d)の如
く波形成形され、更に抵抗(R8)とコンデンサ(C1)によっ
て(e)の如く積分され抵抗(R9)を介してトランジスタ
(Q3)のオン/オフを制御する。このため積分波形(e)が
トランジスタ(Q3)のカットオフレベル(E1)以下になった
期間だけ、トランジスタ(Q3)のコレクタ側の同期信号
(b)は有効にされ、それ以外の期間は略アースレベルに
クランプされて無効になる。換言すれば、フライバック
パルスの積分出力信号(e)によって同期信号(b)の期間は
狭く限定されることになる。従って、ノイズ等は殆どカ
ットされる。また、前記限定された有効な期間(T)内の
ノイズは抵抗(R4)とコンデンサ(C2)による積分作用によ
って除くことができる。
In Fig. 1, the flyback pulse (FP) is at point (c).
Is applied. This flyback pulse (FP) is a resistor (R 5 )
Waveform shaping as shown in Fig. 2 (d) by (R 6 ) (R 7 ) and transistor (Q 2 ), and further integrated by resistor (R 8 ) and capacitor (C 1 ) as shown in (e). 9 ) Via transistor
Controls on / off of (Q 3 ). Therefore the integrated waveform (e) only cut-off level (E 1) period is the following transistor (Q 3), the collector side of the synchronizing signal of the transistor (Q 3)
(b) is enabled, and for the rest of the time it is disabled by being clamped to approximately ground level. In other words, the period of the synchronization signal (b) is narrowly limited by the integrated output signal (e) of the flyback pulse. Therefore, most of the noise is cut off. Further, the noise within the limited effective period (T) can be removed by the integral action of the resistor (R 4 ) and the capacitor (C 2 ).

このようにして、本構成ではノイズの多い弱電界時であ
っても、第2図(f)の如くノイズに影響されずに同期信
号を正確な形で同期判定装置に与えることができる。
In this way, in this configuration, even in a weak electric field with a lot of noise, the synchronization signal can be given to the synchronization determination device in an accurate form without being influenced by the noise as shown in FIG. 2 (f).

発明の効果 上述のように本発明によれば、弱電界時のノイズ等の影
響による同期分離出力の不要成分を極めて少なくするこ
とができるので、例えば同期信号の数をカウントして同
期判定を行う同期判定装置の判定を正しく行わせること
が可能となり、その効果は大である。
EFFECTS OF THE INVENTION As described above, according to the present invention, it is possible to extremely reduce the unnecessary components of the sync separation output due to the influence of noise or the like during a weak electric field. It is possible to correctly make the determination by the synchronization determination device, and the effect is great.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明を実施した同期判定装置の入力回路を示
す回路図であり、第2図はその各部の信号波形図であ
る。第3図及び第4図は従来例の説明図である。 (b)……同期信号,(FP)……フライバックパルス, (C1)……積分用コンデンサ,(R1)……積分用抵抗。
FIG. 1 is a circuit diagram showing an input circuit of a synchronization determination device embodying the present invention, and FIG. 2 is a signal waveform diagram of each part thereof. 3 and 4 are explanatory views of a conventional example. (b) …… Synchronization signal, (FP) …… Flyback pulse, (C 1 ) …… Integrating capacitor, (R 1 ) …… Integrating resistor.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】受信テレビジョン信号の同期信号を判定す
る同期信号判定装置の入力回路において、 フライバックパルスを該フライバックパルスよりも幅狭
の矩形波に波形成形する成形手段と、 前記波形成形された矩形波を積分する積分手段と、 前記積分手段により積分された信号が所定レベルを超え
て突出する期間に前記受信テレビジョン信号中の同期信
号を通過させるためのゲート手段と、 を備え、前記同期信号の期間を狭くすることを特徴とす
る同期判定装置の入力回路。
1. An input circuit of a sync signal judging device for judging a sync signal of a received television signal, wherein a shaping means for shaping a flyback pulse into a rectangular wave narrower than the flyback pulse, and the waveform shaping. An integrating means for integrating the rectangular wave, and a gate means for passing a synchronizing signal in the received television signal in a period in which the signal integrated by the integrating means projects beyond a predetermined level, An input circuit of a synchronization determination device, characterized in that the period of the synchronization signal is narrowed.
JP62294719A 1987-11-21 1987-11-21 Input circuit of synchronization judgment device Expired - Lifetime JPH0638647B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62294719A JPH0638647B2 (en) 1987-11-21 1987-11-21 Input circuit of synchronization judgment device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62294719A JPH0638647B2 (en) 1987-11-21 1987-11-21 Input circuit of synchronization judgment device

Publications (2)

Publication Number Publication Date
JPH01136481A JPH01136481A (en) 1989-05-29
JPH0638647B2 true JPH0638647B2 (en) 1994-05-18

Family

ID=17811422

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62294719A Expired - Lifetime JPH0638647B2 (en) 1987-11-21 1987-11-21 Input circuit of synchronization judgment device

Country Status (1)

Country Link
JP (1) JPH0638647B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2600121Y2 (en) * 1992-03-25 1999-10-04 アイワ株式会社 Tuning device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS532012A (en) * 1976-06-29 1978-01-10 Nippon Telegr & Teleph Corp <Ntt> Time sharing light channel network utilizing light phase conversion switch and pertinent light phase conversion switch
JPS6059785B2 (en) * 1978-12-12 1985-12-26 松下電器産業株式会社 television signal detection device

Also Published As

Publication number Publication date
JPH01136481A (en) 1989-05-29

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