JPH063870B2 - Output circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit, and more particularly to an output circuit having a function of preventing a malfunction caused by a simultaneous change of output signals in an integrated circuit or the like.

[Conventional technology]

In general, an integrated circuit needs to output an operation result of internal logic or the like toward the outside of the integrated circuit in order to exert its function. Therefore, at least one output circuit is provided for this purpose. . However, a large number of output circuits are usually used in order to increase the functionality of the integrated circuit itself, and it is required that some of the output circuits operate at the same timing.

Next, a conventional output circuit is shown in FIG.

First, when a signal from the low level to the high level is input to the point A, the output of the inverter 8 shifts from the high level to the low level, the p-channel transistor 9 turns on, the n-channel transistor 10 turns off, and the output result shows the high level. It is transmitted. Also, when a signal from the High level to the Low level is input to the point A, the output of the inverter 8 shifts from the Low level to the High level in reverse to the previous time, and the p-channel transistor 9
Is turned off and the n-channel transistor 10 is turned on, and the output level is transmitted as a low level. H at point A of the latter
FIG. 4 shows the transient response of the drain-source current I _DS of the n-channel transistor 10 when a signal that falls from the igh level to the Low level is input. At the instant when the n-channel transistor 10 is turned on, I _DS has a value corresponding to the saturation current of the transistor because the electric charge stored in the output load capacitance 11 is discharged. In particular, when a plurality of signals change at the same time, the total current of I _DS flows in the power supply line of the integrated circuit. As a result, the power supply level (GND level) of the entire integrated circuit rises, causing malfunction in the internal circuit and the input circuit. As a measure against this, conventionally, the number of output signals that change simultaneously is reduced.

Reduce the output load capacitance C _L.

A delay circuit is added before the output circuit, and the peak value of I _DS is shifted in the output circuit where the signal changes at the same time.

Was doing things. FIG. 5 shows an example of the above measures. Outputs of 6- ^bit D-type flip-flop 12 Q0 to Q5
_May change at the same time depending on the CLOCK signal, but by adding the delay circuit 13 to the outputs of Q0 to Q2, the output terminals OUT ₀ to OUT ₂ become slower than OUT ₃ to OUT ₅ , and I _DS The peak value of is shifted.

[Problems to be solved by the invention]

In the above-mentioned conventional measures, it is almost impossible to reduce the number of simultaneously changing output signals, because the configuration of the system using the integrated circuit must be changed. Further, in order to reduce the output load capacity, a new drive circuit needs to be provided outside the integrated circuit, so that the system cannot be downsized and the cost increases. Furthermore, the method of adding a delay gate has a drawback that the delay time increases and varies up to the output, which makes it difficult to cope with high-speed equipment.

SUMMARY OF THE INVENTION An object of the present invention is to provide an output circuit which can solve the above-mentioned drawbacks, is easy to downsize the system, is low in cost, has a short delay time, and can obtain an output signal without variation.

[Means for solving problems]

The output circuit of the present invention is an output circuit including an inverter in which transistors having different conductivity types are connected in series between a power supply and a ground power supply, and a common input signal is supplied to the gate of the transistor, and the transistors forming the inverter are included in the output circuit. Of the first conductivity type first transistor provided between the output terminal and the ground power source, a second transistor is provided in parallel to receive the input signal and the delayed inverted signal of the output signal of the inverter. A delay control means for applying an output to the gate of the second transistor, the input signal changes in the power supply level direction, and the output signal of the inverter is directed from the power supply level to the ground power supply level. And a means for making the second transistor conductive after a predetermined time has elapsed after the change.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. In FIG. 1, 1 is an input stage inverter of an output circuit, 2 is an output signal feedback circuit side inverter, 3 is an AND circuit, 4,5 are n-channel transistors, 6 is a p-channel transistor, and 7
The load outside the integrated circuit will be described with reference to FIG.

Fig. 1 When a signal falling from High level to Low level arrives at point A, point B rises through the inverter of 1, the transistor of 5 turns on first, the transistor of 6 turns off and the load capacitance of 7 is charged. The _generated current becomes I _DS and flows into the transistor of 5, and I _{DS at} this time is 5
Limited to the saturation current of the transistor. This is point a in FIG. Next, this voltage is fed back to the inverter of 2 and passes through the AND circuit of 3 to turn on the new transistor of 4. The limit of I _DS at this time is the saturation current value of the transistors of 4 and 5 (the actual I _DS is considerably smaller than the control value because the discharge of the load capacitance of 7 has already started). That is, by limiting the peak value of I _DS immediately after the signal falls, the rise of the power supply level of the integrated circuit is eliminated, and the malfunction caused by the simultaneous change of a plurality of output signals can be prevented.

〔The invention's effect〕

As described above, the present invention reduces the peak value of the output current when the output signal changes by using the output current control circuit for feedback of the external output signal. It is not necessary to add a delay gate inside the integrated circuit to prevent fluctuations in the power supply level, the input signal to the integrated circuit, or malfunction of the internal circuit, or to provide a drive circuit outside the integrated circuit to reduce the output load capacitance. There is an effect that the integrated circuit itself can avoid it without worrying about delay of delay time, variation, and high cost.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a comparison of transient response characteristics of I _DS of n-channel transistors in FIGS. 1 and 3, FIG. 3 is a conventional circuit diagram, and FIG. The figure is n in FIG.
The transient response characteristic of the I _DS of the channel transistor is shown in FIG. 1,2,8 …… Inverter circuit, 3 …… AND circuit, 4,5,10
…… n-channel transistor, 6,9 …… channel transistor, 7,11 …… output load capacity, 12 …… 6 ^bit D-type
Flip-flop, 13 ... Delay circuit, 14 ... Output circuit (conventional type) 15 ... Output terminal.

Claims (1)

[Claims] 1. An output circuit including an inverter in which transistors having different conductivity types are connected in series between a power supply and a ground power supply, and a common input signal is supplied to the gate of the transistor, among the transistors forming the inverter. A second transistor of one conductivity type is provided in parallel with respect to the first transistor of one conductivity type provided between the output terminal and the ground power supply, and a delayed inverted signal of the input signal and the output signal of the inverter is provided. In response to this, there is provided delay control means for applying an output to the gate of the second transistor, the input signal changes in the power supply level direction, and the output signal of the inverter changes from the power supply level to the ground power supply level. The output circuit is characterized in that the second transistor is made conductive after a lapse of a predetermined time from the change toward the second transistor.