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JPH063872B2 - Semiconductor - Google Patents
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JPH063872B2 - Semiconductor - Google Patents

Semiconductor

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Publication number
JPH063872B2
JPH063872B2 JP62088169A JP8816987A JPH063872B2 JP H063872 B2 JPH063872 B2 JP H063872B2 JP 62088169 A JP62088169 A JP 62088169A JP 8816987 A JP8816987 A JP 8816987A JP H063872 B2 JPH063872 B2 JP H063872B2
Authority
JP
Japan
Prior art keywords
voltage
circuit
capacitor
load
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62088169A
Other languages
Japanese (ja)
Other versions
JPS63253719A (en
Inventor
幸夫 岡
研一 荒井
滋夫 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP62088169A priority Critical patent/JPH063872B2/en
Publication of JPS63253719A publication Critical patent/JPS63253719A/en
Publication of JPH063872B2 publication Critical patent/JPH063872B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Electronic Switches (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、両方向通電形の半導体しゃ断器に関する。The present invention relates to a bidirectional energization type semiconductor breaker.

〔従来の技術〕[Conventional technology]

両方向通電形の半導体しゃ断器として、第4図に示すよ
うなものがある。
A bidirectional energizing type semiconductor breaker is shown in FIG.

図中11は直流電源、13は負荷で、その間に順方向通電ゲ
ートターンオフサイリスタ(以下GTOサイリスタと称
す)2と逆方向通電GTOサイリスタ3とを並列接続
し、これらGTOサイリスタ2,3に対しダイオード
5,6,7,8とコンデンサ4によるブリッジ整流形ス
ナバ回路14を並列接続し、かつ電圧依存性非線形抵抗
器、例えばZnOアレスタ9を並列接続している。
In the figure, 11 is a DC power supply, 13 is a load, and a forward conduction gate turn-off thyristor (hereinafter referred to as GTO thyristor) 2 and a reverse conduction GTO thyristor 3 are connected in parallel between them, and a diode is connected to these GTO thyristors 2 and 3. 5, 6, 7 and 8 and a bridge rectification type snubber circuit 14 composed of a capacitor 4 are connected in parallel, and a voltage dependent non-linear resistor such as a ZnO arrester 9 is connected in parallel.

前記ブリッジ整流形スナバ回路14のコンデンサ4には、
放電用抵抗10,11とその中間に挿入した放電用のGTO
サイリスタ12からなる直列回路が接続される。
In the capacitor 4 of the bridge rectification type snubber circuit 14,
Discharge resistors 10 and 11 and a GTO for discharge inserted between them
A series circuit composed of thyristors 12 is connected.

第5図は前記両方向通電形の半導体しゃ断器の動作波形
図で、(イ)はオン信号、(ロ)はオフ信号、(ハ)は
負荷電流、(ニ)は主端子a−a間電圧、Eは直流
電源1の電圧、ErはZnOアレスタ9の制限電圧を示
す。
FIG. 5 is an operation waveform diagram of the bidirectional energization type semiconductor circuit breaker. (A) is an on signal, (b) is an off signal, (c) is a load current, and (d) is a main terminal a 1 -a 2. Voltage, E is the voltage of the DC power supply 1, and Er is the limiting voltage of the ZnO arrester 9.

(ロ)に示すように時刻tでは両GTOサイリスタ
2,3のゲートにはオフ信号が印加されており、両GT
Oサイリスタ2,3はオフ状態を維持している。
As shown in (b), an off signal is applied to the gates of both GTO thyristors 2 and 3 at time t 0 , and both GTs
The O thyristors 2 and 3 remain off.

時刻tになるとオフ信号が除かれ、オン信号が両GT
Oサイリスタ2,3のゲートに与えられ、放電用GTO
サイリスタ12のゲートにも同時に与えられる。これによ
り、主端子a−a間電圧の極性にあったGTOサイ
リスタ2がオンし(第5図(イ)、(ロ)、(ハ)、
(ニ)参照)、負荷電流が零から増加する(第5図
(ハ)参照)。
At time t 1 , the off signal is removed and the on signal is transmitted to both GTs.
GTO for discharge given to the gates of O-thyristors 2 and 3
It is also given to the gate of the thyristor 12 at the same time. As a result, the GTO thyristor 2 having the polarity of the voltage between the main terminals a 1 and a 2 is turned on (FIG. 5 (a), (b), (c),
(See (d)), and the load current increases from zero (see FIG. 5 (c)).

時刻tになるとオン信号が除かれ、オフ信号が両GT
Oサイリスタ2,3のゲートに与えられ(GTOサイリ
スタ12のゲートにも同時に与えられる)、GTOサイリ
スタ2がオフする。負荷電流はターイオード5,6を通
してコンデンサ4に流れ込むため、主端子間電圧が上昇
する。やがて主端子間電圧はアレスタ9の制限電圧Er
に達し、負荷電流はZnOアレスタ9に転流する(第5
図(ニ)参照)。
At time t 2 , the ON signal is removed and the OFF signal is output to both GTs.
It is applied to the gates of the O thyristors 2 and 3 (also applied to the gate of the GTO thyristor 12), and the GTO thyristor 2 is turned off. Since the load current flows into the capacitor 4 through the diodes 5 and 6, the voltage between the main terminals rises. Eventually, the voltage between the main terminals becomes the limit voltage Er of the arrester 9.
And the load current commutates to the ZnO arrester 9 (5th
(See Figure (d)).

時刻tになると負荷のエネルギはZnOアレスタ9で
消費され、負荷電流は零に減衰する。コンデンサ4はダ
イオード5,6がオフするため主端子a,aから切
離され、主端子間電圧は直流電源電圧に落ち着こうとす
る。しかしZnOアレスタ9の寄生容量は大きく、負荷
電流が零になると負荷13のインダクタンス13aとZnO
アレスタ9の寄生容量15の間でLCの共振振動が起こ
る。やがて時刻tになると主端子間電圧の回路の抵抗
分により直流電源電圧Eに減衰する。以上で両方向通電
形しゃ断器の動作は完了する。
At time t 3 , the load energy is consumed by the ZnO arrester 9, and the load current is attenuated to zero. The capacitors 4 are disconnected from the main terminals a 1 and a 2 because the diodes 5 and 6 are turned off, and the voltage between the main terminals tends to settle down to the DC power supply voltage. However, the parasitic capacitance of the ZnO arrester 9 is large, and when the load current becomes zero, the inductance 13a of the load 13 and ZnO
Resonant vibration of LC occurs between the parasitic capacitances 15 of the arrester 9. Eventually, at time t 4 , the DC power supply voltage E is attenuated by the resistance component of the circuit of the voltage between the main terminals. This completes the operation of the bidirectional energizing circuit breaker.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

このように前記第4図に示した従来回路では、負荷電流
が零になると負荷のインダクタンス13とZnOアレスタ
の寄生容量15の間でLCの共振振動が起こり系が不安定
になるという問題がある。一般的に、ZnOアレスタ9
の制限電圧Erと直流電源電圧Eの差は大きくその振動
の振幅は大きいものとなる。さらに、回路の抵抗分が小
さいとその減衰時間も非常に大きなものとなる。
As described above, in the conventional circuit shown in FIG. 4, when the load current becomes zero, LC resonance vibration occurs between the load inductance 13 and the ZnO arrester parasitic capacitance 15 and the system becomes unstable. . In general, ZnO arrester 9
The difference between the limiting voltage Er and the DC power supply voltage E is large, and the amplitude of the vibration is large. Furthermore, if the resistance of the circuit is small, the decay time will be very long.

本発明の目的は前記従来例の不都合を解消し、負荷電流
(事故電流)しゃ断時に発生するZnOアレスタの寄生
容量と負荷のインダクタンスとの間の寄生振動を速やか
に減衰させ系の安定を保つことができる半導体しゃ断器
を提供することにある。
An object of the present invention is to eliminate the disadvantages of the above-mentioned conventional example, to promptly damp parasitic oscillation between the parasitic capacitance of the ZnO arrester and the inductance of the load, which occurs when the load current (fault current) is cut off, and to maintain the stability of the system. It is to provide a semiconductor breaker capable of

〔問題点を解決するための手段〕[Means for solving problems]

本発明は前記目的を達成するため、逆並列に組合せた1
組のゲートターンオフサイリスタに、ダイオードとコン
デンサなどからなるブリッジ整流形スナバ回路及びZn
Oアレスタのごとき電圧依存性非線形抵抗素子を並列接
続した両方向通電形の半導体しゃ断器において、前記半
導体しゃ断器のしゃ断時に、前記電圧依存性非線形抵抗
素子の寄生容量と負荷のインダクタンス間で起こる共振
振動を減衰させる抵抗とコンデンサの直列回路を前記電
圧依存性非線形抵抗素子に並列接続したことを要旨とす
るものである。
In order to achieve the above-mentioned object, the present invention combines antiparallel 1
A pair of gate turn-off thyristors, a bridge rectification type snubber circuit including a diode and a capacitor, and a Zn
In a bidirectional energization type semiconductor circuit breaker in which voltage-dependent nonlinear resistance elements such as O arresters are connected in parallel, resonance vibration occurs between the parasitic capacitance of the voltage-dependent nonlinear resistance element and the inductance of the load when the semiconductor circuit breaker is cut off. The gist is that a series circuit of a resistor and a capacitor for attenuating is connected in parallel to the voltage-dependent nonlinear resistance element.

〔作用〕[Action]

本発明によれば、ZnOアレスタに並列に接続された抵
抗とコンデンサは負荷のインダクタンスとともにRLC
の振動減衰回路を構成する。この振動減衰回路により負
荷電流しゃ断時にZnOアレスタの寄生容量と負荷イン
ダクタンスの間で起こる寄生振動を防止し、系の安定を
保つことを可能にする。
According to the present invention, the resistor and the capacitor connected in parallel to the ZnO arrester together with the inductance of the load cause the RLC
Vibration damping circuit. This vibration damping circuit prevents parasitic vibration that occurs between the parasitic capacitance of the ZnO arrester and the load inductance when the load current is cut off, and makes it possible to maintain the stability of the system.

〔実施例〕〔Example〕

以下、図面について本発明の実施例を詳細に説明する。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

第1図は本発明の半導体しゃ断器の1実施例を示す回路
図、第2図はこの第1図回路の動作波形図で、前記従来
例を示す第4図、第5図と同一構成要素には同一参照符
号を付したものである。
FIG. 1 is a circuit diagram showing one embodiment of the semiconductor breaker of the present invention, and FIG. 2 is an operation waveform diagram of the circuit shown in FIG. 1, which has the same components as those shown in FIGS. Are denoted by the same reference numerals.

すなわち、直流電流1と負荷13間の順方向GTOサイリ
スタ2と逆方向サイリスタ3の並列回路に対し、ダイオ
ード5,6,7,8とコンデンサ4によるブリッジ整流
形スナバ回路14と非線形抵抗器ZnOアレスタ9とが各
々並列接続され、ブリッジ整流形スナバ回路14のコンデ
ンサ4には放電用抵抗10,11及び放電用のサイリスタ12
が接続される点は前記従来例と同じである。
That is, for the parallel circuit of the forward direction GTO thyristor 2 and the reverse direction thyristor 3 between the direct current 1 and the load 13, the bridge rectification type snubber circuit 14 and the nonlinear resistor ZnO arrester by the diodes 5, 6, 7, 8 and the capacitor 4 are provided. 9 and 9 are connected in parallel, and the capacitors 4 of the bridge rectification type snubber circuit 14 have discharging resistors 10 and 11 and a discharging thyristor 12 respectively.
Is the same as that of the conventional example.

本発明はこのような回路にさらに、抵抗16とコンデンサ
17の直列接続回路を、ZnOアレスタ9に並列に接続し
た。
The present invention further includes a resistor 16 and a capacitor in such a circuit.
Seventeen series connection circuits were connected in parallel to the ZnO arrester 9.

主な動作は前記第5図で示した従来例と同じなので説明
は省略するが、抵抗16、コンデンサ17の値R,Cを適当
に選ぶことにより第2図に示すように時刻tにおいて
(負荷電流が零に減衰する時点)主端子a−a間電
圧を振動なく電源電圧Eに減衰させることができる。
The main operation is omitted the description the same as the prior art shown in the fifth figure, resistor 16, the value R of the capacitor 17, at time t 3 as shown in FIG. 2 by appropriately selecting the C ( When the load current attenuates to zero) The voltage between the main terminals a 1 and a 2 can be attenuated to the power supply voltage E without vibration.

ちなみに、前記R,Cの選定は下記のごとくに行なう。Incidentally, the selection of R and C is performed as follows.

第1図の回路は基本的には、第3図に示す等価回路で表
され、この回路の特性方程式は3次式SLCCR+
L(C+C)+SCR+1=0…(1)となる。
The circuit of FIG. 1 is basically represented by the equivalent circuit shown in FIG. 3, and the characteristic equation of this circuit is a cubic equation S 3 LCC 0 R +
S 2 L (C + C 0 ) + SCR + 1 = 0 (1)

したがって式(1)が3実根を持つようにC,Rの定数
を選べば、第1図の回路において振動なく主端子間電圧
を減衰させることができる。
Therefore, if the constants of C and R are selected so that the equation (1) has three real roots, the voltage between the main terminals can be attenuated without vibration in the circuit of FIG.

〔発明の効果〕〔The invention's effect〕

以上述べたように本発明の半導体しゃ断器は、逆並列に
組合せた1組のGTOサイリスタに、ブリッジ整流形ス
ナバ回路及び非線形抵抗素子ZnOアレスタを並列接続
した両方向通電形の半導体しゃ断器において、負荷電流
しゃ断時に、ZnOアレスタの寄生容量と負荷インダク
タンスの間で起こる共振振動を抑制し、系を外乱なく安
定に保つことができるものである。
As described above, the semiconductor circuit breaker of the present invention is a bidirectional energization type semiconductor circuit breaker in which a bridge rectification type snubber circuit and a nonlinear resistance element ZnO arrester are connected in parallel to one set of GTO thyristors combined in antiparallel. When the current is cut off, resonance oscillation that occurs between the parasitic capacitance of the ZnO arrester and the load inductance can be suppressed, and the system can be kept stable without disturbance.

特に、前記共振振動を減衰するコンデンサと抵抗の直列
回路のうち、コンデンサには抵抗Rの直流的な電力容量
を小さくする効果もある。
In particular, in the series circuit of the capacitor and the resistor that attenuates the resonance vibration, the capacitor also has an effect of reducing the DC power capacity of the resistor R.

また、GTOサイリスタターンオフ後の素子がまだ動的
な状態においてアノード、カソード間電圧の振動を抑制
でき、その結果素子責務を低減でき、素子の信頼性を向
上できるものである。
Further, the oscillation of the voltage between the anode and the cathode can be suppressed while the element after the GTO thyristor turn-off is still dynamic, and as a result, the element duty can be reduced and the element reliability can be improved.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の半導体しゃ断器の1実施例を示す回路
図、第2図は第1図回路の動作波形図、第3図は第1図
回路の基本等価回路図、第4図は従来例を示す回路図、
第5図は同上動作波形図である。 1…直流電源 2…順方向GTOサイリスタ 3…逆方向GTOサイリスタ 4…コンデンサ 5,6,7,8…タイオード 9…ZnOアレスタ、10,11…抵抗 12…放電用GTOサイリスタ 13…負荷、13a…インダクタンス 14…ブリッジ整流形スナバ回路 15…ZnOアレスタの寄生容量 16…抵抗、17…コンデンサ (イ)…オン信号、(ロ)オフ信号 (ハ)…負荷電流 (ニ)…主端子a−a間電圧
FIG. 1 is a circuit diagram showing an embodiment of the semiconductor breaker of the present invention, FIG. 2 is an operation waveform diagram of the circuit of FIG. 1, FIG. 3 is a basic equivalent circuit diagram of the circuit of FIG. 1, and FIG. Circuit diagram showing a conventional example,
FIG. 5 is an operation waveform diagram of the same as above. 1 ... DC power supply 2 ... Forward GTO thyristor 3 ... Reverse GTO thyristor 4 ... Capacitor 5, 6, 7, 8 ... Tioode 9 ... ZnO arrester, 10, 11 ... Resistor 12 ... Discharge GTO thyristor 13 ... Load, 13a ... Inductance 14… Bridge rectification snubber circuit 15… ZnO arrester parasitic capacitance 16… Resistance, 17… Capacitor (a)… On signal, (b) Off signal (c)… Load current (d)… Main terminal a 1 -a Voltage between two

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】逆並列に組合せた1組のゲートターンオフ
サイリスタに、ダイオードとコンデンサなどからなるブ
リッジ整流形スナバ回路及びZnOアレスタのごとき電
圧依存性非線形抵抗素子を並列接続した両方向通電形の
半導体しゃ断器において、前記半導体しゃ断器のしゃ断
時に、前記電圧依存性非線形抵抗素子の寄生容量と負荷
のインダクタンス間で起こる共振振動を減衰させる抵抗
とコンデンサの直列回路を、前記電圧依存性非線形抵抗
素子に並列接続したことを特徴とする半導体しゃ断器。
1. A bidirectional energization type semiconductor cutoff in which a pair of gate turn-off thyristors combined in antiparallel are connected in parallel with a bridge rectification type snubber circuit composed of a diode and a capacitor and a voltage dependent nonlinear resistance element such as a ZnO arrester. In the switching device, a series circuit of a resistor and a capacitor for damping resonance oscillation occurring between the parasitic capacitance of the voltage-dependent nonlinear resistance element and the inductance of the load when the semiconductor breaker is cut off is connected in parallel to the voltage-dependent nonlinear resistance element. A semiconductor breaker characterized by being connected.
JP62088169A 1987-04-09 1987-04-09 Semiconductor Expired - Lifetime JPH063872B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62088169A JPH063872B2 (en) 1987-04-09 1987-04-09 Semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62088169A JPH063872B2 (en) 1987-04-09 1987-04-09 Semiconductor

Publications (2)

Publication Number Publication Date
JPS63253719A JPS63253719A (en) 1988-10-20
JPH063872B2 true JPH063872B2 (en) 1994-01-12

Family

ID=13935415

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62088169A Expired - Lifetime JPH063872B2 (en) 1987-04-09 1987-04-09 Semiconductor

Country Status (1)

Country Link
JP (1) JPH063872B2 (en)

Also Published As

Publication number Publication date
JPS63253719A (en) 1988-10-20

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