JPH063910B2 - Data transmission system between a plurality of devices - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION A plurality of devices are connected by a transmission / reception transmission line, and a synchronization signal is given at a constant cycle. Each device creates a plurality of time slots within the above-mentioned fixed period on the basis of this synchronization signal. One of these time slots
One is for synchronizing signals, the other is for transmitting and receiving control signals, and the remaining time slots are for transmitting and receiving data signals assigned to each device. In the control signal transmission / reception time slot,
Connections between any devices are attempted. The connected device is
Data signals are mutually transmitted and received in the time slot for data signal transmission and reception.

Table of Contents (1) Background of the Invention (1.1) Technical Field (1.2) Prior Art (2) Outline of the Invention (2.1) Purpose of the Invention (2.2) Structure and Effect of the Invention (3) Description of the Embodiment (3.1) Overall System Overview of configuration and operation (3.2) Device configuration (3.3) Synchronization establishment processing (initial processing) (3.4) Message format (3.5) Connection and communication processing (3.6) Collision detection (1) Background of the invention (1.1) Technical field The present invention relates to a data transmission system between a plurality of devices, and more particularly, to a system for exchanging digital data including voice data between a plurality of terminals in a private branch exchange system or other local networks. Regarding

(1.2) Prior Art Star type network systems, loop type network systems, etc. are typically used as data transmission systems between a plurality of devices.

However, these conventional systems all require a main controller for connection and communication, and a plurality of terminals connected to the main controller perform mutual data transmission via the main controller. . Even if the number of terminals is extremely small, it is inevitable to install the main control unit, which causes a problem of increasing capital investment cost.

Further, in these conventional systems, since it is necessary to provide the main control device with interfaces for communication as many as the number of terminals, it is unavoidable that the configuration of the main control device becomes complicated and expensive in this respect as well. .

Further, in the star type system, since all terminals are connected to the main controller by a separate transmission line, the total transmission line length becomes extremely long. Even in a loop system, a transmission line and a reception line are necessary.

(2) Outline of the Invention (2.1) Object of the Invention The present invention provides a data transmission system between a plurality of devices that does not require a conventional main control device and can shorten the total transmission line length. The purpose is to do.

(2.2) Configuration and effect of the invention A data transmission system between a plurality of devices according to the present invention transmits a synchronization signal at a fixed cycle to a plurality of devices which are connected by a transmission / reception transmission line and are pre-identified. And means for doing so. Then, each device, within the above-mentioned fixed period, based on the synchronization signal,
Means are provided for creating a plurality of time slots divided by at least two more than the number of devices. The time length of each time slot is 2 times the maximum propagation delay time between devices for the duration from the beginning to the end of the signal to be communicated.
It is the length including doubled time. Further, one of these time slots is for a synchronization signal for synchronizing the communication signal between the transmitting device and the receiving device, and the other one is a connection request signal transmitted from the device requesting the start of data communication or A connection completion signal transmitted from a device requested to start data communication, a release request signal transmitted from a device requesting termination of data communication, or a release completion signal transmitted from a device requested to terminate data communication, and data. The control signal including the identification code of the device requesting the start or end of communication and the identification code of the device requesting the start or end of the data communication are transmitted and received, and the remaining time slots are used for data transmission. Further, each device is a device that transmits a synchronization signal, a first gate that is opened in synchronization with a synchronization signal time slot, and is closed after the time of this time slot has elapsed, a device that receives the synchronization signal. In the second gate, which is opened in synchronization with the synchronization signal time slot and is closed after the elapse of the time of this time slot, when transmitting the control signal, it is synchronized with the control signal transmission / reception time slot. The third gate which is opened and closed after the elapse of the time of this time slot, is opened in synchronization with the control signal transmission / reception time slot when the control signal is received, and the time of this time slot 4th gate that is closed after the elapse of time, when data is transmitted, the data previously assigned for data transmission for each identification code of the device Fifth gate that is opened in synchronization with the trust time slot and closed after the time of this time slot has elapsed, when the other device to communicate with has been determined by sending and receiving a control signal, and when data is to be received. In addition, a sixth gate opened in synchronization with a time slot for data transmission assigned to the partner apparatus and closed after the time of this time slot has passed, and a third gate when requesting the start of data communication. After opening the gate and transmitting the control signal to the transmission line, opening the fourth gate at the above-mentioned constant period to take in the control signal from the transmission line, and by transmitting and receiving the control signal, the device to be communicated is determined, and then the fifth signal is transmitted. Open the gate,
Send the data to be transmitted to the transmission line or open the sixth gate to take in the data from the transmission line, and when requesting the end of data communication, open the third gate to send the control signal to the transmission line. It is provided with means for transmitting, transmitting the control signal from the transmission line by opening the fourth gate at the above-mentioned constant period, and ending the communication by transmitting and receiving the control signal.

Preferably, the device for transmitting the synchronization signal is included in one device. In this case, the time slot creating means of one device creates a time slot on the basis of the synchronization signal to be transmitted. The time slot creating means of the other device receives the sync signal transmitted from the one device, and creates a time slot on the basis of the received sync signal.

The device requesting the start of data communication (communication requesting device) is
When the third gate is opened, the control signal including the connection request signal, the identification code of the own device, and the identification code of the device of the communication partner is sent to the transmission line.

Another device takes in a connection request signal and a control signal including these identification codes from the transmission line when the fourth gate is opened. If the identification code of the communication partner device included in the control signal is one of these other devices, it means that the other device is a device (communication requested device) for which communication is requested. Therefore, a reply is sent to the communication request side device.

When the communication requesting device is in the communicable state, this device transmits the control signal including the connection completion signal to the communication requesting device when the third gate is opened. If the communication-requested device is in a state in which it cannot communicate because it is already communicating with another device, it transmits a control signal including a busy signal.

The communication requesting device, when the fourth gate is open,
Control signal The control signal of the time slot for transmitting and receiving is taken in. If this signal includes a connection completion signal, then the data is transmitted using the time slot for data transmission previously assigned to the own device. Also, the communication request side device receives data from the data transmission time slot assigned to the communication request side device. Communication is performed in this way.

When ending communication, one of the device requesting communication or the device requesting communication transmits a control signal including a release request signal, and the other device receiving this signal completes releasing the control signal. Transmit including signals. In this way, the communication ends.

According to the present invention, since the plurality of devices are connected by the transmission / reception transmission line, the total transmission line length is extremely short compared to the conventional star system, and is half that of the loop system. Become.

Further, the present invention does not require a main control device having a replacement or connection function as in the prior art, and it suffices to simply provide a means for generating a synchronization signal of a constant cycle. The synchronization signal generating means can also be incorporated in at least one device.

Since each device has its own connection function, it is possible to construct a system without providing a main control device if there are at least three devices, and the number of devices to be connected will be increased sequentially as necessary. You can also

Further, according to the present invention, since the devices can communicate with each other in each cycle in which the synchronization signal is generated, real-time data transmission / reception is ensured, and communication between arbitrary devices is possible.

(3) Description of Embodiments (3.1) Outline of Overall System Configuration and Operation FIG. 1 schematically shows the overall configuration of a data transmission system according to the present invention.

In FIG. 1 (A), n devices are mutually connected by a two-wire multi-drop method. Two transmission lines that connect n devices are used for both transmission and reception. These devices are, for example, telephones and other terminals controlled by a computer, and for the sake of convenience, 1, 2, ..., I,
..., k, ..., n are numbered.

Each of the n units has a line interface (I /
F) and communicate with each other via this line I / F. All the line I / Fs except that the line I / F of the device 1 has a function of transmitting the synchronization signal S.
Have exactly the same configuration.

The generation of the synchronization signal S by the device 1 does not mean that the device 1 has the initiative in communication. Only this synchronization signal generating function is completely separated from the device 1, and the first
The synchronization signal generator 10 may be connected to a line as shown in FIG. By doing so, the n devices have exactly the same function with respect to mutual communication, and can be regarded as completely equal in the communication system.

In the following description, for convenience, it is assumed that the device 1 has a function of generating the synchronization signal S.

FIG. 2 shows the timing relationship of the entire system. The device 1 sends the synchronization signal S on the line at intervals of a fixed time T and divides the cycle T into (n + 2) pieces, so that the continuous (n + 2) pieces having the same time length are included in the cycle T. Time slot TS _x (where x is s, c,
1, 2, ..., I, ... K, ..., N). Other device 2
~ N receives the synchronization signal S transmitted from the device 1, and based on the received synchronization signal S, in each of the devices similarly, consecutive (n + 2) times of the same time length
Create slot TS _x . As will be described later, the synchronization signal S
Has a specific bit pattern, each device 2
~ N can detect this signal S. A series of time slots TS _x in each of the devices 2 to n are phase-delayed by the propagation time of the signal with reference to that in the device 1.

The first time slot TS _s is for establishing synchronization between n devices (synchronization channel), and the above-mentioned synchronization signal S
Are transmitted and received in this time slot TS _s .

The second time slot TS _c is for connecting or disconnecting at least two of the n devices to each other (control channel). This time
In slot TS _c , for example, one device addresses another one to issue a connection request, and in the subsequent time slot of period T, the corresponding other device connects to the corresponding device. If the reply is complete, the two devices are connected to each other and are ready for communication. The same operation is performed when disconnecting the two connected devices, but the details will be described later. The signal transmitted / received in this time slot TS _c is the control signal D _c.
Called.

The other time slots TS _{1 to} TS _n are used for sending and receiving data (data channels). The time slot TS _i is a time slot in which the device _i transmits data. At this time, the device connected to the device i receives the transmitted data. For example, when device i and device k are connected and communicate with each other, time slot T
At S _i , device i sends out a data signal D _i and device k
Receives it, device k sends out a data signal D _k in time slot TS _k , and device i receives it.
As a result, full-duplex communication of data and bidirectional simultaneous voice communication are realized.

Each signal _{S, D c, D 1,} ~D n respectively the same number of bits, and for example, in 10 bits, as described later.
Let τ _{b be} the time length of these signals.

As described above, the phases of the time slots in each of the devices 1 to n are offset from each other by the propagation time. Further, the signals sent from the respective devices 1 to n are on the same line. A guard time τ _g is provided in each time slot so that the signals emitted from each device 1-n do not overlap each other on the transmission line due to the delay due to the propagation time. The propagation time in the two devices with the longest transmission distance is set as the maximum propagation delay time τ _d . Different time
The condition for preventing signals transmitted from different devices from overlapping each other during the slot is given by the following equation, where the time length of the time slot is [TS _x ] °.

[TS _x ] = τ _b + τ _g > 2 · τ _d + τ _b (1) From this, 2 · τ _d <τ _g (2). It can be seen that the guard time τ _g having a time length that satisfies the condition of the expression (2) should be provided.

FIG. 3 shows the transmission / reception timing of signals between two devices and the bit configuration of each signal. Here, the manner in which the data signal D _i is transmitted from the device i to the device k is illustrated in an enlarged manner. In the transmission-side apparatus i, the time slot in synchronization with the TS _i (in synchronization with the start of the time slot TS _i) the data signal D _i is transmitted. However, since the propagation delay time changes depending on the distance between the communicating devices, at the receiving device k, the signal D _i arrives within the time slot TS _i , but the phase of the reception timing is the time slot TS _i . changes within _i ,
That is, it is asynchronous. Therefore, as can deal with when reception timing is asynchronous, the start bit ST before the bit sequence d ₁ to d ₈ of the signal D _i, asynchronous method which stop bit SP were respectively added later is adopted ing. Therefore, if the data bits consist of 8 bits, the signal D _i will be 10 bits.

Other signals other than the data signal, that is, a bit configuration of the asynchronous method equally well synchronization signals S and control signal D _c.

FIG. 4 shows an example of the structure of the synchronization signal S. All the data bits d _{1 to} d ₈ are 1, and a start bit ST and a stop bit SP are provided before and after this bit string.
There is. Thus, the sync signal S has a specific bit pattern.

(3.2) Device Configuration FIG. 5 shows an example of the configuration of the devices 1 to n described above. Since all the devices have exactly the same hardware configuration, FIG. 5 shows only one device. This device is suitable for sending and receiving digital data.

Processing such as time slot generation, connection control, transmission data generation, reception data decoding, and communication with a host CPU is performed by the CPU 20, preferably a microprocessor. The CPU 20 includes a ROM 21 storing the program, a RAM 22 for storing data necessary for control such as the device number, data to be transmitted, and received data, a time slot gate signal generation circuit 23,
Interface 26 with upper CPU, sending control signal D _c ,
The reception buffers 34 and 33 and the transmission / reception buffers 36 and 35 for transmitting the data signal D _i are connected via various buses.

The time slot gate signal generation circuit 23 includes the CPU 20
Under the control of 1), the gate control signals G1 to G6 are generated at the timing described later.

The synchronization signal detection circuit 31 detects the above-mentioned specific bit pattern (FIG. 4), and for example, 8 bits
It includes an AND circuit which receives the data d _{1 to} d ₈ . The sync signal generating circuit 32 generates the sync signal S having the same specific bit pattern as described above.

The synchronization signal generation circuit 32, the control signal transmission buffer 34, and the data transmission buffer 36 are provided with gates 2, 4 and 6, respectively.
Is connected to the parallel-to-serial conversion circuit 24 via the bus, and further connected to the transmission line via the circuit 24. Similarly, the synchronization signal detection circuit 31, the control signal reception buffer 33, and the data reception buffer 35 are bus-connected to the serial-parallel conversion circuit 25 via the gates 1, 3 and 5, respectively, and further this circuit 25
Via the transmission line.

FIG. 6 shows an example of a device suitable for communicating analog data, and here, a device capable of transmitting and receiving voice is shown. Telephone / phone 29 which is an acoustic / electrical converter for transmitting / receiving voice, for encoding or digitizing an analog signal from the telephone 29 (for example, PCM encoding) and for converting a digital signal into an analog voice signal. A codec (CODEC, AD / DA interface or encoding / decoding circuit) 27, and a subscriber circuit 28 having functions such as transmission of dial signals and amplification of voice current are provided.
The codec 27 is bus-connected to the data transmission / reception buffers 36 and 35 and is also connected to the circuit 28. The subscriber circuit 28 is bus-connected to the CPU 20. The telephone 29 is connected to the codec 27 via this circuit 28.

The other structure is the same as that shown in FIG. 5 except that the interface 26 with the upper CPU is not provided, and therefore, the same components are designated by the same reference numerals.

FIG. 7 shows an example of a concrete configuration of the time slot gate signal generation circuit 23. A sync signal detection signal output from the sync signal detection circuit 31 (for devices 2 to n),
Alternatively, a synchronizing signal generation command signal given from the CPU 20 to the synchronizing signal generating circuit 32 is given as a start signal to the counter 59 via the OR circuit 49, whereby the counter 59 starts counting from zero. The relationship between the synchronization signal generation command signal or the detection signal and the count output of the counter 59 is shown in FIG. The counter 59 is (n +
2) Time slot number (T
S _s , TS _c , TS ₁ , TS _2, ...) Is generated. This count output is the coincidence circuit 51-
Given to 56 respectively.

On the other hand, each of the matching circuits 51 to 56 has a set value register
41 to 46 are provided. CPU for these registers
20 presets a value corresponding to a count value representing the number of the time slot in which the corresponding gate should be opened. The outputs of the registers 41-46 correspond to the matching circuits 51-
Sent to 56 each.

Therefore, in the time slot in which the count output of the counter 59 and the setting value of the register match, the gate control signals (G1 to G1) are output from the corresponding matching circuits as the matching signals.
6) occurs. For example, as shown in FIG. 8, when the set value of 1010 is set in the register 46,
The gate control signal G6 is generated in the time slot TS _4.

The time slot gate signal generation circuit 23 further includes
For gates 1 and 2, decoders 47 and 48 are provided to force and close these gates. When the CPU 20 gives a compulsory closing command for the gate 1, the decoder 47 decodes the command to generate a low level signal, and one input terminal of the AND circuit 57 is set to a low level. However, the gate control signal G1 is not transmitted. Similarly, when a command to force gate 2 to close is issued by the CPU 20, the decoder 48
Decodes this, closes the AND circuit 58, and prohibits output of the gate control signal G2.

(3.3) Synchronization establishment processing (initial processing) As described above, the device 1 has a function of creating and transmitting the synchronization signal S in order to synchronize the entire system. This device 1 does not need to receive the synchronization signal S. Therefore, the operation of the apparatus 1, especially the procedure of the processing of the CPU 20 is as shown in FIG.

When the power is turned on, first, the initial processing of the apparatus 1 itself is performed (step 101). Since the reception of the synchronization signal S is unnecessary, the compulsory closing command is given to the decoder 47 to close the gate 1, so that the gate circuit is closed.
57 is always closed, and the gate control signal G1 is not output (step 102). This state lasts forever.

Further, the CPU 20 presets the set value 0000 (corresponding to the time slot TS _s ) in the register 42, and the CPU 20 issues a synchronization signal generation command and gives it to the synchronization signal generation circuit 32 and the counter 59. This causes the counter 59 to start counting and generate a count output corresponding to the time slot sequence. Matching circuit when the set value of register 42 and the count value of counter 59 match
The gate control signal G2 is output from 52, which causes the gate 2 to open. In response to the synchronization signal generation command, the synchronization signal generation circuit 32 generates the synchronization signal S, which is sent out from the parallel / serial conversion circuit 24 to the transmission line through the gate 2 which is open at that time (step 103).

When a predetermined period T elapses from this point (step 104), the gate 2 is similarly opened and the synchronizing signal S is transmitted (step 103). If the counter 59 is a ring counter, the CPU 20 only gives the first operation command (synchronization signal generation command) and the counter self-runs to repeat the above-described operation every cycle T. Then, when the count value of the counter 59 reaches 0000, the count output of the counter rises (or falls).
Triggers the synchronizing signal generating circuit 32 by the synchronizing signal S
To generate.

The devices 2 to n other than the device 1 do not send the synchronization signal S, but receive the synchronization signal S from the device 1 and create a time slot sequence synchronized with this. Therefore, the operation in the other devices 2 to n is as shown in FIG.

Initial processing of the device itself is first performed (step
111). By this initial processing, the counter 59 is placed in the reset state, and its count output shows 0000. By setting the setting value 0000 in the register 41, the matching circuit
The gate control signal G1 is generated from 51 and passes through the AND circuit 57 (at this time, the output of the decoder 47 is at the high level).
Being delivered, the gate 1 is kept open. Also, the CPU 20 issues a compulsory closing command for the gate 2 to the decoder 48.
Is applied to the gate control signal G2, the output of the decoder 48 becomes low level and the gate circuit 58 is closed.
Is never output and gate 2 is permanently closed (step 112).

In this state, the apparatus waits for the synchronization signal S sent from the device 1 and input through the transmission line, the serial-parallel conversion circuit 25, and the gate 1. Then, when the detection circuit 31 detects the synchronization signal S (step 113), the counter 59 starts the counting operation. The count value representing the time slot sequence synchronized with the detected synchronization signal S is sequentially output from the counter 59. When the count output of the counter 59 becomes a value other than 0000, it does not match the setting value 0000 set in the setting value register 41, so the output of the matching circuit 51 becomes low level, and the output of the AND gate 57 accordingly. G1 also goes low and gate 1 is closed. When the first detection of the synchronization signal S is given to the CPU 20, the CPU 20
The set value corresponding to the last time slot TS _n of the time slot sequence is given to the register 41. When the count value of the counter 59 matches this set value, the gate control signal G1 is output and the gate 1 is opened. When the next synchronization signal S is detected, the counter 59 starts counting from zero again.
Then, again, since the count output value of the counter 59 and the set value of the set value register 41 do not match, the gate 1 is closed in the same manner as described above. In this way the device 2
In n, the gate 1 is opened and closed every period T, and each time the synchronizing signal S sent from the device 1 is received, a time slot sequence synchronized with the synchronizing signal S is created (step 114). In the devices 2 to n, the CPU2
With 0, forward protection and backward protection of the synchronization signal S are also performed (step 115).

(3.4) Message Format As the format of the control message transmitted / received by the control signal D _c and the data message transmitted / received by the data signal D _i (i = 1 to n), various formats can be adopted. As an example, a case where a format called HDLC (High Level Data Link Control) is used will be briefly described.

The frame format of this HDLC is shown in FIG. 11 (A), and the start flag (F) field (8 bits), address
(A) field (8 bits), control (control:
C) field (8 bits), information (I) field (arbitrary number of bits), check (frame check sequence; FCS) field (16 bits) and end flag (F) field (8 bits) .

The start flag field and end flag field are for identifying the beginning and end of a frame. Further, the start flag starts the inspection of the transmission error by the CRC (Cyclic Redundancy Check) method, and the end flag ends the inspection.

The address field is used to specify the address of the communicating station. For example, when the device i attempts to communicate with the device k, the device (communication partner station) k is included in the address field of the control message sent from the device i to the device k.
Is set (such as the number k), and when the device k responds to this control message to the device i, the address of the device i is set in the address field of the response control message.

When the data telegram is transmitted and received between the devices i and k after the connection between the device i and the device k is completed, the address field of the data telegram follows the rules of the HDLC procedure.
Address data is not always necessary in the data telegram. 2 data channels formed by a particular time slot after the connection is completed
This is because there is a 1: 1 relationship between the two devices.

The control field is used for distinguishing a response from a call from the local station to the remote station and a response from the remote station to the local station. This is a hall (P) in the HDLC convention,
Shown in Final (F), etc.

Information fields have different appearances in control and data telegrams.

In the control message, the information field is always composed of 16 bits, and each bit has a specific meaning as shown in FIG. 11 (B). That is, the first 8 bits b _{11 to} b ₁₈ represent the address of the own station. Continued 8
Of the bits, the first bit b ₂₁ is a connection request, the second bit b ₂₂ is a release request (connection disconnection request), the fifth bit b ₂₅ is connection completion, and the sixth bit b ₂₆ is release completion. 7th
Bit b ₂₇ represents busy (communication with another station). Since the information field contains the address of the own station (transmitting station), the partner station (receiving station) can know the position (number) of the time slot to be received corresponding to this address of the transmitting station. .

Such control messages are UI (Unnumbered In-formation)
Since the frame is configured, it will be simply referred to as a UI command or a UI response hereinafter.

In the data telegram, the information field contains the data to be transmitted. Therefore, the number of bits in this field changes depending on the length of data.

In the check field, the result of arithmetically calculating the numerical value represented by all the binary bits in the frame by the transmitting side by the CRC method for error checking is set. On the receiving side, the same calculation is performed at the receiving side and the result is compared and collated with the value of the inspection field sent to check whether a transmission error or the like has occurred.

As described above, the control signal _Dc is composed of 10 bits (substantially 8 bits) including the start bit and the stop bit. On the other hand, the control message is composed of 64 bits as can be seen from FIG. As shown in FIG. 12, the time slot sequence is repeated in the period T, so that the control message is divided into eight control signals D _{c1 to} D _c8 , which are continuously transmitted over eight periods. One control message will be transmitted and received. That is, the first control signal D _c1 is the start flag
It is configured by adding a start bit ST and a stop bit SP before and after the 8-bit data of the field. In the time slot TS _c of the next cycle,
The 8-bit address data of the address field and the bits ST and SP are transmitted as the control signal D _c2 .
In the same manner, the time of the 3rd to 8th cycles
Various data in the control message are edited in _units of 8 bits in the control signals D _{c3 to} D _c8 sent in the slot TS _c .

Just like this, the data telegram has six or more data signals D in which all the bit data constituting the data telegram are continuous.
_ij (i = 1 to n, j = 1 to m, m ≧ 6) is divided into 8 bits and transmitted. Since the number of bits of the information field is determined according to the data length to be transmitted, the number of data signals D _ij also changes accordingly.

(3.5) Connection and communication processing In FIG. 5 or FIG. 6, gates 3 and 4 are gate control signals G for interconnection of two devices to communicate.
Opening and closing are controlled by 3 and G4, respectively. Control of these gates 3 and 4 is performed in the same manner in any device.

In order to receive a UI command sent from any other device, the gate 3 receives the time slot T every cycle.
In synchronization with the S _c is opened only during the time slot TS _c. This is because, in FIG. 7, the set value corresponding to the count value of the counter 59 representing the time slot TS _c in the register 43 CPU20 is achieved by preset. Any UI command (series of control signals D _c ) being transmitted on the transmission line is stored in the receive buffer 33 through the deserializer 25 and the open gate 3. The CPU 20 decodes the UI command stored in the reception buffer 33, and if it is addressed to its own station, sends a necessary UI response (a series of control signals D _c ) as described later. When the local station sends a UI command to call another device or responds to the received UI command with a UI response, these commands or responses are edited in the transmission buffer 34 and the time slots open gate 4 in TS _c and the same timing, and sends a control signal D _c constituting the edited message in each period. This signal is converted into a serial signal by the parallel-serial conversion circuit 24 and appears on the transmission line. The gate 4 is opened in the same manner as described above.

The time slot TS _c is commonly used by all the devices 1 to n, so that the control signal D _c sent from two or more devices is used.
Can overlap (collide). For this reason, collision detection is performed as will be described later, and the case of collision is dealt with.

When the two devices are connected to each other by the communication of the UI command and the UI response to the UI command, data transmission / reception starts. At this time, opening / closing control of the gates 5 and 6 is performed by the gate control signals G5 and G6. Gates 5 and 6
The opening / closing control operation of is performed in exactly the same manner in all the devices 1 to n. That is, it is realized by setting a predetermined set value in the registers 45 (not shown) and 46.

As described above, in data transmission / reception between the device i and the device k, the time slots TS _i and TS _k are fixed. When the device i sends data to the device k is the CPU20 the transmission buffer 36 of the device i, and stores the transmission data telegram edited during this time slot TS _i in synchronization with the time slots TS _i Only the gate 6 is opened, and the data signal D _i forming the data message edited in each cycle is sent to the line through the parallel-serial conversion circuit 24. Also in the device k, the gate 5 is opened in synchronization with the time slot TS _i , and the data signal D _i sent from the device i on the transmission line is taken into the reception buffer 35 via the serial-parallel conversion circuit 25.

The connection process and the data transmission / reception process will be generally described with reference to FIGS. 13 and 14. FIG. 13 shows the operation flow of the device on the transmission side (designated as device i), and FIG. 14 shows the procedure of the operation of the device on the reception side (designated as device k).

Assuming that device i has data to be sent to device k (step 121), device i will store the address of device k in the address field, the address of its own station in the first 8 bits of the information field, and the next 8 bits. The UI command in which “connection request” (set to 1) is set in the first bit b ₂₁ of the bits is edited, and the time slot TS _c
And it sends this as a control signal D _c at the timing (step 122).

All other devices have gate 3 in time slot TS _c
Is opened to watch the control signal D _c . Device k
There When receiving the control signal D _c having a bit of contain and "connection request" to the address field of the address of the own station (device k) (step 141), currently in communication own station to other devices It is checked whether it is (busy) (step 142). If not busy, the address of the partner station i is set in the address field, the address of the local station k is set in the first 8 bits of the information field, and "connection completed" (1 is set in the fifth bit b ₂₅ of the following 8 bits). edit the UI response that sets each set), and sends the timing of the time slot TS _c (step 14
3). In the case of busy, U in which the 7th bit b _{27 is set} to 1
The I response is sent (step 147).

After sending the above-mentioned UI command, the device i opens the gate 3 in synchronization with the time slot TS _c and waits for a UI response from the device k. When receiving the UI response in which the address of the device i is set in the address field, the device i decodes the response and the address of the partner station k is stored in the first 8 bits of the information field and the fifth of the following 8 bits. It is determined whether the bit b ₂₅ is set to 1 or the 7th bit is set to 1 (steps 124 and 125).

When the UI response from the device k indicates "connection completed", the gate 6 is opened in synchronization with the time slot TS _i assigned to the own station, that is, the device i, and necessary data is transmitted.

The device k which has sent the UI response of “connection completed” opens the gate 5 in synchronization with the time slot TS _i in preparation for the communication with the device i, and waits for the arrival of the data telegram from the device i.

In this way, data is transmitted from the device i to the device k in the time slot TS _i (steps 126 and 144).

At this time, if there is data to be transmitted from the device k to the device i, it is possible to perform connection processing using the control signal and then transmit this data using the time slot TS _k .

When the device i finishes sending all the data to be sent to the device k (step 127), the device i receives the address (address field) of the device k, the address of its own station i, and the "release request" (second bit b). ₂₂ ) UI command with (information field) is set to time slot TS
It is sent at the timing of _c (step 128).

Device k receives this "release request" UI command (step 145), "release completion" (the sixth bit b ₂₆₎ sends a UI response that sets (step 146),
Finish the process. In device i, this U from device k
When the I response is received (step 129), the processing is similarly ended.

When the device i receives the "busy" UI response from the device k (step 124), the process proceeds to the partner busy process (step 130). At this point, the device i
Cannot communicate with device k.

The other party's busy process is a process of issuing a connection request again after a certain time in the case of data communication. In the telephone system, a "busy tone" is generated in the telephone and the connection request is made again after a certain time if necessary. Refers to the process of issuing.

When the system according to the present invention is applied to a local telephone exchange system, the PCM as already described in FIG.
Coded voice data is transmitted and received between the devices. In a telephone exchange system, it is impossible to hold voice data in a buffer or the like for a long period of time, so quick communication is necessary. For example, if the period T is set to 125 μS and each time slot is set to 10.417 μS, this system can be applied to 10 telephones. Audio is 8KHz
Since it is sampled every 1/8000 = 125 μS, one sampling data may be transmitted / received every 125 μS. Of course, the device i in time slot TS _i to device k, it is possible to send audio to device i from the device k in time slot TS _k, the possible bidirectional call course.

In the above-mentioned embodiment, since all the n devices have the synchronizing signal generating function, even if the device generating the synchronizing signal goes down, another device instead generates the synchronizing signal and the system is activated. It is possible to continue communication in.

It is also possible in a system according to the invention for one device to send data to multiple devices simultaneously. For example, setting the global address in HDLC in the address field allows one device to connect to all other devices. When one device connects to any number of devices, one device may issue a connection request to each device.

(3.6) Collision detection Fig. 15 shows an example of the collision detection circuit. The signal sent from the device is converted into a serial signal by the parallel-serial conversion circuit 24, and then sent out to the transmission line through the line driver 61. The signal on the transmission line is received by the line receiver 62 and then input to the serial-parallel conversion circuit 25. The input side (point A) of the line driver 61 and the output side (point B) of the line receiver 62 are connected to the exclusive OR circuit EOR63. The output side (point C) of the EOR 63 is connected to the differentiating circuit 64 and the data input terminal D of the DT flip-flop 66. The differentiating circuit 64 detects the rising edge of the input signal, and the detection signal resets the counter 65. The counter 65 is, for example, a decimal counter, and starts counting from zero by a reset signal. A signal representing a certain count output (count value C _N , eg 5) of the counter 65 is sent to the timing input terminal T of the DT flip-flop 66. The clock supplied to the counter 65
It is assumed that the pulse has a speed 10 times as long as one bit length of the signal. The output signal Q of the DT flip-flop 66 becomes the collision detection signal.

FIG. 16 shows the operation of this collision detection circuit,
(A) shows a case where no collision has occurred, and (B) shows a case where a signal collision has occurred.

Referring to FIG. 16 (A), the device drives the line driver 61.
The signal sent to the transmission line via the line is also input to the line receiver 62. Therefore, signals with almost the same waveform appear at points A and B, but these signals are
The driver 61 and the line receiver 62 are out of phase by the delay time td. This phase shift is detected by the EOR 63, and the counter 65 is reset by the rise of the detection signal detected by the differentiating circuit 64.
65 starts counting. When the count value of the counter 65 reaches C _N , a pulse is given to the timing input terminal T of the DT flip-flop 66. However, since the signal at point C (data input D) is at low level at this point, the DT flip-flop 66 is not set.

In FIG. 16 (B), when a signal sent from another device (a signal at point A) and a signal sent from another device are propagating on the transmission line, these signals were noticed. A signal appears on the transmission line in a form, and a signal waveform slightly delayed from this appears at point B. Therefore, a wide signal may appear in the EOR operation result (point C) of the signal at point A and the signal at point B. When the output of the counter 65 is applied to the DT flip-flop 66 while the signal at the point C is at the high level, the DT flip-flop 66 is set, so that the signal collision is detected.

This collision detected means that another device is transmitting, so that device waits until the channel is empty.

[Brief description of drawings]

1 (A) and 1 (B) are block diagrams schematically showing examples of the overall configuration of a data transmission system according to an embodiment of the present invention. FIG. 2 is a time chart showing the timing relationship of the entire system. FIG. 3 shows the transmission / reception timing of signals between two devices and the bit configuration of each signal. FIG. 4 shows the bit structure of the synchronization signal. FIG. 5 and FIG. 6 are block diagrams respectively showing examples of the hardware configuration of the apparatus. FIG. 7 is a block diagram showing an example of a concrete configuration of the time slot gate signal generating circuit, and FIG. 8 is a time chart showing its operation. 9 and 10 are flow charts showing the synchronization establishing process, and FIG. 9 is a flow chart of the device for transmitting the synchronization signal.
The figure shows the operation of each of the other devices. FIGS. 11A and 11B show the HDLC message format. FIG. 12 shows how a message is transmitted and received over a plurality of cycles. 13 and 14 show the connection and communication processing between the two devices. FIG. 13 shows the operation on the originating side, and FIG. 14 shows the operation on the receiving side. FIG. 15 is a block diagram showing an example of a concrete configuration of the collision detection circuit, and FIGS. 16 (A) and 16 (B) are waveform charts showing the operation thereof. 20 ... CPU, 23 ... Time slot gate signal generation circuit.

Claims (2)

[Claims] 1. A plurality of devices, which are connected by a transmission / reception combined transmission line and are provided with an identification code in advance, and a means for transmitting a synchronization signal at a constant cycle. Each device has a synchronization signal as a reference. A plurality of time slots divided by a number that is at least two or more larger than the number of devices within the fixed period, and the time length of each time slot is a duration from the beginning to the end of a signal to be communicated. A length including time plus twice the maximum propagation delay time between devices, and one of these time slots is a synchronization for synchronizing a communication signal between a transmitting device and a receiving device. For signals, the other one requires a connection request signal transmitted from a device requesting the start of data communication, a connection completion signal transmitted from a device requested to start the data communication, or the end of data communication. Release request signal transmitted from the device that requests the end of the data communication, the release completion signal transmitted from the device that requested the end of the data communication, the identification code of the device requesting the start or the end of the data communication, and the device requested to start or end the data communication. Means for creating such time slots, for transmitting and receiving control signals containing the identification code of, and for the remaining time slots for data transmission;
The first gate, which is opened in synchronization with the slot and closed after the time of this time slot has elapsed,
A second gate that is opened synchronously with the slot and closed after the time of this time slot has elapsed.
The third gate, which is opened in synchronization with the slot and closed after the time of this time slot has elapsed, is opened in synchronization with the control signal transmission / reception time slot when the control signal is received, and this time A fourth gate which is closed after the lapse of the time of the slot, which is opened in synchronization with a data transmission time slot which is previously assigned for data transmission for each device identification code when transmitting data, Fifth gate which is closed after the time of the time slot elapses. For transmitting data assigned to the partner device when data is to be received after the partner device to communicate with is determined by sending and receiving control signals. A sixth gate opened synchronously with the time slot and closed after the time of this time slot has elapsed, as well as the start of data communication. When the request is made, the third gate is opened to send the control signal to the transmission line, and the fourth signal is sent at the constant cycle.
Open the gate of the control signal to take in the control signal from the transmission line, and after sending and receiving the control signal to determine the device to communicate, open the fifth gate to send the data to be transmitted to the transmission line or the sixth gate. Open to take in data from the transmission line, and when requesting the end of data communication, open the third gate to send a control signal to the transmission line, and open the fourth gate at the above-mentioned constant period. A data transmission system between a plurality of devices, which comprises means for controlling so that a control signal is taken in from a transmission line and communication is terminated by sending and receiving the control signal. 2. A means for transmitting a synchronization signal is included in one device, and the time slot creating means of the one device creates a time slot on the basis of the synchronization signal to be transmitted, The time slot creating means of another device creates a time slot by receiving a synchronization signal transmitted from one device and using the received synchronization signal as a reference. A data transmission system between a plurality of devices described in 1.