JPH063917B2 - Interrupt arbitration system - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt arbitration system, and more particularly, to prioritizing interrupt requests to CPUs from a plurality of external devices sharing a single CPU bus. An interrupt arbitration system that arbitrates equally.

[Prior Art] When a plurality of external devices are connected to a single CPU bus and an interrupt request from the external device is processed, each external device generates an interrupt request at an arbitrary time. May occur. However, since the CPU cannot process a plurality of interrupt requests at the same time, it is necessary to arbitrate the interrupt requests by some method and process them one by one.

Hitherto, in order to arbitrate interrupt requests from a plurality of external devices, methods such as a daisy chain method and a polling method have been used.

[Problems to be solved] In the above-mentioned conventional method using the daisy chain, since the interrupt request lines from a plurality of external devices are connected by the daisy chain, priority is given to each external device, and the interrupts of all devices are interrupted. It cannot be used when you want to treat the Further, in the daisy chain, when the external device is mounted on the motherboard in a removable structure, if one external device is removed, all interrupts of the external device with lower priority cannot be accepted.

Even when the polling method is used, the priority order is usually determined by the polling order, and the sequence becomes complicated when the priority order is not desired. Also, when the number of external devices is large, it takes a very long time to poll all the devices.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an interrupt arbitration system that arbitrates interrupt requests from a plurality of external devices in a simple and equal manner without setting priorities.

[Means for Solving Problems] In order to achieve the above object, the interrupt arbitration system according to the present invention uses CPs from a plurality of external devices sharing a CPU bus.
In a system that arbitrates interrupt requests for U,
The external device is provided with a generation circuit for giving an interrupt arbitration clock in which a device number is encoded, and the external device issues an interrupt request to the CPU and outputs an interrupt vector when an interrupt acknowledge signal is received from the CPU. And the CPU only when the interrupt request line is negated when the interrupt request is generated and the decode value of the interrupt arbitration clock matches the device number preset in each external device.
Means for enabling reception of the interrupt acknowledge signal of is provided.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of an interrupt arbitration system according to an embodiment of the present invention. FIG. 2 is a time chart showing the operation of the interrupt arbitration system shown in FIG.

In FIG. 1, reference numeral 1 is a main CPU, and a plurality of external devices 2-1, 2-2, ... Are connected to one CPU bus. A control circuit 3 outputs an interrupt request signal IREQ when an interrupt request is issued to the main CPU 1. Then, the main CPU 1 issues an interrupt acknowledge signal IA.
When CK is returned, the interrupt vector is put on the data bus and the main CP confirms that it is the device that generated the interrupt.
Notify U1. Reference numeral 4 denotes a device number setting unit that sets individual numerical values in advance in binary numbers for each external device 2.

Reference numeral 5 denotes an arbitration signal generation circuit provided in an external device, which decodes the interrupt arbitration clock signals SEL0 to SEL2 from the interrupt arbitration clock generation circuit 6 and compares the decoded value with a device number set in advance. , If they are equal, the arbitration signal SEL is asserted. 7
Is an interrupt acknowledge reception circuit, which is an interrupt acknowledge signal TIACK of the main CPU 1 only under a certain condition.
Can be accepted by the control circuit 3. The interrupt request line TIREQ from each external device 2 is connected by wired OR.

The circuit in the external device 2 is shown only for the external device 2-1, but the external devices 2-2, 2-3 ... Have the same configuration.

In this embodiment, the interrupt arbitration clock signals SEL0 to SEL0
Although SEL2 converts 0 to 7 into a binary number and the number of external devices 2 is 8, the number of external arbitration clocks 9 can be increased by increasing the number of bits of the interrupt arbitration clock.

In the above configuration, each control circuit 3 generates an interrupt request at an arbitrary time and asserts the interrupt request signal IREQ. However, each control circuit 3 can receive the interrupt acknowledge signal IACK and output the interrupt vector only when the point G1 in the interrupt acknowledge reception circuit 7 is at "H" level. The G1 point becomes the “H” level when the following three conditions are met.

The interrupt request signal IREQ is asserted.

The interrupt request line TIREQ is negated.

The arbitration signal SEL is asserted.

That is, none of the external devices 2 other than itself has asserted the interrupt request, and its own arbitration signal SEL.
Is asserted, the interrupt acknowledge signal IACK of the main CPU 1 can be accepted.

Usually, only one of the above three conditions is sufficient.
However, if there is no condition of (2), when two or more external devices 2 generate interrupt requests at exactly the same time, the two or more external devices 2 simultaneously generate the interrupt acknowledge signal IAC.
It is possible that K will be accepted. For this reason, in the present invention, the condition is added to prevent this.

[Effect of the Invention] As described above, the present invention provides a plurality of interrupt arbitration clocks to external devices, and each external device has means for accepting an interrupt acknowledge signal only under a certain condition. Even if the external devices simultaneously generate interrupt requests, it is possible to prevent the collision on the interrupt vector data bus output by each external device.

[Brief description of drawings]

FIG. 1 is a block diagram of an interrupt arbitration system according to an embodiment of the present invention, and FIG. 2 is a timing chart of the system of FIG. 1: Main CPU 2: External device 4: Device number setting section 5: Arbitration signal generation circuit 6: Interrupt arbitration clock generation circuit 7: Interrupt acknowledge reception circuit

Claims (1)

[Claims] 1. A system for arbitrating interrupt requests to a CPU from a plurality of external devices sharing a CPU bus, comprising a generating circuit for supplying an interrupt arbitration clock in which a device number is coded to the external device. The device has means for making an interrupt request to the CPU, outputting an interrupt vector when the interrupt acknowledge signal is received from the CPU, and an interrupt request line being negated when the interrupt request is generated, and An interrupt arbitration system comprising means for accepting the interrupt acknowledge signal of the CPU only when the decoded value of the arbitration clock matches the device number preset in each external device.