JPH063918B2 - Integrated wiring system - Google Patents

Description

The present invention relates to a data transmission system using a microcomputer, and more particularly to an integrated wiring system suitable for transmitting various control signals in a vehicle.

[Conventional technology]

For example, in automobiles, many electrical components such as various lamps and motors, various switches and sensors for control, and electrical devices such as actuators (hereinafter, these electrical components and electrical devices are called loads) are arranged. However, the number has been increasing with the progress of car electronics, and the total number has reached to several hundred.

Therefore, as in the past, wiring was performed individually for a large number of these loads, large-scale and extremely complicated wiring is required, and cost increase, weight increase, space increase,
Alternatively, a big problem such as mutual interference occurs.

Therefore, using a common transmission line such as an optical fiber, data transmission between various loads is performed by microcomputer control (microcomputer control) at the central office.
A so-called integrated wiring system is disclosed, for example, in JP-A-60-551.
It is disclosed in Japanese Patent Publication No.

By the way, in such an integrated wiring system, a connection condition between various loads is tabulated as a predetermined logic (hereinafter, this is a wiring logic) and a table is searched for connection between the various loads. Although the control is performed, the above prior art does not pay particular attention to the above-mentioned wiring logic table formation.

Note that, specifically speaking of this wiring logic, when a switch that is a human load and a lamp that is an output load are assumed, which lamp (including multiple cases) is closed when which switch (including multiple cases) is closed. Including) represents the condition of whether to fall.

[Problems to be solved by the invention]

As is clear from the above description, the wiring logic in the integrated wiring system is a logical operation expression representing the connection condition between the loads.

However, in the above-mentioned prior art, no particular consideration is given to the description format when tabulating this logical operation expression,
Therefore, there is a problem that it takes time to search the table.

This will be described below. For example, an automobile power window device is provided with a key switch: KS door lock switch: LS main switch: MS door switch: DS window drive motor: M, and a wiring logic between them. Is represented by M = KS * LS * (MS + DS), which must be stored in memory and tabulated.

By the way, the following two methods have been conventionally considered as specific methods for storing such wiring logic information in a memory.

1. High-level linguistic method 2. The assembler method. Of these, the former high-level language method is a method of storing necessary wiring logic as it is in the memory in the same idea as languages such as BASIC and FORTRAN. For example, in the above example, KS, L
After encoding S ... etc. and storing it in the memory, a search will be performed.

However, in this case, since the parentheses are included in the expression, the operators cannot be executed in order from the left. In particular,*,
There are three operators, *, +, but the rightmost + must be executed first, then the leftmost *, and finally the middle *. In this method, it is not possible to determine the priority of such operators, so it takes a huge amount of time to search the memory.

Also, if this method is adopted, the input and the operator must be encoded respectively. At that time, the input data is 1
Since it takes only / 0, only one bit should be used, but in reality there are many types of operators (AND, O
R, NOT, etc.), therefore, must be expressed using multiple bits. At that time, since the search for each bid takes time, it has been required to apply a method of shortening the search time by other means.

Next is the latter assembler method. This method is, for example, in the above example, It is something that is stored in memory.

However, with this method, the number of processing steps becomes enormous, and the wiring logic cannot be expressed as an equation.
There is a problem of poor productivity and maintainability.

The object of the present invention is to be able to deal with the above-mentioned problems of the prior art and (1) be general in expression.

(2) What can be expressed by the minimum representation method.

(3) High-speed processing is possible.

(4) Easy to change such as adding and deleting logic.

It is an object of the present invention to provide a description method and its expansion method that satisfy the above conditions and are suitable for the expression of logic including a plurality of logical operators such as AND and OR, which is a peculiar problem in the integrated wiring system.

[Means for solving problems]

According to the present invention, the wiring logic in the integrated wiring system is described by the reverse Polish notation, stored in the memory and tabulated, and the connection in the case where the input / output relationship is 1: 1 is used as the table. Two types of tables are provided: a one-to-one wiring table that describes the conditions and a general wiring table that describes the connection conditions when the input / output relationship is other than one-to-one, and the input data and operation for the general wiring table are performed. Each byte of data is assigned to the description of the child data, and the input data and the operator data are distinguished by the most significant bit of each byte.

Here, the reverse Polish notation will be described.

A logical operation expression is generally expressed as follows, for example.

However, in the reverse Polish notation, the right side of this logical operation expression is expressed as follows.

Therefore, for example, the right side of y = X + Y → XY + y = (W + X) * (Y + Z) right side → WX + YZ ++.

[Action]

According to the reverse Polish notation, operators are described in order of their priority.

For example, if the right side of the above equation M = KS * LS * (MS + DS) ... (a) is represented by the inverse Polish K method, it becomes KSLSMSDS + ** ... (b).

In the expression (a), the operators are not arranged in the execution order, whereas in the expression (b), the operators are arranged in the execution order.
Data processing time is reduced.

The wiring table is divided into a one-to-one wiring table and a general wiring table. As a result, when the input / output relationship is one-to-one, a simple one-to-one wiring table search is performed. Since it is only necessary, the data processing time can be further shortened.

Furthermore, since 1 byte of data is assigned to each of the description of the input data and the operator data in the general wiring table, the input data and the operator data are distinguished by the most significant bit of each byte. Since the input and the operator can be discriminated only by examining the most significant bit, the data processing time can be shortened.

〔Example〕

Hereinafter, the integrated wiring system according to the present invention will be described in detail with reference to the illustrated embodiments.

FIG. 1 is an embodiment of the present invention. In this system, an optical fiber cable OF is used as a signal transmission line, and a central control unit CCU (hereinafter, simply referred to as CCU, which is a Cent
Ral Control Unit) 10 and a plurality of terminal processing devices LC
U (hereinafter referred to simply as LCU, this is Local Cont
RL Unit) 11 to 14 are commonly coupled by an optical signal channel, and an optical branch connector OC is provided at a branch point of the optical fiber cable OF.

The CCU 10 is installed at an appropriate place such as near the dashboard of an automobile and controls the entire system.

LCU 11 to 14 are various operation switches SW and meter M
A predetermined number of the display devices, lamps L, sensors S, etc. are arranged in the vicinity of loads installed in the automobile in a dispersed manner.

Photoelectric conversion modules O / E 66 to 68 for bidirectionally converting an optical signal and an electric signal are provided in a portion where the CCU 10 and each of the LCUs 11 to 14 are coupled to the optical fiber cable OF.

The CCU 10 includes a microcomputer 18 and has a data communication function by serial data. Corresponding to this, each LCU has a communication processing circuit CIM (hereinafter simply referred to as CIM, which is an abbreviation of Communication Interface Module) 15 to 17 Is provided, the CCU sequentially selects one of the LCUs, exchanges data with the LCU,
By repeating this, it becomes possible to perform multiplex transmission via the one-channel optical fiber cable OF, and it is possible to simplify complicated and large-scale wiring in the vehicle.

The CCU 10 is provided with three types of tables: a microcomputer 18 monitor table 97, a control table 98, and an arrangement table 99.

In the monitor table 97, the CCU 10 has LCUs 11 to 14
And the data sent back to the CCU 10 from the LCUs 11-14. It should be noted that the reason why both the data before and after transmission is stored is that a method is adopted in which both data before and after transmission are checked and the control data is sent from the CCU 10 only for loads where they do not match. is there.

The control table 98 has a function of storing data to be sent to each load, such as on / off data.

The wiring table 99 serves to store the above-mentioned wiring logic.

FIG. 2 shows the configuration of the CIMs 15 to 17 in the embodiment of FIG. 1, RXD is the received data input as serial data, TXD is the same transmitted data, XTA.
L is the signal from the crystal oscillator installed in each CIM,
EXTAL is an output terminal.

The clock line 308 receives the clock signal supplied from the oscillation circuit 310 and the synchronization signal from the synchronization circuit 309,
Two-phase clocks φ _M and φ _S whose phases are shifted by a half cycle are generated and supplied to the stage counter 306.

The stage counter 306 controls the clocks φ _M and φ.
_The stage decoder 307 operates by _S and recognizes the state of the entire CIM such as reception and transmission by the ucant value. The result is decoded by the stage decoder 307, and various control signals necessary for the operation are sent to the stage decoder 3
It is output from 07.

On the other hand, loads including various electric devices such as switches, lamps, meters, and sensors are connected to the input / output terminals of the I / O buffer 301. And this I /
The input / output terminal of the O buffer 301 can be arbitrarily selected in advance in accordance with the type of load to be connected thereto, and its address is designated by the address decoder 304 to input the address value ADDR0. ~ AD
It is designed to be given by the decoding of DR5.

The 25-bit shift register 302 is the I / O buffer 3
01 parallel data transmission, and on the other hand, the received data RXD input as serial data is serially written to the shift register 302 as it is, and then parallel transmitted to the I / O buffer 301. It Similarly, the data in the I / O buffer 301 is written in parallel to the shift register 302, and then serially read from the shift register 302 to become the transmission data TXD.

Fail-safe data is previously stored in the fail-safe register 305 from the shift register 302. The fail-safe data is stored in the I / O from the fail-safe register 305 when a transmission error occurs.
The data is transmitted in parallel to the O buffer 301, which guarantees fail-safe.

For other required control signals, etc., MPU
MPU interface unit 311 for controlling the state of (micro processing unit), transmission mode,
It is generated from a mode decoder 312 that defines a CIM mode called a reception mode and a comparator 303 that detects an address error.

Therefore, the received data RXD transmitted from the CCU is transmitted in parallel from the I / O buffer 301 to each load, while the data from each load is I / O gable 301.
From the parallel shift register to the shift register 302,
It is serially read and becomes transmission data TXD, and CCU
Will be sent to.

Next, a data transmission operation using the above various tables will be described.

FIG. 3 shows the relationship between the monitor table and each CIM. The monitor table and the control table are as follows.
There are 16 data for each CIM. This is because, in this embodiment, the I / O buffer of each CIM has 16 input / output terminals and the number of connectable loads is 16, as shown in FIG.

Then, the same number of tables as the number of CIMs are secured. In this embodiment, the number of CIMs is 9.

As described above, the monitor table is used for each CIM before and after transmission.
The data of is stored.

Therefore, assuming that when the switch SW1 of the CIM1 is turned on, the lamp L is controlled to light by having a predetermined wiring logic, the control procedure at this time is as follows. .

(1) Each CIM transmits data indicating the load state to CC.

(2) The CCU, after receiving the data from each of these CIMs,
Store it in the monitor table. Then, the data before and after the transmission in the monitor table is checked to find the changed portion. At this point, the CCU determines which switch of each CIM has been turned on / off (in this case the S of CIM1).
Know W1).

(3) Input the data stored in the monitor table,
Refer to the wiring table. Then, based on the wiring logic, load data, that is, information such as which lamp is to be turned on / off (L in CIMI in this case) is determined.

(4) The CCU transmits the data of the monitor table in the order based on the control table of each CIM via the transmission path. CI
After receiving the data, M1 turns on the lamp L.

Next, a method of generating control data using these tables will be described more specifically.

By the way, one of the features of this embodiment is that this wiring table is divided into two types, and each of them is set as follows.

That is, first, one table describes the input / output relationship in a one-to-one correspondence, which is called a wiring table as it is. Next, in the other table, it is assumed that the wiring logic for the input / output relations other than one-to-one relation, that is, the relation of many-to-one relation is described by the above-mentioned reverse Polish notation, and this is called a general wiring table.

Then, in the wiring table, as shown in FIG.
The first bit of the second byte is used as a flag, and when this bit is "0", the input / output relationship is one-to-one correspondence. Therefore, at this time, only this wiring table can be referenced. This means that the output is given, and when this bit is "1", the relationship of the output to the input is a many-to-one correspondence. Therefore, at this time, the general wiring logic table GET is further added.
The output is determined by also referring to BL.

Here, the fact that the wiring table shown in FIG. 4 (a) has a one-to-one correspondence is as follows.

That is, not only when the input / output relationship is actually one-to-one correspondence but also when it is many-to-one correspondence, anyway, in this wiring table, the one-to-one correspondence is described. is there. That is, AND, OR of multiple inputs
Even in the case of so-called general wiring logic in which the output is determined by taking the above, the logic is decomposed into a one-to-one relationship for all inputs.

For example, if there is a wiring logic of y = a + b + c, the output for the input a is stored in this wiring table as y, y for b, and y for c.

An example of the store is shown in FIG. 4 (b). This shows that for input CIM # 5, terminal #F, output CIM # C,
Terminal # 0, 1: 1.

Input CIM # 0, output CIM # for terminal # 0
9, terminal 6. Many-to-one.

Becomes

Further, the general wiring logic table GETBL is as shown in FIG. 5, and the wiring logic for the output is described in reverse Polish notation.

Here, three types of operators: NOT: (80) _H AND: (C0) _H OR: (E0) _H are adopted, and in addition, end: (FF) _H is used.

Therefore, in the first line of FIG. 5, the input logic (CIM # 2, terminal # 4) * (CIM # A, terminal # 0) is described for the output, CIM # 3, and terminal #D. Therefore, in the second line, for the output, CIM # 3, terminal #E, the input logic {(CIM # D, terminal # 0) + (CIM # 9, terminal # 3)} * ( CIM # 5, terminal # 0) are described.

Furthermore, the third line describes the input logic (CIM # 0, terminal # 3) + (CIM # 5, terminal # 5) for the output, CIM # 4, and terminal # 5. .

The third byte in the table of FIG. 5 is provided to facilitate control during table search.

Next, a specific control data generation process using these tables will be described with reference to FIGS. 6 and 7.

In FIG. 6, (1) the contents of the old monitor table are all cleared in advance.

(2) The switch ON information is stored in the new monitor table. In this case, the inputs are CIM # 0 and terminal # 2. This input data is searched by checking the old and new monitor tables.

(3) Search the wiring table to find out which output terminal the input data is connected to. Since the specifications of the wiring table are as shown in FIG. 4, the output is obtained by sequentially searching the input CIM # and the input terminal #. In this case, the output is CIM # 0 and terminal # 1. The second byte has (80) _H, and the most significant bit is 1. Therefore, the corresponding logic has multiple inputs and one output.

(4) Search the corresponding part of the general wiring logic table GETBL. The specifications of this table are as shown in FIG.
Since the IM # and the output terminal # are located at the leftmost side of the table, the corresponding output, in this case, the row of CIM # 0 and the terminal # 1 is searched.

(5) Assume that the relevant line of GETBL is as shown in FIG. In this case, positive data (data in which the first bit of each byte is “0”) is input using two bytes, CIM #,
Represents terminal #, negative data (also the first bit is "1"
Data) is represented using 1 byte. For example, in this example, the terminal # 2 of CIM # 5 and the terminal # 2 of CIM # 0 are ORed and stored in the terminal # 1 of CIM # 0.

(6) For input data, ON / OFF information is retrieved from the monitor table and stored in the buffer. The operator ((C0) _{H in} this case) and the end determination (FF) _H are stored as they are. As a result, both the input data and the operator are stored in the buffer as 1-byte data.

(7) Perform stack operation and calculate output data. In this method, data is checked byte by byte from the left, and when it is negative, that is, when it is an operator, the operation is performed on the previous two 1-byte data. In this example, (0
0) _H , (01) _H , and when (C0) _H , the OR operation of both data is performed for the first time.

(8) Store the output data in the monitor table. Therefore, the monitor table is as shown in FIG. 8, which is supplied to the load and the lamp is turned on.

Therefore, according to this embodiment, even when the input / output relationship is many-to-one and the logical relationship is complicated, the general wiring logic table used for this operation is described in the reverse Polish notation. The processing required for is efficient and a high-speed response is obtained.

Further, in the above embodiment, the wiring table is divided, and when the input / output relationship is one-to-one, the high speed response can be obtained also by this.

Further, in the above embodiment, 1 byte is used for describing the input data and the operator data for the general wiring logic table, and the two are distinguished by the most significant bit of each byte.

Therefore, the input and the operator can be discriminated only by loading the data into the accumulator and discriminating the most significant bit, and the shift operation for each bit in which the output efficiency is poor becomes unnecessary. As a result, a higher speed response becomes possible.

〔The invention's effect〕

According to the present invention, since the wiring logic expression can be generalized and can be expressed by the minimum expression method, there is an effect that the integrated wiring system can be controlled efficiently and at high speed.

Furthermore, since changes such as addition and deletion of logic become easy, there is an effect that even if the input / output relationship must be changed by changing the load manufacturer, model, etc.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram showing an embodiment of an integrated wiring system according to the present invention, FIG. 2 is a block diagram showing an example of CIM, and FIG. 3 is a data transmission using a table in an embodiment of the present invention. Explanatory diagram, FIG. 4 is an explanatory diagram showing an example of a wiring table, FIG. 5 is an explanatory diagram showing an example of a general wiring logic table, and FIG. 6 is an explanatory diagram showing the data transmission process more specifically. , FIG. 7 is an explanatory diagram of the final data generation processing, and FIG. 8 is an explanatory diagram of the monitor table. 10 ... CCU, 11-14 ... LCU, 15-17 ... CI
M, 18 ... Microcomputer, 66-68 ... Photoelectric conversion module, 97 ... Monitor table, 98 ... Control table, 99 ... Wiring table, 301 ... I / O buffer,
302 ... Shift register, 303 ... Comparator, 30
4 ... Address decoder, 305 ... Fail safe register, 306 ... Stage counter, 307 ... Stage decoder, 308 ... Clock circuit, 309 ... Synchronous circuit, 31
0 ... Oscillation circuit, 311 ... MPU interface, 312
… Mode decoder.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Fumio Hamano Inventor Fumio Hamano 2520 Takaba, Katsuta-shi, Ibaraki Sawa Plant, Hitachi, Ltd. (56) References JP-A-57-203336 (JP, A) JP-A-60 -73731 (JP, A) JP 61-210480 (JP, A) JP 59-3688 (JP, A)

Claims (1)

[Claims] 1. A wiring table in which connection conditions between a plurality of terminals are described and stored in reverse Polish notation is provided, and under the computer control by the central office including a search of the wiring table, a connection between the plurality of terminals is performed. In an integrated wiring system in which data transmission is performed via a common data transmission system, as the wiring table, a one-to-one wiring table describing connection conditions when the input / output relationship is one-to-one, and input / output. Two types of tables, the general wiring table that describes the connection conditions when the relationship is other than one-to-one, are provided, and 1-byte data is assigned to each of the input data and the operator data description for the general wiring table. An integrated wiring system characterized in that the input data and the operator data are distinguished by the most significant bit of each byte.