JPH063959B2 - Solid-state image sensor - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a solid-state image sensor of a contact type, particularly a contact type.

[Technical background of the invention]

FIG. 1 is a plan view showing the structure of a general contact type CCD linear image sensor. In this image sensor, unit sensor chips 2 to 5 each provided with a photosensitive portion 1 formed by linearly arranging a plurality of photosensitive pixels such as pn junction photodiodes are provided on a substrate 6 made of, for example, ceramics. Are arranged in two rows in a zigzag pattern.

In the image sensor having such a structure, an original for reading an optical pattern is sequentially moved in the Y direction in the drawing, and the optical pattern is formed on the sensor by a 1: 1 equal-magnification imaging optical system. The signal charges corresponding to the respective light quantities are generated in the respective photosensitive parts 1 of the respective unit sensor chips 2 to 5. Further, this signal charge is read and scanned in the X direction in the drawing to obtain an electric signal corresponding to the optical pattern for each scanning line.

By the way, in such an image sensor, in order to prevent the omission of the reading of the optical pattern in the X direction, the unit sensor chips 2 to 5 are arranged in two rows in a zigzag manner as shown in FIG. It is arranged. For this reason,
The unit sensor chips 2 and 4 and the unit sensor chips 3 and 5 read signals corresponding to optical patterns on different scanning lines on the original. Therefore, when the signal of the optical pattern on a certain scanning line is read by the unit sensor chips 2 and 4, the unit sensor chips 2 and 4 keep the period until the optical pattern on this scanning line reaches the unit sensor chips 3 and 5. Signal must be retained. In the conventional image sensor, a storage circuit is provided externally for holding this signal, and the signals read from the unit sensor chips 2 and 4 are sequentially stored in this storage circuit, so that the unit sensor chips 3 and 5 can be stored.
The storage signal on the scanning line corresponding to the signal read from is read from the storage circuit and signal processing is performed to obtain the signal corresponding to the optical pattern on each scanning line.

[Problems of background technology]

The conventional solid-state image sensor as described above requires an external memory circuit, and it is conceivable to integrate this memory circuit in the unit sensor chips 2 and 4, for example. However, when a memory circuit is configured in the unit sensor chips 2 and 4, the unit sensor chips 2 and 4 and the unit sensor chips 3 and 4 are formed.
5 has a different structure and requires two types of unit sensor chips, which causes a drawback that the manufacturing cost of the image sensor becomes expensive. Further, in the conventional image sensor, there is a drawback that the control required for the processing for storing and reading the signal in the memory circuit becomes complicated.

[Object of the Invention]

The present invention has been made in consideration of the above circumstances, and an object thereof is to reduce the manufacturing cost by using only one type of unit sensor chip without the need to provide an external storage circuit. An object of the present invention is to provide a solid-state image sensor that can be controlled and can be easily controlled.

[Outline of Invention]

In order to achieve the above object, according to the present invention, one unit sensor chip is provided with a photosensitive section in which a plurality of photosensitive pixels are arranged in a straight line, and signal charges obtained by the photosensitive section are sequentially transferred in a predetermined direction. Transfer register, a plurality of charge storage gate electrodes provided between the photosensitive section and the transfer register, each of which is controlled by a multi-phase clock pulse, and the photosensitive section in the substrate below each of the charge storage gate electrodes. A plurality of unit sensor chips arranged in parallel in two rows in a zigzag manner, and a plurality of charges in the unit sensor chips arranged in the one row. The multi-phase clock pulses are sequentially applied to the memory gate electrode from the side closer to the transfer register, so that a plurality of scanning lines on a plurality of scanning lines are formed within one cycle period of the clock pulse. The signal charges corresponding to the logic pattern are moved by one under each charge storage gate electrode, and the plurality of charge storage gate electrodes in the unit sensor chip arranged in the other row are provided with the above-mentioned multiphase By sequentially applying the clock pulse from the side closer to the photosensitive portion, the signal charge corresponding to the optical pattern on one scanning line is transferred to the transfer register via the plurality of charge storage gate electrodes within one cycle period of the clock pulse. The charges are transferred to under the charge storage gate electrode.

Example of Invention

An embodiment of the present invention will be described below with reference to the drawings. The solid-state image sensor according to the present invention constitutes, for example, the contact type CCD linear image sensor shown in FIG. 1, in which the unit sensor chips 2 to 5 are arranged along the plan view of FIG. 2 and the line AA '. It is configured as shown in the sectional view of FIG. This unit sensor chip uses, for example, a p-type silicon substrate 11, and in its surface region, a plurality of n ⁺ -type regions 13 forming a photosensitive pixel 12 formed of a pn junction photodiode together with the p-type silicon substrate 11 are linearly arranged. Has been done. That is, as shown in FIG. 2, a plurality of photosensitive pixels 12 are linearly arranged to form the photosensitive unit 1.
Is configured. The barrier electrode 14 is provided adjacent to the photosensitive portion 1.
However, the storage electrode 15 is adjacent to the barrier electrode 14, and the four storage electrodes 16 to are further adjacent to the storage electrode 15.
19 are provided respectively. The one storage electrode 1
A shift electrode 20 is provided adjacent to 9. The barrier electrode 14, the storage electrode 15, and the four storage electrodes 16 to 1
9 and the shift electrode 20 are provided with respective control terminals 21 to 27, and these electrodes are controlled by a constant DC voltage or a clock pulse applied to the control terminals 21 to 27. The signal charge generated in the pixel 12 is transferred to the bottom of the shift electrode 20 through the potential well formed in the substrate 11 under each electrode. A CCD register 30 for reading is provided adjacent to the shift electrode 20. This CCD register 30 has a control terminal 3
A plurality of transfer electrodes 35 to which any one of the four-phase clock pulses applied to 1 to 34 is supplied, and the transfer is performed from below the shift electrode 20 according to the application method of the four-phase clock pulses φa to φd. The generated signal charges are sequentially transferred in the X ₁ direction or the X ₂ direction in the figure. This CCD register 3
Charge detectors 36 and 37 that detect signal charges and convert them into electric signals such as voltage are provided at the front and rear ends of 0. The electric signals converted by the charge detectors 36 and 37 are provided. Is output from the output terminals 38 and 39. The barrier electrode 14, the storage electrode 15, the storage electrodes 16 to 19, the shift electrode 20 and the transfer electrode 35 in the CCD register 30 are
As shown in FIG. 3, the gate electrode is embedded in the silicon oxide film 41 provided on the substrate 11. In the surface region of the substrate 11 corresponding to the four storage electrodes 16 to 19, the high concentration p ⁺ type region 46 to only the n ⁺ type region 13 side is formed.
49 are provided. Further, the silicon oxide film 41
An optical shield film 50 made of aluminum or the like is provided on the entire surface, leaving only the position corresponding to the n ⁺ type region 13 above. Although not shown, the potential well formed by the barrier electrode 14, the storage electrode 15, the storage electrodes 16 to 19 and the shift electrode 20 is provided in the substrate 11 by means of a high-concentration region or the like. It is separated for each.

The unit sensor chip having the structure shown in FIG. 2 and FIG.
When the image sensor shown in FIG. 1 is configured by using individual units, the distance between the photosensitive portions of the unit sensor chips 2 and 4 is
It is set to three times the length of the photosensitive pixel indicated by the dimension L in FIG.

Further, in FIG. 1, a constant DC voltage V having different values is applied to the barrier electrodes 14 of the two unit sensor chips 2 and 4 and the control terminals 21 and 22 of the storage electrodes 15 arranged in one row.
₁ , V ₂ are applied, and four-phase clock pulses φm _{1 to} φm ₄ are sequentially applied from the electrode 19 to the control terminals 23 to 26 of the four storage electrodes 16 to 19 as shown in the timing chart of FIG. The control terminal 27 of the shift electrode 20 has a fourth
A shift pulse φ _SH as shown in the figure is applied. Also,
In the two unit sensor chips 2 and 4, four-phase clock pulses φa to φd are applied to the control terminals 31 to 34 so that the signal charges are transferred in the CCD register 30 in the X ₁ direction in FIG. It In FIG. 1, the barrier electrodes 1 of the two unit sensor chips 3 and 5 arranged in the other row.
4, the control terminals 21 and 22 of the storage electrode 15 have the same constant DC voltage V as the two unit sensor chips 2 and 4 on the one side.
₁ , V ₂ are applied, and four-phase clock pulses φm _{1 to} φm 4 as shown in FIG. ₄ are sequentially applied from the electrode 16 to the control terminals 23 to 26 of the four storage electrodes 16 to 19 to shift electrodes. A shift pulse φ _SH as shown in FIG. 4 is also applied to the control terminal 27 of 20. In the two unit sensor chips 3 and 5, four-phase clock pulses φa to φd are supplied to the control terminals 31 to 34 so that the signal charges are transferred in the CCD register 30 in the X ₂ direction in FIG. Is applied. Here, the value of the DC voltages V ₁ is set smaller than the low level voltage V _L of the clock pulse φm ₁ ~φm ₄ in FIG. 4, the value of the DC voltage V ₂ is low level φm ₁ ~φm ₄ It is set higher than the voltage V _L.

Next, the operation of the apparatus configured as described above will be described. First, the manuscript whose optical pattern is to be read is indicated by Y in FIG.
Sequentially move in the direction. At this time, a signal charge corresponding to the amount of light at that time is generated in each photosensitive portion 1 of each of the unit sensor chips 2 to 5.

FIGS. 5A to 5C are diagrams showing potential states of the two unit sensor chips 2 and 4 in FIG. 1 at respective times. FIG. 5 (a) is at time t ₁ in FIG. At this time t ₁ , the signal charge generated under the n ⁺ type region 13 exceeds the constant potential barrier 61 generated under the barrier electrode 15 and the well 62 of constant potential generated under the storage electrode 15. The signal charge Q ₄ flowing into the inside of the well 62 corresponds to the optical signal on the current scanning line.
Accumulated within. At this time, the clock pulse φm ₁ ~
φm ₄ is set to a voltage _VL larger than 0, and potential wells 63 to 66 are formed below the storage electrodes 16 to 19. Further, since p ⁺ type regions 46 to 49 are provided in the surface region of the substrate 11 below the memory electrodes 16 to 19,
Potential barriers (potential barriers) 67 to 70 are formed at positions corresponding to these regions 46 to 49, and a signal charge Q ₃ before one scanning line, a signal charge Q ₂ before two scanning lines and a signal before three scanning lines are formed. The charge Q ₁ is the potential barrier 67.
~ 63 of potential wells 63-6 separated by
5 is stored in advance.

FIG. 5 (b) is at time t _{1 in} FIG. 4 when the clock pulse φm ₁ is set to the high voltage V _H. This time t
_{In 2} , the storage electrode 19 is set to a high voltage, so that the potential well 66 and the barrier 70 under this electrode move as a whole downward in the drawing. Then, the signal charge Q ₁ which has been stored in the adjacent potential well 65 until now flows into the potential well 66 below the electrode 19. Less than,
When the clock pulses φm ₂ , φm ₃ , and φm ₄ are sequentially set to the high voltage V _H , the signal charges Q _{2 to} Q ₄ accumulated in the potential wells 64 to 62 are stored in the adjacent potential wells 65 to 63. Transferred to.

FIG. 5 (c) shows the time t _{3 in} FIG. 4 in which the clock pulse φm ₄ is set to the high voltage V _H and then set to the low voltage V _L again. Than when the time t ₃ in the t _1, each of the signal charges Q ₄ to Q ₁ is moved to the right by the well of the one minute potential. That is, in these two unit sensor chips 2 and 4, each signal charge moves by one potential well for each cycle of the clock pulses φm _{1 to} φm ₄ .

After that, when the shift pulse φ _SH is set to the high voltage V _H at time t ₄ in FIG. ₄ , the potential under the shift electrode 20 ′ becomes high, and the potential well 66 under the memory electrode 19 has been stored up to now. The accumulated signal charge Q ₁ passes under the shift electrode and moves under the transfer electrode 35 of the CCD register 30. Such movement of the signal charges occurs in parallel with the signal charges obtained in all the photosensitive pixels 12 in the photosensitive section 1. The signal charges that have moved below each transfer electrode 35 are
Sequentially transferred in the direction of X ₁ in the CCD register 30,
The electric charge detection unit 37 converts the electric signal and outputs the electric signal from the output terminal 39. That is, the unit sensor chips 2, 4
The electrical signal from the device is delayed by three scanning lines.

By the way, since the distance between the photosensitive portions of the unit sensor chips 2 and 3 is set to be three times the length L of the photosensitive pixel as described above, the unit sensor chips 2 or 4 are read at a certain cycle. When the signal charge is accumulated in the potential well 66 below the storage electrode 19, the scanning line position of the document corresponding to the signal charge is set to the unit sensor chips 3, 5
To reach the photosensitive unit 1. At this time, in the photosensitive portion 1 of each of the unit sensor chips 3 and 5, a signal charge corresponding to the amount of light at that time is generated.

6 (a) and 6 (b) show the above-mentioned two unit sensor chips 3, 5
It is a figure which shows the potential state in each time of. FIG. 6 (a) is at time t ₁ in FIG. At this time t _1, the two unit sensor chips 2,
As in the case of No. 4, the signal charge generated under the n ⁺ type region 13 exceeds the constant potential barrier 61 generated under the barrier electrode 14, and the well 62 of the constant potential generated under the storage electrode 15. The signal charge Q ₁ ′ flowing into the well 62 and corresponding to the optical signal on the current scanning line is accumulated in the well 62. Thereafter, the four-phase clock pulses φm _{1 to} φm ₄ are sequentially set to the high voltage V _H , so that the memory electrodes 16 to 19
Since a well and a barrier having a potential equivalent to that generated under the storage electrode 19 in FIG. 5 (b) are sequentially formed therebelow, the sixth well corresponding to the time t ₃ in FIG. 4 is formed.
In FIG. 6B, the signal charge Q ₁ ′ is accumulated in the potential well 66 below the memory electrode 19 via three potential wells. That is, in these two unit sensor chips 3 and 5, the signal charges obtained in each photosensitive pixel move to below the storage electrode 19 during one cycle period of the clock pulses φm _{1 to} φm ₄ . After that, when the shift pulse φ _SH is set to the high voltage V _H at time t ₄ in FIG. ₄ , the potential under the shift electrode 20 becomes high, and the potential well 66 under the memory electrode 19 has accumulated up to now. The stored signal charge Q ₁ ′ passes under the shift electrode and moves under the transfer electrode 35 of the CCD register 30. Such movement of the signal charges occurs in parallel with the signal charges obtained in all the photosensitive pixels 12 in the photosensitive section 1. The signal charges that have moved below each transfer electrode 35 are
After that, the charges are sequentially transferred in the direction of X ₂ in the CCD register 30, converted into an electric signal by the charge detection unit 36, and output from the output terminal 38. That is, the electric signals from the unit sensor chips 3 and 5 are output without delay for one scanning line.

By the way, in the two unit sensor chips 3 and 5, n ⁺
In one cycle period in which the signal charges generated under the mold region 13 are moved and accumulated under the storage electrode 19, the signal charges accumulated under the storage electrode 18 in the other two unit sensor chips 2 and 4 are stored in the storage electrode 19. Moved down 19 and accumulated. Then, when the shift pulse φ _SH is set to the high voltage V _H , the symbol charge under each storage electrode 19 of each of the two unit sensor chips 3, 5 and 2, 4 is transferred to each CCD register 30. Therefore, the electric signal output from the two unit sensor chips 3 and 5 and the electric signal output from the two unit sensor chips 2 and 4 correspond to the optical signal on the same scanning line of the document. Therefore, after this, four unit sensor chips 2 arranged as shown in FIG.
Electrical signals corresponding to the optical pattern on one scanning line of the original are output from the output terminals 5 to 5 through the output terminals 39 or 38.

As described above, according to the above-described embodiment, it is possible to obtain a signal corresponding to the optical pattern without providing an external storage circuit. Further, comparing the noise components due to the dark currents generated in the unit sensor chips 2, 4 and 3, 5, the noise components generated in the unit sensor chips 2, 4 indicate that the time required for one scan is Tint, the photosensitive pixel 12, The dark current generated under the barrier electrode 14 and under the storage electrode 15 is I ₁ , and the storage electrodes 16 to ₁
Assuming that the dark current generated under 9 is I _{2 to} I ₅ , Tint (I ₁
+ I ₂ + I ₃ + I ₄ + I ₅ ). On the other hand, in the unit sensor chips 3 and 5, all the storage electrodes 16
Since the dark current under -19 is read, the noise component generated is Tint (I ₁ + I ₂ + I ₃ + I ₄ + I ₅ ). That is, the noise components due to the dark current generated in the unit sensor chips 2, 4 and 3, 5 are the same. Therefore, the output signals of the sensor chips 2 to 5 are always balanced including the noise component, which is advantageous for the subsequent signal processing. Further, according to the above-described embodiment, each of the unit sensor chips 2 to 5 can have the same configuration,
Since it is not necessary to prepare two different types of chips, the manufacturing price can be reduced. Further, since the same clock pulse is used to control the memory electrodes 16 to 19 in the unit sensor chips 2, 4 and 3, 5, the chips 2, 4 and 3, 5 can be driven simply by changing the pulse wiring. This makes it possible to simplify the control.

It is needless to say that the present invention is not limited to the above-mentioned embodiment and various modifications can be made. For example, in the above-described embodiment, the case where four memory electrodes are provided in each unit sensor chip has been described. However, the number of delay scanning lines required depends on the distance between the photosensitive portions of the two unit sensor chips in the Y direction. It is desirable to select at least (m + 1) for m.

Further, in the above embodiment, the potential barriers 67 to 70 for separating the potential wells 63 to 66 formed in the memory electrodes 16 to 19 are provided in the surface region of the substrate 11 by n ^+.
P ⁺ type regions 46 to 49 provided only on the side of the type region 13
However, this may be realized by changing the film thickness of the silicon oxide film 41 or providing an n-type region in a region other than the potential barriers 67 to 70 in the substrate 11. Further, although the case where each of the memory electrodes 16 to 19 is a single electrode has been described, different electrodes may be connected to each other to have a structure similar to that of a so-called two-phase CCD electrode. In addition, the memory electrodes 16 to 19
The bottom and CCD register 30 may provide a buried channel. Furthermore, the case where the CCD register 30 is provided with the charge detecting portions 36 and 37 at both end portions has been described, but this may be provided only on one side. However, in this case, it is necessary to prepare two types of unit sensor chips having charge detection units on opposite sides.

〔The invention's effect〕

As described above, according to the present invention, it is not necessary to provide a memory circuit externally, and it is possible to reduce the manufacturing cost by using only one type of unit sensor chip, and the control can be easily performed. It is possible to provide a solid-state image sensor capable of performing the above.

[Brief description of drawings]

1 is a plan view of a general contact type CCD linear image sensor, FIG. 2 is a plan view showing one unit sensor chip according to the present invention, and FIG. 3 is a view taken along the line AA 'in FIG. A sectional view, FIG. 4 is a timing chart showing control signals used in the unit sensor chip of FIG. 2, FIG. 5 and FIG.
Each of the figures is a potential state diagram for explaining the operation of the unit sensor chip shown in FIG. 1 ... Photosensitive part, 2-5 ... Unit sensor chip, 11 ... P-type silicon substrate, 12 ... Photosensitive pixel, 13 ... N ⁺ type area, 14 ...
Barrier electrode, 15 ... Storage electrode, 16-19 ... Storage electrode,
20 ... Shift electrode, 30 ... CCD register, 36, 37 ...
Charge detection unit, 46 to 49 ... P ⁺ region.

Claims (2)

[Claims] 1. A photosensitive portion formed by arranging a plurality of photosensitive pixels linearly, and a signal charge generated in a predetermined scanning period in the photosensitive portion is sequentially transferred in a predetermined direction to detect a charge provided at an end portion. A transfer register for extracting pixel signals as a pixel signal by at least one unit, and at least m charge storage gates provided between the photosensitive unit and the transfer register and capable of accumulating signal charges of at least m scanning line segments (m is a positive integer). A charge storage unit having electrodes, in which a control pulse is applied to these charge storage gate electrodes to transfer or store the signal charges of the photosensitive unit in parallel, so that the storage time can be selected from 0 to m times the scanning period. And the unit sensor chips are respectively composed of two or more unit sensor chips in a zigzag pattern along the X direction, and a Y direction intersecting the X direction of the photosensitive portions of the unit sensor chips of the one row and the other row. Is m times the length of the photosensitive pixel in the Y direction, and the photosensitive portions of the unit sensor chips of the one row and the other row are arranged in parallel so as to be continuous in the X direction, and A control pulse is applied to the charge storage gate electrode so that the storage time of the charge storage unit is 0 times the scanning period, and the charge is stored so that the storage time of the charge storage unit in the other column is m times the scanning period. By applying a control pulse to the memory gate electrode, image signals on the same scanning line for the optical pattern moving in the Y direction within the same scanning period can be obtained from the two rows of unit sensor chips. Solid-state image sensor. 2. The transfer register is provided with the charge detectors at both ends thereof in the charge transfer direction, and the charge transfer direction is determined according to the application order of clock pulses. Item 7. The solid-state image sensor according to item.