JPH063993B2 - Inverter control device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an inverter control device for controlling an output voltage of an inverter so as to keep the output voltage constant without being affected by fluctuations in the power supply voltage.

[Prior art]

Inverters that perform pulse width modulation by comparing the output voltage with a carrier and a sine wave, in order to make the output correspond to a sine wave correctly even if the power supply voltage fluctuates, the pulse width of the output voltage depends on the fluctuation. Need to be corrected.

Without such a correction, the output voltage of the inverter will also decrease if the power supply voltage decreases. Even if such an output voltage is applied to the induction motor, a sufficient torque cannot be obtained. On the contrary, when the power supply voltage is too high, it is overexcited. Further, since the output voltage fluctuates due to the fluctuation of the power supply voltage, vibration and noise of the induction motor increase, and the stability deteriorates.

[Outline of Invention]

The present invention has been made to solve the above problems, and detects fluctuations in the power supply voltage of an inverter, frequency-converts the clock in accordance with this fluctuation, and supplies a pulse to the inverter by the modulated clock obtained thereby. It is an object of the present invention to provide an inverter control device capable of maintaining an output voltage value of an inverter at a desired value by correcting a pulse of a width modulation signal.

Example of Invention

An embodiment of the present invention will be described below with reference to the drawings. First
In the figure, 1 is a converter for converting three-phase AC into DC, 2 is a capacitor for smoothing the DC power converted by the converter 1, 3 is an inverter for converting DC power into AC power of variable frequency and variable voltage. Is. Reference numeral 4 is an induction motor driven by the AC power of the inverter 3. Reference numeral 5 is a detection circuit for detecting a DC voltage (power supply voltage) across the capacitor 2, and 6 is an analog-digital (A / D) converter for converting the detection signal DTA output from the detection circuit 5 into a binary voltage data signal DTD. , 7 is a frequency converter (for example, a rate multiplier) that frequency-modulates the clock signal CLK having a reference phase by the voltage data signal DTD from the A / D converter 6 and outputs the clock signal MCLK, and 8 is the reference voltage data REFV. A storage element (for example, a ROM) that stores the value of the reference voltage data REFV, and counts up according to the control signal U / D using the clock signal MCLK of the frequency converter 7 as a control clock. Down to output borrow signal B as a timing signal. Down counter, 1
0 outputs the control signal U / D designating up or down counting to the up / down counter 9 and the load signal LD, thereby inputting the borrow signal B and further inputting the carrier signal 2fc from a circuit not shown, and the inverter 3 To PW
It is a pulse generation circuit that outputs a signal PWM of a pulse train that is M-modulated.

The operation when there is no fluctuation in the DC voltage to the inverter 3 will be described with reference to FIG. The DC voltage input to the inverter 3 is detected by the detection circuit 5, and the detection signal DTA is input to the A / D converter 6 to generate the voltage data signal DTD.
Is converted to. The frequency converter 7 uses the voltage data signal DTD
The clock signal MCLK obtained by frequency-modulating the clock signal MCLK according to the value of is output.

On the other hand, the amplitude signal AMP input to the memory element 8 is a signal indicating the current phase and amplitude of the sine wave signal S as shown in FIG. 2, and the memory element 8 outputs the reference voltage data REFV corresponding to this signal. Output. Up-down counter 9 is the third
As shown in the figure, the carrier signal 2fc (2 of the carrier signal C
A load signal LD input at each time t ₀ , t ₄ ... Of one cycle (having a doubled frequency) is received and the reference voltage data REFV from the storage element 8 is loaded. The up / down counter 9 counts down because the clock signal MCLK of the frequency converter 7 is input as a control clock and the control signal U / D is initially input at a low level. By this counting, the count value of the up / down counter 9 becomes 0 at time t ₁ , and the borrow signal B is output. Therefore, the pulse generating circuit 10 sets the control signal U / D to the high level. Therefore, the up / down counter 9 is switched to the up count. Further, at the time t ₂ when the half cycle of the carrier signal 2fc passes, the control signal U / D is set to low again, and the up / down counter 9 counts down. When the up / down counter 9 outputs the borrow signal B again at time t ₃ , the control signal U /
D becomes high, the up / down counter 9 is switched to the up count, and the up / down counter 9 repeats the above operation. In this way, the positive half cycle of the signal PWM is obtained as shown, and similarly, the negative half cycle is obtained by inverting the waveform of the positive half cycle.

Next, the operation when the DC voltage input to the inverter 3 varies will be described with reference to FIG. Now, assuming that the DC voltage input to the inverter 3 has dropped, the clock signal CLK of the frequency converter 7 is in a state in which some pulses are thinned out in response to the drop in voltage, as shown in the figure. The clock signal CLK is the up / down counter 9
Since it is input as a control clock signal, the count value changes gradually as shown in (b) as compared with (a) when the voltage of the converter 1 does not drop. Therefore, the signal PWM has the waveform shown in (d), and the period during which the voltage of the converter 1 is high becomes longer than that in the case where the voltage of the converter 1 is normal (c). Inverter 3 is corrected by the signal PWM by increasing the period during which it is high as shown in (f) compared with the normal case (e) so that the average voltage value of the AC output becomes a predetermined value. That is, the output phase voltage is controlled so that the areas of the shaded portions in the figure are always constant with respect to the voltage change of the converter 1.

FIG. 5 is a waveform diagram showing an output line voltage waveform of the inverter 3 for one cycle. As shown in the figure, the fundamental wave components of the waveform (a) before the change and the waveform (b) after the change are controlled to be equal to the waveform (c).

In the above embodiment, as the power supply voltage value, the case of detecting the DC voltage value of the inverter is described, but the effective value of the input AC voltage of the inverter, the average value by the predetermined time constant,
You may make it detect a peak value etc. In the above embodiment, the case where the up / down counter is used as the counter has been described, but a down counter may be used as shown in FIG. In FIG. 6, (a) shows the count value of the down counter, and (b) shows the signal PWM output from the pulse generation circuit 10.

Further, in the above embodiment, the one using the A / D converter 6 and the frequency converter 7 is shown, but instead of the voltage
A frequency converter may be used.

〔The invention's effect〕

As described above, according to the present invention, the fluctuation of the power supply voltage of the inverter is detected, the clock is frequency-modulated according to this fluctuation, and the pulse of the pulse width modulation signal supplied to the inverter is corrected by the modulation clock obtained by this. With this configuration, fluctuations in the output voltage of the inverter due to fluctuations in the power supply voltage can be corrected with high accuracy, and as a result, the motor can be driven so that optimum output can be obtained, and vibrations It is effective in reducing noise and noise. Further, since the circuit is composed of digital elements, there is an effect that the circuit can be made small and low in cost, without the need for adjustment as in the case of being composed of analog elements.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an inverter control device according to the present invention, and FIGS. 2, 3, 4, 5, and 6 are waveform diagrams showing the operation of the inverter control device according to the present invention. Is. 1 ... Converter, 2 ... Capacitor, 3 ... Inverter, 5
... Detection circuit, 6 ... A / D converter, 7 ... Frequency converter, 8 ... Storage element, 9 ... Up-down counter, 10 ...
Pulse generator circuit. In the drawings, the same reference numerals indicate the same parts.

Claims (3)

[Claims] 1. A converter that outputs a modulated clock signal by controlling the number of pulses of a reference clock signal according to the level of a power supply voltage of an inverter that converts electric power into AC power of variable frequency and variable voltage; A storage element that stores the reference voltage value data of the output voltage for each amplitude and a predetermined phase, and the reference voltage value data read from the storage element is loaded by a load signal and counted by the modulation clock signal of the converter. , Timing with a predetermined count value
A pulse generating count, a load signal at a predetermined phase of the carrier, and a control signal for controlling the count of the counter by the timing pulse, and having a pulse width modulated waveform. An inverter control device comprising: a pulse generation circuit that generates a pulse train signal that controls an inverter. 2. The inverter control device according to claim 1, wherein the inverter detects an effective value of an AC voltage input to the inverter. 3. The inverter control device according to claim 1, wherein the inverter detects a DC voltage value input to the inverter.