JPH0640179B2 - Semiconductor optical switch - Google Patents
Semiconductor optical switchInfo
- Publication number
- JPH0640179B2 JPH0640179B2 JP13291287A JP13291287A JPH0640179B2 JP H0640179 B2 JPH0640179 B2 JP H0640179B2 JP 13291287 A JP13291287 A JP 13291287A JP 13291287 A JP13291287 A JP 13291287A JP H0640179 B2 JPH0640179 B2 JP H0640179B2
- Authority
- JP
- Japan
- Prior art keywords
- quantum well
- semiconductor
- type
- optical switch
- well thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Photo Coupler, Interrupter, Optical-To-Optical Conversion Devices (AREA)
Description
【発明の詳細な説明】 <産業上の利用分野> 本発明は光通信装置や情報処理装置等で利用される光ス
イッチに関する。The present invention relates to an optical switch used in an optical communication device, an information processing device, or the like.
<従来の技術とその問題点> 従来のこの種の光スイッチでは半導体を用いたフランツ
ケルディシュ効果を用いたデバイスが小型でありすぐれ
ている。フランツケルディシュ効果は半導体に電界を加
えたときに吸収端波長が長波長にシフトする効果であ
る。この半導体として、禁制帯幅の異なるそれぞれ500
Å以下の層を交互に積層した多重量子井戸構造を用いる
導波型光スイッチが考えられている(昭和60年電子通
信学会総合全国大会S3−4)。この様な導波型光スイ
ッチにおいては、スイッチング速度はデバイスの静電容
量とシリーズ抵抗の積からなるCR時定数で主に決まっ
ている。素子の静電容量は、PN接合の空乏層容量で決
まっておりこれはPN接合面積に比例している。第2図
に示す様な従来の素子では、スイッチ動作を行なうスト
ライプが10×500μm2程度と大きく、又ボンディング
用に別に100×100μm2程度の面積を必要とするか
ら比較的大きなPN接合面積を必要としていた。このた
めデバイスの静電容量は3〜5pFと比較的大きく、こ
の容量とシリーズ抵抗の50Ωで決まるCR時定数(〜
300psec)で動作速度が制限されていた。この動作
速度の一層の改善を図るには静電容量の低減すなわちP
N接合面積の低減を図る必要がある。しかしながら従来
の構造の光スイッチでは、ボンディングパッドの面積が
必要であることや、又ストライプ幅を現状よりも狭くす
るとエッチングによる側面の乱れによる信号光の散乱の
増加を招いてしまう等の事情があって、これ以上のPN
接合面積の低減は困難であった。<Conventional Technology and Its Problems> In the conventional optical switch of this type, a device using the Franz-Keldysh effect using a semiconductor is small and excellent. The Franz-Keldysh effect is an effect in which the absorption edge wavelength shifts to a longer wavelength when an electric field is applied to the semiconductor. As for this semiconductor, each forbidden band width is 500
Å A waveguide type optical switch using a multi-quantum well structure in which the following layers are alternately laminated is considered (1985, National Institute of Electronics and Communication Engineers general conference S3-4). In such a waveguide type optical switch, the switching speed is mainly determined by the CR time constant which is the product of the capacitance of the device and the series resistance. The capacitance of the device is determined by the depletion layer capacitance of the PN junction, which is proportional to the PN junction area. In the conventional device as shown in FIG. 2, the stripe for performing the switch operation is as large as about 10 × 500 μm 2 , and another area of about 100 × 100 μm 2 is required for bonding, so that a relatively large PN junction area is required. I needed it. Therefore, the capacitance of the device is relatively large, 3 to 5 pF, and the CR time constant (~) determined by this capacitance and the series resistance of 50Ω.
The operation speed was limited at 300 psec). To further improve the operation speed, the capacitance is reduced, that is, P
It is necessary to reduce the N-junction area. However, in the optical switch of the conventional structure, there is a situation that the area of the bonding pad is required, and that if the stripe width is made narrower than the current state, the scattering of the signal light is increased due to the disturbance of the side surface due to the etching. And no more PN
It was difficult to reduce the bonding area.
そこで本発明の目的は、上述の欠点を除去し、PN接合
面積の低減が容易であって、静電容量が小さく動作速度
の速い半導体光スイッチを提供することにある。SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a semiconductor optical switch that eliminates the above-mentioned drawbacks, can easily reduce the PN junction area, has a small capacitance, and has a high operating speed.
<問題点を解決するための手段> 前述の問題点を解決するために本発明の提供する半導体
光スイッチは、太さが電子の平均自由行程以下の(≦10
00Å)半導体からなる量子井戸細線と、この量子井戸細
線を囲みこの量子井戸細線よりも禁制帯幅の大きな半導
体バリアと、この半導体バリアと前記量子井戸細線から
なる量子井戸細線領域の2つの側面にそれぞれ形成され
たp型半導体領域及びn型半導体領域を備えることを特
徴とする。<Means for Solving Problems> In order to solve the above-mentioned problems, the semiconductor optical switch provided by the present invention has a thickness of not more than the mean free path of electrons (≦ 10
00 Å) A quantum well thin wire made of a semiconductor, a semiconductor barrier that surrounds the quantum well thin wire and has a bandgap larger than that of the quantum well thin wire, and a quantum well thin wire region composed of the semiconductor barrier and the quantum well thin wire on two sides. A p-type semiconductor region and an n-type semiconductor region formed respectively are provided.
<実施例> 次に図面を参照して本発明を詳しく説明する。第1図は
本発明の一実施例の半導体光スイッチの斜視図である。
図中1は半絶縁性基板(GaAs)、2は第1クラッド層(ア
ンドープ高抵抗 0.2≦Xc1≦0.8,厚さ0.5〜3μm、典型的にはXc1
=0.4,厚さ〜1.5μm)、3は量子井戸細線領域(ア
ンドープ高抵抗,厚さ0.1〜1μm,幅0.5〜3μm、
典型的には厚さ0.5μm,幅1μm)、3aは量子井戸
細線(厚さ40〜200Å,幅40〜1000Å,AlxwGa1-XwA
s,0≦Xw<Xb、典型的には厚さ100Å,幅100〜500
Å,Xw=0)、3bはバリア(幅40〜1000Å、Alxb
Ga1-xbAs,0.1≦Xb<Xc1,Xc2、典型的には幅100
〜500Å,Xb=0.2)、4は第2クラッド層(アンド
ープ高抵抗 0≦Xc2≦0.8,厚さ0.5〜3μm、典型的にはXc2=
0.4,厚さ〜1.5μm)、5aはp型キャップ層(p−Ga
As)、5bはn型キャップ層(n−GaAs)、6はp型領
域、7はn型領域、8はp型電極、9はn型電極であ
る。<Example> Next, the present invention will be described in detail with reference to the drawings. FIG. 1 is a perspective view of a semiconductor optical switch according to an embodiment of the present invention.
In the figure, 1 is a semi-insulating substrate (GaAs), 2 is the first cladding layer (undoped high resistance) 0.2 ≦ X c1 ≦ 0.8, thickness 0.5 to 3 μm, typically X c1
= 0.4, thickness to 1.5 μm), 3 is a quantum well thin wire region (undoped high resistance, thickness 0.1 to 1 μm, width 0.5 to 3 μm,
Typically, the thickness is 0.5 μm and the width is 1 μm. 3a is a quantum well thin wire (thickness 40 to 200 Å, width 40 to 1000 Å, Al xw Ga 1-Xw A
s, 0 ≦ Xw <Xb, typically thickness 100Å, width 100-500
Å, X w = 0), 3b is a barrier (width 40 to 1000Å, Al xb
Ga 1-xb As, 0.1 ≦ Xb <X c1 , X c2 , typically width 100
~ 500Å, Xb = 0.2), 4 is the second cladding layer (undoped high resistance) 0 ≦ X c2 ≦ 0.8, thickness 0.5 to 3 μm, typically X c2 =
0.4, thickness ~ 1.5 μm), 5a is a p-type cap layer (p-Ga
As), 5b is an n-type cap layer (n-GaAs), 6 is a p-type region, 7 is an n-type region, 8 is a p-type electrode, and 9 is an n-type electrode.
本実施例ではp型領域6とn型領域7とは半導体膜の同
一平面内にあるから、これらの間に電圧を加えると電界
は半導体膜面と平行な方向に印加される。このとき本実
施例では、量子井戸細線3aを備えているから横方向にも
キャリア閉じ込めがされており、横方向に電界印加時に
量子準位の低エネルギーシフト側への移動が起こって良
好なスイッチング特性が得られた。In this embodiment, the p-type region 6 and the n-type region 7 are in the same plane of the semiconductor film, so that when a voltage is applied between them, the electric field is applied in the direction parallel to the semiconductor film surface. At this time, in this embodiment, since the quantum well thin wire 3a is provided, carriers are confined in the lateral direction as well, and when the electric field is applied in the lateral direction, the quantum level shifts to the low energy shift side and good switching occurs. The characteristics were obtained.
本実施例のPN接合面積は全体厚みと素子長で決まる。
厚さに関しては分子線エピタキシー方法等の高度なエピ
タキシー技術によって高精度に制御出来る。このため厚
さはデバイスに最低必要な厚さ2〜3μmに抑えること
が可能でしかも界面が平坦であるため光の散乱も小さ
い。又、本実施例ではp型領域6とn型領域7は半絶縁
性基板1の上に形成されているためにこれらの面積を大
きくしても静電容量が増加しないから容易にボンディン
グをすることが出来る。本実施例での静電容量はこれら
の効果によって容量が0.5pF以下となって100psec以
下の動作速度が実現した。The PN junction area of this embodiment is determined by the total thickness and the element length.
The thickness can be controlled with high accuracy by advanced epitaxy technology such as molecular beam epitaxy method. Therefore, the thickness can be suppressed to the minimum thickness of 2 to 3 μm required for the device, and since the interface is flat, light scattering is small. Further, in this embodiment, since the p-type region 6 and the n-type region 7 are formed on the semi-insulating substrate 1, the capacitance does not increase even if these areas are increased, so that the bonding is easily performed. You can Due to these effects, the electrostatic capacitance in this embodiment is 0.5 pF or less, and the operating speed of 100 psec or less is realized.
次に本実施例の半導体光スイッチの製作方法の一例を第
3図を用いて説明する。まず第1回目の結晶成長におい
て第3図(a)に示す様に半絶縁性基板1上に第1クラッ
ド層2、多重量子井戸10を成長する。次に第3図(b)
に示す様にフォーカストイオンビーム法等を用いてGa
をストライプ状にイオン注入した後アニールすることに
よってGaが注入された量子井戸を無秩序化して量子井
戸細線領域3を形成する。次に第3図(c)に示す様に第
2回目の結晶成長において第2クラッド層4及びキャッ
プ層5を形成する。その後第3図(d)に示す様に、Si
の選択拡散を行なってn型領域7を形成し次にZnの選
択拡散を行なってp型領域6を形成する。この拡散時に
p型領域6及びn型領域7に含まれる量子井戸細線領域
は無秩序化されて均一な半導体となる。最後にp型電極
8、n型電極9を形成しストライプ上のキャップ層5を
除去して完成する。Next, an example of a method of manufacturing the semiconductor optical switch of this embodiment will be described with reference to FIG. First, in the first crystal growth, as shown in FIG. 3A, the first cladding layer 2 and the multiple quantum well 10 are grown on the semi-insulating substrate 1. Next, Fig. 3 (b)
Ga as shown in Fig.
Are ion-implanted in stripes and then annealed to disorder the Ga-implanted quantum well to form the quantum well thin-line region 3. Next, as shown in FIG. 3C, the second cladding layer 4 and the cap layer 5 are formed in the second crystal growth. After that, as shown in FIG. 3 (d), Si
Are selectively diffused to form an n-type region 7, and then Zn is selectively diffused to form a p-type region 6. During this diffusion, the quantum well wire regions included in the p-type region 6 and the n-type region 7 are disordered and become a uniform semiconductor. Finally, the p-type electrode 8 and the n-type electrode 9 are formed, and the cap layer 5 on the stripe is removed to complete the process.
以上の実施例においては材料としてGaAs/AlGaAsを用い
たが、これに限らず他の材料たとえばInGaAsP/InP,In
GaAlAs/InP等を用いても本発明は実施できる。Although GaAs / AlGaAs is used as the material in the above-mentioned embodiments, the present invention is not limited to this, and other materials such as InGaAsP / InP and In are used.
The present invention can be implemented using GaAlAs / InP or the like.
<発明の効果> 以上に詳しく説明したように、本発明によれば、静電容
量が小さく動作速度が速い半導体光スイッチが得られ
る。<Effects of the Invention> As described in detail above, according to the present invention, a semiconductor optical switch having a small capacitance and a high operation speed can be obtained.
第1図は本発明の一実施例の斜視図、第2図は従来例の
斜視図、第3図は第1図に示した実施例の製作工程を示
す図である。 図中、1……半絶縁性基板、2……第1クラッド層、3
……量子井戸細線領域、3a……量子井戸細線、3b…
…バリア、4……第2クラッド層、5……キャップ層、
5a……p型キャップ層、5b……n型キャップ層、6
……p型領域、7……n型領域、8……p型電極、9…
…n型電極、10……多重量子井戸、20……n型GaAs
基板、21……n型クラッド層、22……多重量子井
戸、23……p型クラッド層、24……キャップ層、2
5……p型電極、26……n型電極、である。FIG. 1 is a perspective view of an embodiment of the present invention, FIG. 2 is a perspective view of a conventional example, and FIG. 3 is a view showing a manufacturing process of the embodiment shown in FIG. In the figure, 1 ... Semi-insulating substrate, 2 ... First cladding layer, 3
・ ・ ・ Quantum well wire region 3a ・ ・ ・ Quantum well wire 3b
… Barrier, 4 …… Second clad layer, 5 …… Cap layer,
5a ... p-type cap layer, 5b ... n-type cap layer, 6
... p-type region, 7 ... n-type region, 8 ... p-type electrode, 9 ...
... n-type electrode, 10 ... multiple quantum well, 20 ... n-type GaAs
Substrate, 21 ... N-type cladding layer, 22 ... Multiple quantum well, 23 ... P-type cladding layer, 24 ... Cap layer, 2
5 ... P-type electrode, 26 ... N-type electrode.
Claims (1)
らなる量子井戸細線と、この量子井戸細線を囲みこの量
子井戸細線よりも禁制帯幅の大きな半導体バリアと、こ
の半導体バリアと前記量子井戸細線からなる量子井戸細
線領域の2つの側面にそれぞれ形成されたp型半導体領
域及びn型半導体領域を備えることを特徴とする半導体
光スイッチ。1. A quantum well thin wire made of a semiconductor whose thickness is equal to or less than the mean free path of electrons, a semiconductor barrier surrounding this quantum well thin wire and having a forbidden band width larger than this quantum well thin wire, this semiconductor barrier and the quantum. 1. A semiconductor optical switch comprising a p-type semiconductor region and an n-type semiconductor region formed on two side surfaces of a quantum well thin line region formed of a well thin line, respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13291287A JPH0640179B2 (en) | 1987-05-27 | 1987-05-27 | Semiconductor optical switch |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13291287A JPH0640179B2 (en) | 1987-05-27 | 1987-05-27 | Semiconductor optical switch |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63294519A JPS63294519A (en) | 1988-12-01 |
| JPH0640179B2 true JPH0640179B2 (en) | 1994-05-25 |
Family
ID=15092427
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13291287A Expired - Lifetime JPH0640179B2 (en) | 1987-05-27 | 1987-05-27 | Semiconductor optical switch |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0640179B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5467953B2 (en) * | 2010-07-07 | 2014-04-09 | 日本オクラロ株式会社 | Semiconductor optical device, optical transmission module, optical transmission / reception module, and optical transmission device |
-
1987
- 1987-05-27 JP JP13291287A patent/JPH0640179B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63294519A (en) | 1988-12-01 |
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