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JPH0640559B2 - Method for forming transfer bump substrate - Google Patents
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JPH0640559B2 - Method for forming transfer bump substrate - Google Patents

Method for forming transfer bump substrate

Info

Publication number
JPH0640559B2
JPH0640559B2 JP60186917A JP18691785A JPH0640559B2 JP H0640559 B2 JPH0640559 B2 JP H0640559B2 JP 60186917 A JP60186917 A JP 60186917A JP 18691785 A JP18691785 A JP 18691785A JP H0640559 B2 JPH0640559 B2 JP H0640559B2
Authority
JP
Japan
Prior art keywords
substrate
transfer bump
electrode
bump
bump substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60186917A
Other languages
Japanese (ja)
Other versions
JPS6247139A (en
Inventor
喜文 北山
幸男 前田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP60186917A priority Critical patent/JPH0640559B2/en
Publication of JPS6247139A publication Critical patent/JPS6247139A/en
Publication of JPH0640559B2 publication Critical patent/JPH0640559B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00Subject matter not provided for in other groups of this subclass

Landscapes

  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、バンプを介して半導体素子を接合するフィル
ムキャリア方式の半導体組立てに用いる転写バンプ基板
の形成方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a transfer bump substrate used for film carrier type semiconductor assembly in which semiconductor elements are bonded via bumps.

従来の技術 従来の転写バンプ基板上に形成されたバンプをインナリ
ードに転写して、バンプを半導体素子の電極に熱圧着で
接合する方法は次のとおりである。すなわち、まず第3
図に示すように、ガラス基板のような絶縁基板1の上全
面にPt,Pd,Auなどの電極膜2を形成したあと、SiO2など
の絶縁膜3を形成して、絶縁膜3に所定のパターン4を
エッチング法等によって形成して転写バンプ基板を得
る。次いでパターン4の部分に第4図aに示すような金
製のバンプ5をメッキなどで形成した後、前記転写バン
プ基板を第1のテーブル6上にセッティングして、フィ
ルムキャリアのインナリード7と金製のバンプ5を位置
合せし、その後にボンディングツール8でインナリード
7と金製のバンプ5を接合して、金製のバンプ5のみを
電極膜2より分離させる。その後第4図bに示すように
第2のテーブル9上に半導体素子10をセッティングし
て、金製のバンプ5と半導体素子10のA電極11と
を位置合せしてボンディングツール8で金製のバンプ5
と半導体素子10のA電極11とを接合させて作業が
完了する。
2. Description of the Related Art A conventional method of transferring a bump formed on a transfer bump substrate to an inner lead and bonding the bump to an electrode of a semiconductor element by thermocompression bonding is as follows. That is, first of all
As shown in the figure, after forming an electrode film 2 of Pt, Pd, Au or the like on the entire surface of an insulating substrate 1 such as a glass substrate, an insulating film 3 of SiO 2 or the like is formed, and the insulating film 3 is provided with a predetermined thickness. Pattern 4 is formed by an etching method or the like to obtain a transfer bump substrate. Then, gold bumps 5 as shown in FIG. 4A are formed on the pattern 4 by plating or the like, and then the transfer bump substrate is set on the first table 6 to form the inner leads 7 of the film carrier. The gold bumps 5 are aligned, and then the inner leads 7 and the gold bumps 5 are joined by the bonding tool 8 to separate only the gold bumps 5 from the electrode film 2. After that, as shown in FIG. 4B, the semiconductor element 10 is set on the second table 9, the bumps 5 made of gold and the A electrodes 11 of the semiconductor element 10 are aligned, and the gold is made by the bonding tool 8. Bump 5
The work is completed by joining the A electrode 11 of the semiconductor element 10 and the A electrode 11 of the semiconductor element 10.

発明が解決しようとする問題点 ところが上記方法では、転写バンプ基板の絶縁膜3を5
000Å程度に形成しなければならないため、ピンホー
ルが多く発生することがあった。その結果として第3図
aに示すように、ピンホール部12に余分なバンプ13
が形成され、これが転写時にボンディングツール8やイ
ンナリード7に付着するという問題があった。
Problems to be Solved by the Invention However, in the above method, the insulating film 3 of the transfer bump substrate is not
Since it had to be formed to about 000Å, many pinholes were sometimes generated. As a result, as shown in FIG.
However, there is a problem in that this adheres to the bonding tool 8 and the inner leads 7 during transfer.

問題点を解決するための手段 上記の問題点を解決するため、本発明の転写バンプ基板
の形成方法は、基板の一面の所定位置に島状の多数の電
極を互いに離乗した状態で形成すると共に、これら電極
を結ぶ配線を形成し、次いで電極を除いた部分を被覆す
る絶縁膜を形成することを特徴とする。
Means for Solving the Problems In order to solve the above problems, the method for forming a transfer bump substrate of the present invention forms a large number of island-shaped electrodes in a predetermined position on one surface of the substrate in a state of being separated from each other. At the same time, a wiring that connects these electrodes is formed, and then an insulating film that covers the portion excluding the electrodes is formed.

作用 本発明によると、転写バンプ基板の基板上に形成された
導電部は、島状の電極と配線からなり、必要最小面積に
抑えられているので、基板全面に電極膜が形成されてい
る従来例に比較して導電面積は激減する。従って絶縁膜
にピンホールが生じても、その部分にメッキ物が形成さ
れる確率は極端に少なくなる。
Action According to the present invention, the conductive portion formed on the substrate of the transfer bump substrate is composed of island-shaped electrodes and wirings and is suppressed to the minimum required area. Therefore, the conventional electrode film is formed on the entire surface of the substrate. The conductive area is drastically reduced compared to the example. Therefore, even if a pinhole occurs in the insulating film, the probability that a plated product will be formed in that portion is extremely reduced.

実施例 本発明の実施例を第1図に基づいて説明する。ガラス基
板20の上にPt,Pd,Auなどの島状電極21とそれら島状
電極21を結ぶ配線22を真空蒸着法等により100Å
から2000Åの厚さに形成したのち、SiO2,SiN等の無
機絶縁膜23をガラス基板の全面に3000Å〜150
00Åの厚さに形成した後、各電極21に対応する位置
にパターン孔24をエッチングによって形成する。
Embodiment An embodiment of the present invention will be described with reference to FIG. On the glass substrate 20, an island-shaped electrode 21 made of Pt, Pd, Au or the like and a wiring 22 connecting the island-shaped electrodes 21 are formed by a vacuum evaporation method or the like to 100 Å
After forming to a thickness of 2000Å from the inorganic insulating film 23 of SiO 2, SiN, or the like on the entire surface of the glass substrate 3000Å~150
After forming to a thickness of 00Å, pattern holes 24 are formed by etching at the positions corresponding to the respective electrodes 21.

このようにして形成された転写バンプ基板は次のように
使用される。すなわち第2図aに示すように、パターン
24部の島状電極21にメッキ法によって金製のバンプ
25を高さ10μm〜35μmに形成したあと、この転
写バンプ基板を第1のテーブル26にセッティングして
フィルムキャリアのインナリード27と金製のバンプ2
5とを位置合せしてボンディングツール28でインナリ
ード27と金製のバンプ25を接合してから、金製のバ
ンプ25のみを島状電極21より分離させ、つぎに第2
図bに示すように第2のテーブル29の上に半導体素子
30をセッティングして、金製のバンプ25と半導体素
子30のA電極31とを位置合せしてボンディングツ
ール28で金製のバンプ25と半導体素子30のA電
極31とを接合させる。
The transfer bump substrate thus formed is used as follows. That is, as shown in FIG. 2A, gold bumps 25 having a height of 10 μm to 35 μm are formed on the island electrodes 21 of the pattern 24 by a plating method, and then the transfer bump substrate is set on the first table 26. Then, the inner lead 27 of the film carrier and the gold bump 2
5, the inner leads 27 and the gold bumps 25 are bonded with the bonding tool 28, and then only the gold bumps 25 are separated from the island-shaped electrode 21.
As shown in FIG. B, the semiconductor element 30 is set on the second table 29, the gold bump 25 and the A electrode 31 of the semiconductor element 30 are aligned, and the bonding tool 28 is used to make the gold bump 25. And the A electrode 31 of the semiconductor element 30 are joined.

なお、島状電極21はPt-ITOのような多層構造になって
いてもよい。
The island electrode 21 may have a multi-layer structure such as Pt-ITO.

発明の効果 本発明によれば、転写バンプ基板の絶縁膜にピンホール
が発生しても、その下地に電極膜がある確率が少なくな
るため、ピンホールによる余分なバンプが形成されるこ
とが少なくなり、これがボンディングツールやインナリ
ードに付着する確率が少なくなる。
EFFECTS OF THE INVENTION According to the present invention, even if a pinhole is generated in the insulating film of the transfer bump substrate, the probability that the electrode film is underneath the pinhole is reduced, so that an extra bump is not formed due to the pinhole. Therefore, the probability that this will adhere to the bonding tool or the inner lead decreases.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の実施例を示し、aはその平面図、bは
A−A断面図、第2図はa,b共その使用例を示す縦断
面図、第3図は従来例を示し、bはその平面図、aはB
−B断面図、第4図はa,b共その使用例を示す縦断面
図である。 20……基板、21……電極、22……配線、23……
絶縁膜。
FIG. 1 shows an embodiment of the present invention, a is a plan view thereof, b is a sectional view taken along the line AA, FIG. 2 is a longitudinal sectional view showing a usage example of both a and b, and FIG. 3 is a conventional example. , B is its plan view, a is B
-B sectional drawing, FIG. 4 is a longitudinal sectional view which shows the usage example together with a and b. 20 ... Substrate, 21 ... Electrode, 22 ... Wiring, 23 ...
Insulating film.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】基板の一面の所定位置に島状の多数の電極
を互いに離乗した状態で形成すると共に、これら電極を
結ぶ配線を形成し、次いで電極を除いた部分を被覆する
絶縁膜を形成することを特徴とする転写バンプ基板の形
成方法。
1. A plurality of island-shaped electrodes are formed at a predetermined position on one surface of a substrate in a state of being separated from each other, a wiring connecting these electrodes is formed, and then an insulating film for covering a portion excluding the electrodes is formed. A method for forming a transfer bump substrate, which comprises forming the transfer bump substrate.
JP60186917A 1985-08-26 1985-08-26 Method for forming transfer bump substrate Expired - Lifetime JPH0640559B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60186917A JPH0640559B2 (en) 1985-08-26 1985-08-26 Method for forming transfer bump substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60186917A JPH0640559B2 (en) 1985-08-26 1985-08-26 Method for forming transfer bump substrate

Publications (2)

Publication Number Publication Date
JPS6247139A JPS6247139A (en) 1987-02-28
JPH0640559B2 true JPH0640559B2 (en) 1994-05-25

Family

ID=16196952

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60186917A Expired - Lifetime JPH0640559B2 (en) 1985-08-26 1985-08-26 Method for forming transfer bump substrate

Country Status (1)

Country Link
JP (1) JPH0640559B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2621186B2 (en) * 1987-07-02 1997-06-18 松下電器産業株式会社 Method of forming transfer bump
JP2503147Y2 (en) * 1990-05-02 1996-06-26 三菱重工業株式会社 Portable pipe automatic processing factory
JPH0639661A (en) * 1992-07-23 1994-02-15 Komoda Kogyo:Kk Automatic prefabricated piping machining system and its equipment
JP2745096B2 (en) * 1992-12-18 1998-04-28 株式会社福田組 Mobile bar-shaped building member processing machine

Also Published As

Publication number Publication date
JPS6247139A (en) 1987-02-28

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