JPH0640580B2 - Semiconductor device - Google Patents

Description

The present invention relates to a gate turn-off (hereinafter abbreviated as GTO) thyristor or transistor (hereinafter abbreviated as TRS) capable of controlling conduction / non-conduction of a main current by a control current. )
And a semiconductor device having a junction structure for increasing the maximum breaking current.

[Background of the Invention]

Large-capacity GTO thyristors and TRSs have an emitter layer composed of one or more strip-shaped regions with a substantially constant width, and are exposed on one main surface of a semiconductor substrate together with a base layer adjacent to the emitter layer. One main electrode is brought into low-resistance contact with the strip-shaped region, and the control electrode is brought into low-resistance contact with the base layer so as to substantially surround each strip-shaped region, and the other main surface of the semiconductor substrate is further provided. The other main electrode is in low resistance contact with each other, and each electrode is connected to a pair of main terminal and control terminal.

"Hereinafter, the operation of the GTO thyristor will be described in detail by taking it as an example.

The turn-off operation of the GTO thyristor with the above structure is
As is well known, this is caused by the rapid elimination of excess carriers such as electrons and holes accumulated in the semiconductor substrate to the outside by a negative gate current.

Therefore, in the GTO thyristor, in order to draw the gate current from the current conduction region as easily as possible, a striped cathode emitter layer (hereinafter abbreviated as unit GTO) structure surrounded by the gate electrode as described above. In the related art, a structure in which a large number of these are arranged on a semiconductor substrate according to the current capacity is proposed (Japanese Patent Laid-Open No. 56-131).
955 publication).

In the conventional structure as described above, if each unit GTO is turned off at the same time, the current cutoff capacity can be increased in proportion to the number of unit GTO, as is apparent.

However, since the difference in the excess carrier extraction resistance of the gate electrode causes a difference in the gate current between the unit GTO placed near the gate electrode lead part and the unit GTO placed far from this, unit
It is very difficult to turn off the GTO at the same time.

Especially, the unit GT that is delayed during turn-off
Since the current is transferred to O from the unit GTO that was turned off early, the unit GTO that was delayed in operation becomes even more difficult to turn off, and at the end, there was a problem that it could not be turned off and thermal destruction occurred.

Such a turn-off failure was remarkable when a larger-diameter semiconductor substrate was used and the unit GTO had a more multiple array. As a solution to such a problem, Japanese Patent Laid-Open No. 59-16
A semiconductor device as disclosed in Japanese Patent No. 5457 has been proposed.

This is in the form of a strip, and it is not possible to directly conductively connect the gate electrode facing one side in the width direction of the emitter layer with the gate electrodes facing each other in the width direction to the gate electrode facing the other side. Instead, it is a structure in which it is electrically connected to the gate electrode and / or the gate lead connection portion on the one side through the high resistance of the base layer to form a float gate electrode.

According to such a floating gate electrode structure, in the initial stage of the turn-off operation, excess carriers in the semiconductor substrate become unbalanced from the gate electrodes facing each other in the width direction of the emitter layer due to the influence of the resistance of the base layer. It is pulled out.

However, at the end of the turn-off operation, the carriers can be biased to the other side and can be pulled out from the gate electrodes on both sides almost evenly, which can increase the maximum breaking current in each unit GTO. did it.

However, even in this structure, it is difficult to make the turn-off operation timing between the unit GTOs uniform.
With GTO thyristors and TRSs that use a disk-shaped semiconductor substrate and have multiple unit GTOs that have strip-shaped emitter layers and gate electrodes arranged radially and concentrically, even if the number of unit GTOs is increased, Has a problem that the maximum cutoff current cannot be increased.

[Object of the Invention]

Therefore, an object of the present invention is to improve the current drawing effect from the control terminal at the time of current interruption and the uniformity of turn-off operation timing between unit GTOs, and to increase the maximum interruption current. To provide a device.

[Outline of Invention]

A feature of the present invention is that at least three semiconductor layers having different conductivity types are alternately laminated between a pair of main surfaces of a semiconductor substrate, and one outermost layer is a strip region. The intermediate layer, which is divided and is separated from each other and exposed on one of the main surfaces, and which is adjacent to the outermost layer, is exposed on one of the main surfaces so as to surround the strip-shaped region, and each strip-shaped one The main electrode is in low resistance contact with the outermost layer and the other outermost layer, the control electrode is in low resistance contact with the one intermediate layer, and each strip-shaped one outermost layer is in the lead connection portion of the control electrode. In the semiconductor device which is multiply arranged, the control electrode portion, which is arranged most distantly with respect to the lead connection portion and is opposed to one side in the width direction of each strip-shaped outermost layer, is formed in the width direction. Higher impedance than the control electrode part facing the other side of the , The control electrode portions electrically connected to the lead connection portion and facing one side in the width direction of each one outermost layer are connected to each other by the conductive connection means, thereby increasing the maximum breaking current. There is a point.

Example of Invention

An embodiment in which the present invention is applied to a GTO thyristor will be described below with reference to the accompanying drawings.

FIG. 1 and FIG. 3 are plan views each showing a cathode side plane pattern of a semiconductor substrate 1 of a GTO thyristor, which is a different embodiment of the present invention, in quarters. FIG. 1 shows an example of a so-called center gate structure in which the gate connecting portion C ₁ is provided at the center of the semiconductor substrate. FIG. 3 shows the gate connecting portions C ₂ arranged in a ring shape and in multiple concentric circles. An example of an intermediate ring gate structure provided in the middle of the unit GTO array is shown.

Further, FIGS. 2 (a) and 2 (b) respectively show A- of FIG.
It is an expanded sectional view which follows the A and BB line, and FIG. 4 (a) and (b) is sectional drawing which follows CC and DD line of FIG. 3, respectively.

As is well known to those skilled in the art, and as can be seen from the sectional views of FIGS. 2 and 4, inside the semiconductor body 1 there are a p-emitter layer 11, an n-base layer 12, a p-base layer 13 and an n-emitter layer. 14 is formed, and a pn junction necessary for performing a thyristor operation is formed between the layers.

Then, the p-emitter layer 11 has an anode electrode 20
The cathode electrode 2 is conductively connected to the emitter layer 14, and the gate electrode 3 is conductively connected to the p base layer 13.

Further, as clearly shown in FIGS. 1 and 3, a strip-shaped unit GT in which a gate electrode 3 is formed so as to surround the cathode electrode 2 on the cathode-side main surface of the semiconductor substrate 1.
A large number of O 1-1 are arranged in parallel in a ring shape.

The ring-shaped array furthest from the gate connection parts C ₁ and C ₂ (herein referred to as the heaviest array) is composed of float gate units GTO 1-2 and 1-2 _a different from the normal unit GTO. In addition, the float gate electrodes 3-1 are electrically connected to each other, which is the main feature of the present invention.

FIG. 5 shows a position farthest from the gate connecting portions C ₁ and C _{2 of} FIGS. 1 and 3, that is, the float gate unit GTO1-2 arranged on the outer peripheral edge of the semiconductor substrate 1 and a partially enlarged plane of the periphery thereof. The figure is shown.

6 (a) and 6 (b) are sectional views taken along lines EE and FF in FIG. 5, respectively. That is, FIG. 6 (a)
Is the main gate electrode 3 and the strip-shaped float gate electrode 3-1.
FIG. 6B is a longitudinal sectional view of a portion (extending between the cathode electrodes 2), and FIG. 6 (b) shows the main gate electrode 3, the strip cathode electrode portion 2, the base resistance region 3-2, and the connection. It is a similar longitudinal sectional view of the float gate electrode 3-1-1.

Each strip-shaped cathode electrode 2 is sandwiched by the main gate electrode 3 and the float gate electrode 3-1 on both sides in the width direction.

Further, as shown in FIG. 6 (a), the inner ends of the respective floating gate electrodes 3-1 are connected to each other via a p base resistance region 3-2 _i (shown by hatching in FIG. 5). And is connected to the main gate electrode 3, and the outer ends thereof are conductively connected to each other by the connection float gate electrode 3-1-1. Thereby, all the floating gate electrodes 3-1 can maintain substantially the same potential.

N-emitter layer 1 in which strip-shaped cathode electrodes 2 are conductively connected
As shown in FIG. 6 (b), the outer peripheral edge of 4 is p
P base resistance region 3-2 formed in the base layer 13
via _p (shown with diagonal lines in FIG. 5),
It is connected to the connection float gate electrode 3-1-1.

As can be seen from FIGS. 6A and 6B, in the illustrated embodiment, the float gate electrode 3-1 and the connection float gate electrode 3-1-1 are connected via the p base resistance region 3-2 _p . Is formed on the surface of the p base layer 13 having the same height as the main gate electrode 3.

Then, the p base resistance regions 3-2 _i and 3-2 _p
Are formed by removing the p base layer 13 to some extent to make it thin. Further, an SiO ₂ insulating film 4 is formed on the exposed surface of the semiconductor substrate 1 in order to improve the gate breakdown voltage and protect the _p -base resistance regions 3-2 _i and 3-2 _p .

By adopting the structure shown and described above, it is assumed in FIG. 1 that the concentric multiple arrays of each unit GTO are arranged in the first row and the second row from the side close to the gate connecting portion C _1. , If you call it the third column, the normal GTO GTO
Unit GTO of the 1st and 2nd row
, And each float gate unit GTO in the third column, there is a difference in turn-off operation speed due to the difference in gate electrode resistance.

That is, the unit GTOs in the first and second rows turn off promptly, but the first row is still faster, so
The breaking current is transferred to the second row.

On the other hand, the turn-off operation of the float gate unit GTO in the third column is caused by both the difference in gate electrode resistance and the float gate effect due to the resistances 3-2 _i and 3-2 _p of the p base region 13 in the first and second columns. A little later than the line. Therefore, the cutoff current transferred from each unit GTO in the first column to each unit GTO in the second column is further transferred to each float gate unit GTO in the third column.

In addition, in each float gate unit GTO in the third column, as is clear from the description of Japanese Patent Laid-Open No. 165457/1984, as a prior art, it turns off due to the presence of the p base resistance region 3-2 _i. At the end of the operation, the carriers are extracted from both the main gate electrode 3 and the float gate electrode 3-1 almost uniformly, so that the maximum breaking current can be increased.

In this case, the main gate electrode 3 and the connection floating gate electrode 3
By adjusting the value of the base resistance region 3-2 _p interposed between the main gate electrode 3 and the floating gate electrode 3-1, the current drawing balance from the main gate electrode 3 and the float gate electrode 3-1 can be improved.

Further, the impedance adjusting method disclosed in Japanese Patent Laid-Open No. 59-165457 (e.g., etching removal, formation of opposite conductivity type region, between the cathode electrode 2 and the float gate electrode 3-1).
(Increased spacing, etc.) is also applicable to the present invention.

Furthermore, in the present invention, since the float gate electrodes 3-1 forming each unit GTO in the third column are connected by the connecting float gate electrodes 3-1-1,
The potential difference between the gate electrodes of each float gate unit GTO 2-1 is substantially zero.

Therefore, it is possible to transfer the currents of the respective end gates, which are transferred to the respective float gate units GTO, uniformly and at substantially the same timing, and to increase the maximum interruption current.

As shown in Fig. 1, in the conventional GTO thyristor in which strip-shaped unit GTOs are arranged and the third row also has a normal unit GTO structure, the withstand voltage is 2.5KV and the maximum breaking current is 1200A. According to the present embodiment, in the GTO thyristor in which all the floating gate electrodes are conductively connected to each other and the float gate unit GTO is arranged at the outermost periphery, the maximum breaking current is 220 when the breakdown voltage and the size of the semiconductor substrate 1 are the same.
It is about 2 times higher than 0A.

FIG. 7 shows a position farthest from the ring-shaped gate connection portion C _{2 in} FIG. 3—that is, a float gate unit GTO 1 arranged in the most distant arrangement, which is arranged at substantially the center of the semiconductor substrate 1.
-2a and _a partially enlarged plan view of the periphery thereof.

In the figure, the same reference numerals as those in FIG. 5 represent the same or equivalent parts. The sectional structure in this case is
Since FIGS. 6 (a) and 6 (b) are substantially the same, their illustration and description are omitted.

In the turn-off operation, in FIG. 3, the current is transferred from the ring-shaped gate connection portion C ₂ toward the inner side to the first row, the second row, and the third row, and the fourth row floating gate unit GTO 1
In -2 _a, the current cut-off takes place almost simultaneously and uniformly.

Meanwhile, in the outer region of the ring-shaped gate connecting portion C _2, in a manner similar to that described above with respect to FIG. 1, said ring-shaped gate connecting portion C ₂ toward the outside, the first row, the second row and the current After the relocation, the float gate unit GTO 1-2 in the third row will cut off the current almost simultaneously and uniformly.

Therefore, according to the embodiment of FIG. 3, in the final stage of the turn-off operation, the number of float gate units GTO contributing to the current interruption is further increased, and the maximum interruption current can be further increased.

As shown in Fig. 3, in the conventional GTO thyristor in which strip-shaped unit GTOs are multiply arranged and the third row also has a normal unit GTO structure, the withstand voltage is 4.5KV and the maximum cut-off current is 200K.
According to the present embodiment, the floating gate unit GTO is arranged at the outermost periphery and the central portion of the semiconductor substrate, and the floating gate electrodes are conductively connected.
In the O 2 thyristor, when the breakdown voltage and the size of the semiconductor substrate were the same, the maximum breaking current was improved to 2500A.

Although no examples have been given for TRS, it is clear that the n base layer 12 in FIGS. 2 and 4 may be made to correspond to the n type collector layer. In addition, the GTO thyristor and NT with the gate lead connection part having a multiple intermediate ring gate structure
Also in RS, if the linked float gate unit GTO of the present invention is applied to the unit GTO in the row far from each lead connection portion, the same effect can be obtained.

Furthermore, even when using a prismatic semiconductor substrate as disclosed in the above-mentioned Japanese Patent Laid-Open No. 59-165457,
By providing a means for conductively connecting the floating gate electrodes to each other, the same effect can be achieved.

〔The invention's effect〕

As described above, according to the present invention, it is possible to obtain a semiconductor device such as a GTO thyristor or TRS in which the current extraction effect from the control terminal at the time of current interruption is improved and the maximum interruption current is improved.

[Brief description of drawings]

1 and 3 are plan views showing a cathode side plane pattern of a quarter of a semiconductor substrate of a GTO thyristor according to a different embodiment of the present invention, and FIGS. 2 (a) and 2 (b) are diagrams of FIG. Sectional drawing which follows the AA cutting line and the BB cutting line, 4th
(A) and (b) are sectional views taken along the lines C-C and D-D of FIG. 2, and FIG. 5 is arranged on the outer peripheral edge of the semiconductor substrate in FIGS. 1 and 3. Float gate unit GT
A partially enlarged plan view of O and its periphery, and FIGS. 6 (a) and 6 (b) are
FIG. 5 is a sectional view taken along the line EE and line FF in FIG. 5, and FIG. 7 is a partially enlarged view of the float gate unit GTO arranged in the central portion of the semiconductor substrate in FIG. 3 and its periphery. It is a top view. 1 ... Semiconductor substrate, 1-1 ... Unit GTO, 2 ... Cathode electrode, 1-2, 1-2 _a ... Float gate unit G
TO, C ₁ , C ₂ ... Gate connection part, 3 ... Main gate electrode, 3-1 ... Float gate electrode, 3-1-1 ... Connection float gate electrode, 3-2 _i , 3-2 _p ... Base resistance region, 11 ... p emitter layer, 12 ... n base layer, 13 ... p base layer, 14 ... n emitter layer, 20
...... Anode electrode

Claims (2)

[Claims] 1. Between a pair of major surfaces of a semiconductor body, alternately.
At least three semiconductor layers having different conductivity types are sequentially stacked, and one outermost layer is divided into strip regions and separated from each other to be exposed on one of the main surfaces, and one of which is adjacent to the outermost layer. Is exposed on one of the main surfaces so as to surround the strip-shaped region, and the main electrodes are in low-resistance contact with each of the strip-shaped one outermost layer and the strip-shaped outermost layer, respectively. In a semiconductor device in which the control electrodes are in low-resistance contact with the layers, and the strip-shaped outermost layers are multiply arranged with respect to the lead connection portions of the control electrodes The control electrode portion facing one side in the width direction of each strip-shaped outermost layer is electrically connected to the lead connecting portion with a higher impedance than the control electrode portion facing the other side in the width direction, Each one of the outermost layers A semiconductor device in which control electrode portions facing each other on one side in the width direction are connected to each other by conductive connecting means. 2. The high impedance between the control electrode portion and the lead connecting portion, which face one side in the width direction of each one outermost layer, has a high impedance between the two in the above claim 1. A semiconductor device, characterized in that at least one of removing a part of a layer by etching and forming a region of opposite conductivity type in the part is performed.