JPH0640673B2 - Recursive noise reduction device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cyclic noise reduction device in which a luminance signal and a chrominance signal are time-division multiplexed and noise is reduced by a single cyclic noise reduction circuit.

[Prior Art] A magnetic recording / reproducing apparatus such as a video tape recorder used for home use has a structure in which a frequency-modulated luminance signal is frequency-multiplexed with a low-frequency converted color signal. A cyclic noise reduction method is particularly effective in removing noise components mixed in the processing process.
This cyclic noise reduction method focuses on the characteristic peculiar to a video signal having a high signal correlation in a field cycle or a frame cycle, and cyclically outputs an output delayed by one field period or one frame period in an image memory to an input. This is a method of removing noise by adding positively.

In the conventional cyclic noise reduction device 1 shown in FIG. 4, the luminance signal Y and the color signal C included in the video signal are separated by the luminance / color separation circuit 2, and then the color signal C is decoded by the decoding circuit 3. It is decomposed into two color difference signals of RY and BY. afterwards,
By the AD conversion circuits 4, 5 and 6 prepared for each signal,
The luminance signal Y and the color difference signals RY and BY are separately AD-converted, and noise reduction processing is performed by the cyclic noise reduction circuits 7, 8 and 9 connected to the AD conversion circuits 4, 5 and 6. After that, each signal is DA-converted by the DA conversion circuits 10, 11 and 12. The color difference signals RY and BY output from the DA conversion circuits 11 and 12 are combined into the color signal C by the encoding circuit 13, and the luminance signal output from the DA conversion circuit 10 is output by the luminance / color mixing circuit 14. It is mixed with Y and output. 15
Is an AD conversion circuit 4, 5, 6 and a cyclic noise reduction circuit 7,
8, 9 and a DA converter circuit 10, 11, 12 is a clock generation circuit for generating a clock signal, which separates the horizontal synchronizing signal in the video signal to be converted, and is an integer of the frequency f _H of the separated horizontal synchronizing signal. Form a clock signal with double frequency. The AD conversion circuit 4 used in this example is
The frequencies of the clock signals of 5, 6 and the DA conversion circuits 10, 11, 12 are 456 _H , 114 _H , 114 _H, which is about twice the color sub-carrier frequency sc (= 227.5 _H ),
This corresponds to 1/2 times and 1/2 times the frequency.

[Problems to be Solved by the Invention] Although the above-described conventional cyclic noise reduction device 1 needs to AD-convert the luminance signal Y and the color difference signals RY and BY in parallel, AD conversion is performed. 3 circuits of 4, 5 and 6 and 3 DA conversion circuits of 10, 11 and 12 are required, and in actuality, a color difference signal R that does not require noise reduction processing in a strict and wide band like the luminance signal Y. -Y and BY are subjected to independent noise reduction processing, so that 7, 8, 9 and 3 cyclic noise reduction circuits using an expensive image memory are required. Is inevitable and increase in manufacturing cost is unavoidable, and there is a margin in the conversion capability of the AD conversion circuits 5 and 6 as compared with the AD conversion circuit 4. Therefore, when the same element configuration is used, Problems such as not being able to fully utilize the conversion capabilities of the AD conversion circuits 5 and 6 There was a point.

[Means for Solving Problems] The present invention has been made to solve the above problems, and a luminance / color method in which a video signal is decomposed into a luminance signal and a color signal, and each signal is AD-converted and then time-division multiplexed. A time division multiplex circuit, a cyclic noise reduction circuit connected to the luminance / color time division multiplex circuit, which reduces noise by cyclically adding an output delayed by an image memory to an input, and this cyclic type It is characterized in that it is provided with a luminance / color signal superimposing circuit which is connected to a noise reduction circuit, decomposes an input into a luminance signal and a color signal, and DA-converts each of them and then mixes them.

[Operation] The present invention decomposes a video signal into a luminance signal and a chrominance signal, AD-converts each signal, and time-division-multiplexes the time-division multiplexed outputs of the luminance signal and the chrominance signal into a single image memory. By supplying the noise to the cyclic noise reduction circuit and performing noise reduction processing, the functions of the cyclic noise reduction are integrated into one circuit common to the luminance signal and the chrominance signal, and the circuit configuration is simplified.

[Embodiment] An embodiment of the present invention will be described below with reference to FIGS. 1 to 3. FIG. 1 is a circuit configuration diagram showing one embodiment of the cyclic noise reduction apparatus of the present invention, and FIG.
A circuit diagram showing an embodiment of the clock generation circuit shown in the figure,
FIG. 3 is a signal waveform diagram of each part of the circuit shown in FIG.

In FIG. 1, a cyclic noise reduction apparatus 21 decomposes a video signal into a luminance signal Y and a color signal C, AD-converts each signal, and time-division-multiplexes it, and a luminance / color time-division multiplexing circuit 22. Image memory 23 connected to color time division multiplexing circuit 22
A cyclic noise reduction circuit 23 that cyclically adds the output delayed by a to the input to reduce noise, and is connected to the cyclic noise reduction circuit 23, and the inputs are connected to the luminance signal Y and the color signal C.
It is composed of a luminance / color signal superimposing circuit 24 which is decomposed into a plurality of parts, which is DA-converted and mixed, and a clock generating circuit 25 which supplies a clock signal to each part of the circuit.

The luminance / color time division multiplexing circuit 22 connects the luminance signal / color signal AD conversion circuits 22a and 22b to the luminance / color separation circuit 2 which decomposes an input video signal into a luminance signal Y and a color signal C, The AD conversion circuit 22a is directly connected to the AD conversion circuit 2
2b is a changeover switch 2 via a decoding circuit 22c
2d, and the signals alternately selected by the changeover switch 22d are supplied to the cyclic noise reduction circuit 23. The decoding circuit 22c converts the quadrature two-phase modulated color signal C converted into a digital signal into the color difference signals RY, B-.
A circuit for decomposing into Y, and two sets of latch circuits 26, 27 and 2 for latching the color signal C at different timings.
8 and 29 are connected to the changeover input terminal of the changeover switch 30 at the final stage. The latch circuits 26 and 27 of one set respectively include clock signals Sf and Sh which will be described later.
The latch operation is performed according to. The other set of latch circuits 28 and 29 respectively perform a latch operation according to clock advances Sg and Si obtained by advancing the clock signals Sf and Sh by a phase angle of 90 degrees.

The cyclic noise reduction circuit 23 has a gain of 1-K (however,
The input attenuator circuit 23b with 0 <K <1) is connected to the field memory type image memory 23a via the adder circuit 23c, and the output of the image memory 23a is added via the feedback attenuator circuit 23d with a gain of K. The configuration is such that it is supplied to the circuit 23c, and the addition circuit 23c
Is the output video signal. The cyclic noise reduction circuit 23 obtains a higher degree of SN improvement as the positive feedback gain K is brought closer to 1 and the number of fields to be correlated is increased. In this embodiment, the frequency ck of the clock signal Sa of the image memory 23a is set to the horizontal synchronization frequency.
It is set to 840 times _H.

The luminance / color signal superimposing circuit 24 is the cyclic noise reduction area circuit 2
The latch circuit 24b for the luminance signal is connected to one switching output terminal of the changeover switch 24a connected to No. 3, and the pair of latch circuits 24c and 24d for the color difference signal is connected to the other switching output terminal. Latch circuit 24b
Is the luminance / color mixing circuit 14 via the DA conversion circuit 24e.
It is connected to the. The latch circuits 24c and 24d include two latch circuits 24f, 24g and 24h, 24, respectively.
It is connected to the encoding circuit 24j via i, and the output of the encoding circuit 24j is supplied to the luminance / color mixing circuit 14 via the DA conversion circuit 24k.

As shown in FIG. 2, the clock generation circuit 25 includes a sync separation circuit 31 for separating the horizontal sync signal from the video signal supplied to the luminance / color separation circuit 2 and a burst gate circuit 32 for separating the color burst signal. And a clock signal Sa (frequency c
k), or a lock signal Se (frequency 4sc) locked in phase with the color burst signal is used to form various clock signals. The sync separation circuit 31 includes a phase comparison circuit 3
3, low frequency wave circuit 34, voltage controlled oscillator 35, 1/84
The 0 frequency dividing circuit 36 is connected to form a phase locked loop, and the output of the voltage controlled oscillator 35 has the frequency ck (= 840 _H ) for the AD conversion circuit 22a, the DA conversion circuit 24e and the image memory 23a. It becomes the clock signal Sa. The clock signal Sa is divided by the 1/2 divider circuit 37 to become the clock signal Sb, and the changeover switch 22
and the latch circuit 24b. Further, the frequency is 1 from the 1/2 frequency divider circuit 38 following the 1/2 frequency divider circuit 37.
The clock signal Sc of / 4ck is the phase correction circuit 4 described later.
6 is supplied. Furthermore, 1 following the 1/2 divider circuit 38
The clock signal Sd having a frequency of 1/8 ck is supplied from the / 2 frequency dividing circuit 39 to the changeover switch 30 and the latch circuits 24c and 24d. However, the latch circuit 24
Since d operates with a clock signal having a phase opposite to that of the latch circuit 24c, a signal obtained by inverting the phase of the clock signal Sd by an inverter circuit (not shown) or the like is supplied to the latch circuit 24d.

On the other hand, the burst gate circuit 32 includes a phase comparison circuit 4
0, sample and hold circuit 41, low frequency wave circuit 42,
The voltage controlled oscillator 43 and the 1/4 frequency dividing circuit 44 form a phase locked loop and are connected. The burst gate circuit 32 operates in synchronization with the burst gate pulse supplied from the burst gate pulse generation circuit 45, and extracts the color burst signal in the input video signal. The sample and hold circuit 41 uses the output of the burst gate pulse generation circuit 45 as a sampling clock and samples and holds the output of the phase comparison circuit 40. The output of the voltage controlled oscillator 43 is supplied to the AD conversion circuit 22d and the DA conversion circuit 24k as a clock signal Se having a frequency of 4sc. The output of the 1/4 frequency divider circuit 44 is supplied to the latch circuit 26 and the latch circuits 24g and 24i as a clock signal Sf having a frequency of sc. Furthermore, 1/4
From the frequency dividing circuit 44, the clock signal Sg having the same frequency as the clock signal Sf and having a phase advanced by 90 degrees from the clock signal Sf is supplied to the latch circuit 28.

The 1/4 frequency divider circuit 44 includes a phase correction circuit 46 for phase-correcting the clock signal Sf with the clock signal Sc.
Is connected, and the clock signal Sh of frequency's obtained from the phase correction circuit 46 is supplied to the latch circuits 27 and 2
The clock signal Si, which is supplied to 4f and has a phase advanced by 90 degrees from the clock signal Sh, is supplied to the latch circuit 29.

By the way, the signal waveforms of the respective parts of the circuit of the cyclic noise reduction device 21 having the above-mentioned configuration are as shown in FIG. As can be seen from the figure, the output of the luminance / color time division multiplexing circuit 22 is changed according to the switching cycle of the changeover switch 22d.
The color difference signals RY and BY are alternately arranged twice before and after the luminance signal Y, but the image memory circuit 2
In order to save the storage capacity of 3a, even if only one of two consecutive times is stored in the image memory circuit 23a, each signal is processed by a clock signal having a frequency exceeding twice the occupied band. Therefore, it is possible to use the common cyclic noise reduction circuit 23 for noise reduction processing without considering the loss of the original information. That is, among the outputs of the changeover switch 22d, the signal density ratio of the color difference signals RY and BY to the luminance signal Y is 4: 1, but the luminance signal Y and the color difference signals RY and Considering the originally occupied band of BY, there is no inconvenience that the original information is lost due to this signal density ratio.

As described above, the cyclic noise reduction device 21 decomposes the video signal into the luminance signal Y and the color signal C and AD-converts each, and the color signal C is decoded by the decoding circuit 22c.
And B-Y and time-division-multiplexed on the luminance signal Y, and the obtained time-division-multiplexed output is supplied to the cyclic noise reduction circuit 23 using the image memory 23a to perform noise reduction processing. As for the cyclic noise reduction circuit 23 which requires the expensive image memory 23a, only one circuit is required, which has a great effect of cutting down the manufacturing cost, and in consideration of the occupied band of the luminance signal Y and the color signal C. By setting the time division ratio to an appropriate ratio, both signals can be time division multiplexed without losing the original information. Therefore, a circuit configuration in which a single cyclic noise reduction circuit 23 performs noise reduction processing The noise reduction can be mentioned without worrying about the adverse effect of the reduction. Further, the output of the cyclic noise reduction circuit 23 is output to the luminance signal Y by the latch circuits 24b, 24c and 24d.
And color-difference signals R-Y and B-Y.
Since BY is encoded into the color signal C by the encoding circuit 24j and then DA-converted and mixed, the luminance signal Y and the color signal C are subjected to AD / DA conversion processing by their respective basebands. Therefore, the influence of the jitter can be eliminated even in the case of a signal such that the time axis of the luminance signal and the color signal are slightly deviated from each other, such as the reproduction output of the video tape recorder. Furthermore, since both the AD conversion circuit and the DA conversion circuit need to have two circuits 22a and 24e for the luminance signal and two circuits 22b and 24k for the color signal, respectively, the configuration of the entire apparatus can be favorably simplified. be able to.

In the above embodiment, the frequencies of the various clock signals generated by the clock generation circuit 25 are not limited to the frequencies shown in the embodiment, and it goes without saying that the AD conversion circuits 22a and 22b or the DA conversion circuit to be used are used. 24e, 24k
It is advisable to set appropriate frequencies in consideration of the conversion capability such as or the like, or the occupied band of the luminance signal and the chrominance signal targeted for the low noise region.

[Effects of the Invention] As described above, according to the present invention, a video signal is decomposed into a luminance signal and a color signal, each signal is AD-converted, and then time-division multiplexed, and a time-division multiplexed output of the luminance signal and the color signal is generated. Since it is supplied to a cyclic noise low-frequency circuit using an image memory and subjected to noise reduction processing, the output of the cyclic noise reduction circuit is decomposed into a luminance signal and a chrominance signal, which are DA-converted and then mixed. As for the cyclic noise reduction circuit, only one circuit is required, and by setting the time division ratio in consideration of the occupied bands of the luminance signal and the chrominance signal, both signals can be time division multiplexed without losing the original information. Therefore, it is possible to raise the noise reduction effect without worrying about the adverse effect of the simplification of the circuit configuration in which the noise reduction processing is performed by a single cyclic noise reduction circuit. Baseband Since it is subjected to AD / DA conversion processing by, it is possible to eliminate the influence of jitter even in the case where the time axis of the luminance signal and the color signal are slightly deviated from each other, such as the reproduction output of the video tape recorder. Furthermore, since the AD conversion circuit and the DA conversion circuit each need to have two circuits for the luminance signal and the color signal, respectively, there is an excellent effect that the configuration of the entire apparatus can be favorably simplified.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of the cyclic noise reduction apparatus of the present invention, FIG. 2 is a circuit diagram showing an embodiment of the clock generation circuit shown in FIG. 1, and FIG. FIG. 4 is a signal waveform diagram of each part of the circuit shown in FIG. 1, and FIG. 4 is a circuit configuration diagram showing an example of a conventional cyclic noise reduction device. 21 ... Recursive noise reduction device, 22 ... Luminance / color time division multiplexing circuit, 23 ... Recursive noise reduction circuit, 24 ... Luminance / color signal superposition circuit.

Claims (1)

[Claims] 1. A luminance / color time-division multiplexing circuit for decomposing a video signal into a luminance signal and a color signal, AD-converting each signal and then time-division multiplexing, and connected to the luminance / color time-division multiplexing circuit,
A cyclic noise reduction circuit that reduces noise by cyclically adding the output delayed in the image memory to the input, and is connected to this cyclic noise reduction circuit, and decomposes the input into a luminance signal and a chrominance signal, A recursive noise reduction device comprising a luminance / color signal superimposing circuit which is DA-converted and then mixed.