JPH0642232B2 - Parallel processor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a parallel processing apparatus configured by connecting a plurality of processing units in parallel, and processing data of each processing unit is stored in a common storage area or another storage area. The present invention relates to a data transfer method for high-speed transfer to the processing unit.

(Prior Art) With the development of semiconductor technology in recent years, it has become easy to realize a small-sized arithmetic unit represented by a microcomputer and having excellent processing capability. On the other hand, in many applications, for example, in the field of computer graphics, the amount of calculations to be processed is increasing more and more, and a powerful processing device with excellent cost performance is being demanded.

Recently, many parallel processing devices have been developed which have a configuration in which a high-performance microcomputer and a processing unit composed of a high-speed numerical operation LSI are used as a unit and a large number of them are connected in parallel.

Such a parallel processing device has an advantage that even if the processing capacity of the processing unit is small, a processing device having a desired processing capacity can be configured by increasing or decreasing the number of processing units according to the purpose. . However, when processing is performed by this type of parallel processing device, it is necessary to transfer data necessary for processing of each processing unit and processing results to each other or to a common storage area.

Conventionally, some configurations have been adopted to realize a communication function between a plurality of processing units.

For example, there is a method in which each processing unit is provided with an external input / output terminal, is connected to another processing unit via this terminal, and requests the other processing unit for data transmission / reception by an interrupt or the like. However, this method has a problem that the overhead becomes large because the operation of each processing unit is always required when data is transferred.

When collecting the processing results of each processing unit in a common storage area, the output data from each processing unit and the address where it should be stored are temporarily stored in a buffer memory, and A mechanism for sequentially reading the contents of the buffer memory and transferring the data to the corresponding address in the common storage area has been realized. However, this mechanism has a problem that if the access time of the storage area to which the data is to be transferred is slow, it takes time to store the data in the storage area. This is for devices that require high-speed data transfer, such as when generating a shadow image and transferring / displaying it in an image memory.
It was a big problem.

(Object of the Invention) In a parallel processing device configured by connecting a large number of processing units in parallel, data transfer between the processing units or a common data storage area such as an image memory from each processing unit. When performing data transfer to and from the processing units, the processing units were coupled by a data bus capable of high-speed data transfer via an interface having a buffer memory, and data was transferred from each processing unit via the data bus. In this case, after the end of the data transfer, the processing unit number that permits the next data transfer is also transferred at the same time. In each processing unit, the data to be transferred is temporarily stored in the buffer memory, and the data on the data bus is transferred. Always monitor the processing unit number and if it is equal to your unit number, the current data transfer sequence. The data stored in the buffer memory is collectively transferred after the end of the connection.
It is to realize a function of transferring data of a large number of processing units to another processing unit or a common storage area at high speed without causing contention.

(Structure and Operation of the Invention) FIG. 1 is an example of a parallel processing device configured by connecting a plurality of processing units in parallel, and is a structural example of a device having a high-speed data transfer bus according to the present invention.

This type of device configuration itself is generally known as a configuration method for realizing a function of performing a huge amount of calculation at high speed by using a processor with a limited processing capability, and for example, for generating a three-dimensional shadow image in computer graphics. The processing device and the like have the same configuration.

In FIG. 1, MP is a main control unit that controls the entire apparatus,
PU # 1, PU # 2, ..., PU # N are processing units that execute processing independently, and CM is a common memory for commonly storing processing data. For example, processing images are stored in the CM. Is an image memory or the like for displaying.

The HB is a high-speed data transfer bus for transferring data between each processing unit and the common memory CM, IFP # 1,
IFP # 2, ..., IFP # N are processing units PU #
1, PU # 2, ..., PU # N and the high-speed data transfer bus HB
And an interface unit having a buffer memory for temporarily storing processing data to be transferred.

Similarly, the IFM is an interface unit between the common memory and the high speed data transfer bus HB.

To operate the apparatus configured as described above, for example, first, the main control unit MP loads a program and data required for processing to each processing unit.

Next, in each processing unit, processing is executed independently based on the loaded program and data, and if it is necessary to transfer the processed data to another processing unit or common memory, the data to be transferred is transferred to the interface unit. Transfer to other processing units or common memory via the IFP and high speed data transfer bus. At this time, the high-speed data transfer bus executes data transfer requests from a large number of processing units without causing contention.

FIG. 2 is a diagram showing an example of a data transfer format when data is transferred from each processing unit to a common memory (for example, an image memory) on the high-speed data transfer bus shown in FIG. This is an example of the case where the write address and the data are transferred in a packet format.

The transfer in the packet format as shown in the figure has an advantage that the number of signal lines required to realize a high speed data transfer bus can be reduced.

In FIG. 2, the memory address A is the address data of the common memory in which the data should be written, the transfer data number N is the total number of data to be transferred in the data sequence, and the bus master number PN is the data transfer after the end of the data sequence. Data 1, data 2, ..., Data N (D1, D2, ..., DN) indicate data to be written in the common memory.

As shown in the figure, when a plurality of data are transferred to a common memory following one address data, the plurality of data are regarded as data to be stored at consecutive addresses and are stored in the common memory.

Further, the table shows an example of the types of actual signal lines of the high speed data transfer bus in FIG. 1, and FIGS. 3 and 4 also show the states of signals on the high speed data transfer bus. Here is an example.

As shown in the table, in order to express high-speed data transfer, the entire bus is a synchronous bus that operates in synchronization with the basic clock. Further, the six control lines for transferring the control signal from the processing unit to the common memory are for identifying the data type in the data packet of FIG. 2 and for facilitating the implementation of the interface circuit. Is.

FIG. 3 is an example showing the basic operation of the high-speed data transfer bus and shows the states of data transfer and control signals (indicated by negative logic).

In the data transfer sequence, when a processing unit is designated by the bus master number PN, the interface unit IF between the processing unit and the high speed data bus in FIG.
P transfers data to the common memory in the following sequence.

1) The output of the data clock is started in synchronization with the basic clock, and the transfer flag is activated (negative).

2) The address data A is output to the data line in synchronization with the first and second data clocks, and at the same time, the address validity is activated.

3) In synchronization with the next data clock, the number N of data to be transferred is output to the data line and the data number valid is activated.

4) The predetermined processing unit number is output to the data line as the bus master number PN in synchronization with the next data clock. At the same time, the bus master valid is activated.

5) The data D1, D2, ..., DN for the number of data N is output to the data line in synchronization with the subsequent data clock. Also, the data valid line is activated from the first data transmission to the last data transmission.

According to the sequence as described above, data is transferred from each processing unit to the common memory, and at the interface IFM with the high-speed data transfer bus on the common memory side in FIG. 1, the memory corresponding to the address data A in the above sequence. Data sequentially from address D1, D
2, ..., DN are stored in the common memory.

As described above, the bus master number PN in the data transfer sequence in FIG. 2 designates the processing unit that permits the data transfer after the data transfer sequence is completed, so that a large number of processor units share the same data transfer bus. It is possible to arbitrate access contention when using.

FIG. 4 shows an example of data transfer by a plurality of processing units, and arbitration of access competition is performed as follows.

1) Each processing unit has its own processing unit number as an identifier.

2) Access from each processing unit to the high-speed data transfer bus is performed by the following method.

a) A unit having an access right (a processing unit permitted to transfer data to the high-speed data transfer bus) outputs the number of the processing unit to which the access right is given next as the bus master number PN in the data transfer sequence.

b) Each processing unit compares the bus master number PN on the data line with its own unit number, and only when they match, starts bus access after the end of the current data transfer sequence. If this does not match, do nothing.

c) When the unit to which the access right is given does not have the data to be transferred, the access right is handed over to the next unit in the sequence in which the data number N is 0 as shown in FIG.

The configuration and basic operation of the high-speed data transfer bus in the parallel processing device shown in FIG. 1 have been described above.
The operation of such a high-speed data transfer bus is performed by the interface section IFP # 1, ..., IFP # N between the bus and each processing unit PU # 1, ..., PU # N in FIG. 1 and the common memory MC. It is realized by the interface unit IFM.

FIG. 5 is a schematic configuration diagram of the interface unit IFP between the high-speed data transfer bus and the processing unit, wherein the data output from the data bus (processor bus) of the processing processor constituting the processing unit is described above. The data is transferred to an operating high-speed data transfer bus.

In the figure, 1 is a processor bus, 2 is a processor bus interface, 3 is a first data buffer, 4 is a second data buffer, 5 is a data counter, 6 is a bus master number register, 7 is a data multiplexer,
8 is a high-speed data transfer bus control circuit, 9 is a unit number register, 10 is an access right detection circuit,
HB indicates a high speed data transfer bus.

An outline of the operation of the interface unit IFP will be described with reference to FIG.

The address and data of the common memory are stored in the first data buffer 3 or the second data buffer 4 from the processing unit via the processor bus interface 2, and at the same time, the data stored in the data counter 5 is counted.

In addition, the access right detection circuit 10 always compares the bus master number in the transfer data sequence on the high-speed data transfer bus HB with the contents of the preset unit number register 9, and if they match, the high-speed data transfer is performed. The operation of the bus control circuit 8 is permitted, and the bus control circuit outputs the contents of the data buffer, the data counter 5, and the bus master number register 6 to the high-speed data transfer bus HB according to the procedure described in FIGS. 2 and 3. Take action.

FIG. 6 is a schematic configuration diagram of an interface unit IFM between the high speed data transfer bus and the common memory.

In the figure, the transfer data and various control signals on the high-speed data transfer bus HB are decoded by the high-speed data transfer bus receiving circuit 11, and the transfer data and the memory address are output respectively.

After the memory address is stored in the address register 12,
The address decoder 13 converts the physical address of the common memory CM15, and the write control circuit 14 makes the memory cell of the corresponding address writable.

On the other hand, the transferred data are sequentially sent to the serial-parallel conversion circuit 16, and time-series data are collected and transferred in parallel to the memory. Reference numeral 17 is a basic clock generation circuit.

This is for writing data at high speed in a memory composed of semiconductor memory devices that operate at a normal access speed. For example, by writing 32 pieces of data in parallel at the same time, the write speed of the memory device can be increased. It can be 32 times faster than the access speed.

Therefore, the data transfer speed of the high-speed data transfer bus can be increased, and a large amount of image data such as a moving image can be transferred to the image memory at high speed. However, in the data transfer sequence of FIG. 2, it is necessary to control the interface unit IFP of each processing unit so that the number of data transferred at one time becomes an integral multiple of the number of parallel simultaneous writes to the memory.

The above is the description of the embodiment of the configuration and operation of the high-speed data transfer bus when the processing data is transferred from the processing unit to the common memory at high speed in the parallel processing device of FIG.

On the other hand, in order to transfer data from each processing unit to another processing unit, for example, a data transfer format in which the number of the transfer destination processing unit is transferred instead of the memory address in FIG. 2 is used. Good.

FIG. 7 is a schematic configuration example of an interface circuit between a high-speed data transfer bus and a processing unit for transferring data between the processing units.

In the interface unit IFP between the processing unit and the high-speed data transfer bus HB, a transfer destination detection circuit 18 for detecting a match between the transfer destination processing unit and the processing unit, a receiving buffer memory 19 for receiving data, FIG. High-speed data transfer bus receiver circuit 11 and serial-parallel converter circuit
By providing 16 and storing the data transferred to the processing unit in the data receiving memory, the data transfer between the processing units can be performed at high speed.

A high-speed data transfer bus that operates as described above,
By providing an interface with the processing unit and the common memory, it is possible to transfer processing data from each processing unit to a common memory such as image memory at high speed and to transfer data between processing units without causing access conflict. You can

Of course, the parties to which data is transferred from each processing unit are not limited to the common memory and other processing units,
Obviously, it may be an external output device or another processing device, or a plurality of sets of these may be the transfer destination.

Further, in addition to the data transfer format and signal format of the high speed data transfer bus described in the above embodiment, various data transfer formats and signal formats capable of obtaining the same effect may be adopted.

(Effects of the Invention) As described above, according to the present invention, in a parallel processing device configured by connecting a large number of processing units in parallel, data such as a calculation result of each processing unit causes access competition. Without this, the data can be transferred at high speed to another processing unit, a common memory such as an image memory, or another processing device.

Therefore, for example, in a parallel processing device that generates a three-dimensional shadow image based on three-dimensional object shape data, each processing unit shares and generates the above-described image, and the generated image data is generated at high speed according to the present invention. By transferring the image to the image memory having the function of displaying the image on the display by the data transfer bus, the function of generating and displaying the image at high speed can be realized.

That is, since the transfer of the image data to the image memory can be performed without interfering with the image generation processing in a large number of processing units, it is possible to provide a shadow image generation apparatus having excellent processing capability as the entire apparatus.

In this case, if a larger number of processing units are used or the processing capability of the processing units is improved by using higher performance elements, real-time generation and display of moving images will be possible.

Further, since the present invention adopts a method of transferring data to the data memory in a packet format, converting the data packet into parallel data, and writing in parallel to the data memory, a general high-speed semiconductor memory device is used. Even if the data memory configured as described above is used, there is also an advantage that data can be transferred at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram of a parallel processing device having a high-speed data transfer bus, FIG. 2 is a diagram showing an example of a data transfer format on the high-speed data transfer bus of FIG. 1, and FIG. FIG. 4 is an explanatory diagram showing an operation example, FIG. 4 is an example of a data transfer operation by a plurality of processing units in the high speed data transfer bus, and FIG. 5 is a schematic configuration example of an interface circuit between the high speed data transfer bus and each processing unit. Similarly, FIG. 6 is a schematic configuration example of an interface circuit between the high-speed data transfer bus and the common memory, and FIG. 7 is a schematic configuration of an interface circuit between the high-speed data transfer bus and the processing unit for performing data transfer between the processing units. Here is an example. PU: main control unit, PU # 1 to PU # N ... processing unit, IFP # 1 to IPF # N ... interface unit, IFM ... interface unit, HB ... high-speed data transfer bus, CM ... common memory , 1 ... Processor bus, 2 ... Processor bus interface, 3 ... First data buffer, 4 ... Second data buffer, 5 ... Data counter, 6 ... Bus master number register, 7 ... Data multiplexer , 8 ... High-speed data transfer bus control circuit, 9 ... Unit number register, 10 ... Access right detection circuit, 11 ... High-speed data transfer bus receiving circuit, 12 ... Address register, 13 ... Address decoder, 14 ... … Write control circuit, 15 …… Common memory (CM), 16 …… Serial-parallel conversion circuit, 17 …… Basic clock generation circuit, 18 …… Transfer destination detection times Road, 19 ... Receive buffer memory.

Claims (2)

[Claims] 1. A parallel processing apparatus comprising: two or more sets of processing units each independently performing a processing; a data transfer bus; and an interface unit connected to the data transfer bus for each processing unit. Is a data transfer bus control circuit for sending data to the data transfer bus, and monitors the data on the data transfer bus. If the number of the processing unit to which the access right is given next matches the self processing unit number, A parallel processing device comprising: an access right detection circuit that permits the operation of a data transfer bus control circuit; and a transfer destination detection circuit that detects data destined for its own processing unit on the data transfer bus. 2. Two or more sets of processing units for independently executing processing, a common memory for storing data of processing results, a data transfer bus, and each processing unit connected to the data transfer bus. One interface part,
A parallel processing device including a second interface unit that connects the common memory to a data transfer bus, wherein the first interface unit includes a data transfer bus control circuit that sends data to the data transfer bus, and a data transfer unit. An access right detection circuit for monitoring the data on the bus and permitting the operation of the data transfer bus control circuit when the number of the processing unit to which the access right is given next and the self processing unit number match are included. Parallel processing unit.