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JPH0642494B2 - Method of manufacturing thin film transistor - Google Patents
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JPH0642494B2 - Method of manufacturing thin film transistor - Google Patents

Method of manufacturing thin film transistor

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Publication number
JPH0642494B2
JPH0642494B2 JP523388A JP523388A JPH0642494B2 JP H0642494 B2 JPH0642494 B2 JP H0642494B2 JP 523388 A JP523388 A JP 523388A JP 523388 A JP523388 A JP 523388A JP H0642494 B2 JPH0642494 B2 JP H0642494B2
Authority
JP
Japan
Prior art keywords
thin film
substrate
film transistor
polycrystalline
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP523388A
Other languages
Japanese (ja)
Other versions
JPH01181570A (en
Inventor
節夫 金子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP523388A priority Critical patent/JPH0642494B2/en
Publication of JPH01181570A publication Critical patent/JPH01181570A/en
Publication of JPH0642494B2 publication Critical patent/JPH0642494B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Description

【発明の詳細な説明】 (従来の技術) 近年液晶フラットパネルディスプレイ、エレクトロルミ
ネセンスディスプレイ等の駆動デバイスとして使われる
薄膜トランジスタの研究開発が盛んに行われている。こ
の薄膜トランジスタに要求されていることは、(1)透明
絶縁性基板上に形成できること、(2)ON電流が大きく
OFF電流が十分小さいこと、(3)大容量のトランジス
タアレイを形成するプロセスが可能なこと等があげられ
ており、半導体薄膜として多結晶SiやアモルファスS
iを能動層に用いた薄膜トランジスタが研究開発されて
いる(例えば、ソサエティオブインフォーメイションデ
ィスプレイ、ダイジェストオブテクニカルパイパー(Soc
iety of lnformation Display,Digest of Technical Pa
per)p312,1984)。ところが、多結晶Siやアモルファス
Siのキャリア移動度は1〜20cm2/v・secと比較的小
さいため、この薄膜トランジスタを駆動させるための周
辺駆動ICが必要となる。そのため、大容量の薄膜トラ
ンジスタアレイと周辺駆動ICとの端子接続が必要にな
り、装置の大型化、高コスト化、低信頼化をもたらして
きた。
DETAILED DESCRIPTION OF THE INVENTION (Prior Art) In recent years, research and development of thin film transistors used as driving devices for liquid crystal flat panel displays, electroluminescent displays, and the like have been actively conducted. This thin film transistor requires (1) it can be formed on a transparent insulating substrate, (2) a large ON current and a sufficiently small OFF current, and (3) a process for forming a large capacity transistor array. As a semiconductor thin film, polycrystalline Si or amorphous S is mentioned.
A thin film transistor using i as an active layer has been researched and developed (for example, Society of Information Display, Digest of Technical Piper (Soc
iety of lnformation Display, Digest of Technical Pa
per) p312, 1984). However, since the carrier mobility of polycrystalline Si or amorphous Si is relatively small at 1 to 20 cm 2 / v · sec, a peripheral drive IC for driving this thin film transistor is required. Therefore, it is necessary to connect terminals between the large-capacity thin film transistor array and the peripheral driving IC, which has brought about an increase in size, cost, and reliability of the device.

一方、単結晶Siはトランジスタとしての前述の条件
(2),(3)の要求を満足し、移動度も高く周辺駆動回路も
トランジスタアレイ形成時に同時に同一基板上に形成で
きるため、周辺駆動回路との端子接続が不要になる利点
が有る(たとえば、ソサエティ オブ インフォーメー
ションディスプレイ,ダイジェスト オブ テクニカル
ペイパー(Society of Information Display,Digest of
Technical Paper),p150-p151,1983)。しかしながらこの
Si単結晶基板を用いた周辺回路を伴ったトランジスタ
アレイは、基板として不透明の単結晶Siを使用してい
るため、基板を透過する光を使う液晶ディスプレイを駆
動するには不適当であった。
On the other hand, single-crystal Si has the above-mentioned conditions as a transistor.
Since the requirements of (2) and (3) are satisfied and the mobility is high and the peripheral drive circuit can be formed on the same substrate at the same time when the transistor array is formed, there is an advantage that terminal connection with the peripheral drive circuit is unnecessary (for example, , Society of Information Display, Digest of Technical Paper
Technical Paper), p150-p151, 1983). However, since the transistor array with peripheral circuits using this Si single crystal substrate uses opaque single crystal Si as the substrate, it is unsuitable for driving a liquid crystal display using light transmitted through the substrate. It was

一方、単結晶Siを薄膜化する技術としては、デバイス
が形成された単結晶Si基板を支持基板に張付けた後研
摩加工して薄膜化し、再度所望の基板に張付ける転写技
術が知られている(ジャパニーズ ジャーナル オブ
アプライド フィジックス(Jpn.J.Appl.Phys.)23,L815
〜817,1984)。この技術を用いて液晶を駆動するトラン
ジスタ部と周辺駆動回路を同時に形成することにより端
子接続技術の不要な周辺駆動回路付薄膜トランジスタア
レイが得られる。
On the other hand, as a technique for reducing the thickness of single crystal Si, a transfer technique is known in which a single crystal Si substrate on which a device is formed is attached to a supporting substrate, then polished to form a thin film, and attached again to a desired substrate. (Japanese Journal of
Applied Physics (Jpn.J.Appl.Phys.) 23, L815
~ 817, 1984). A thin film transistor array with a peripheral drive circuit that does not require a terminal connection technique can be obtained by simultaneously forming a transistor portion for driving a liquid crystal and a peripheral drive circuit using this technique.

しかし、単結晶Siトランジスタを液晶を駆動するため
のスイッチング素子として使用する場合には光感度が高
いため光感度低減のために遮光膜を設ける必要があるこ
と、島状の単結晶Si部を薄膜トランジスタアレイ部に
残す必要があるためプロセスが複雑になることなどの問
題があった。
However, when a single crystal Si transistor is used as a switching element for driving a liquid crystal, it has a high photosensitivity, and therefore it is necessary to provide a light shielding film to reduce the photosensitivity. There is a problem that the process becomes complicated because it needs to be left in the array section.

(発明が解決しようとする問題点) 本発明の目的は、前記単結晶Siを薄膜化する技術を用
い、周辺駆動回路を単結晶Si駆動回路で構成した時の
液晶を駆動するのに適した薄膜トランジスタを簡単なプ
ロセスで製造する方法を与えることである。
(Problems to be Solved by the Invention) An object of the present invention is suitable for driving a liquid crystal when a peripheral drive circuit is configured by a single crystal Si drive circuit by using the technique of thinning the single crystal Si. It is to provide a method of manufacturing a thin film transistor by a simple process.

(発明が解決しようとする手段) 本発明によればSi基板上に選択研磨用絶縁層を形成す
る工程と、該絶縁層上に多結晶Si薄膜を形成し必要以
外の多結晶Si薄膜を除去し島状化する工程と、該島状
の多結晶Si層にソース、ドレイン領域を含むTFTを
形成する工程と、形成された該TFT側に透明絶縁性基
板を接着する工程と、Si基板を研摩加工して除去し、
選択研磨用絶縁層と該TFT及び透明絶縁性基板を残し
て薄膜化する工程と、該選択研磨用絶縁層に穴をあけT
FTのソース、ドレイン層と電気的接触せしめるように
ソース、ドレイン電極を形成する工程とを少くとも含む
ことを特徴とする薄膜トランジスタの製造方法が得られ
る。
(Means to be Solved by the Invention) According to the present invention, a step of forming an insulating layer for selective polishing on a Si substrate, a polycrystalline Si thin film is formed on the insulating layer, and the unnecessary polycrystalline Si thin film is removed. Island-shaped step, a step of forming a TFT including source and drain regions in the island-shaped polycrystalline Si layer, a step of adhering a transparent insulating substrate to the formed TFT side, and a Si substrate Remove by polishing
A step of thinning the selective polishing insulating layer, the TFT and the transparent insulating substrate, and forming a hole in the selective polishing insulating layer T
A method of manufacturing a thin film transistor, which comprises at least a step of forming source and drain electrodes so as to make electrical contact with the source and drain layers of FT.

(作用) 上述した構成から分るように、従来の技術でプライナー
構造のトランジスタで行われた2回のデバイス転写が本
発明では1回で良くプロセスが簡略化されている。ま
た、この製造方法で作製された薄膜トランジスタは、デ
バイス全体が透明接着層によって透明絶縁性基板に接着
されている構造となるため、透明絶縁性基板から入射し
た光は吸収がほとんどなく、透過型液晶ディスプレイと
して最適な構造である。
(Operation) As can be seen from the above-described configuration, the device transfer performed twice in the transistor of the planer structure in the conventional technique can be performed once in the present invention, and the process is simplified. In addition, since the thin film transistor manufactured by this manufacturing method has a structure in which the entire device is bonded to the transparent insulating substrate by the transparent adhesive layer, light incident from the transparent insulating substrate hardly absorbs, and the transmissive liquid crystal It is the most suitable structure for a display.

また、従来構造の多結晶Si薄膜トランジスタと比べて
ドレイン配線とゲート配線が比較的厚い平坦な素子分離
用絶縁膜によって簡単に多層配線され、電極間の短絡等
の画素欠陥の恐れの少ない薄膜トランジスタアレイが得
られる。
In addition, a thin film transistor array in which the drain wiring and the gate wiring are easily multilayered by a flat element isolation insulating film which is relatively thick as compared with the conventional polycrystalline Si thin film transistor, and there is less risk of pixel defects such as short circuit between electrodes. can get.

(実施例) 本発明の実施例を図面を用いて説明する。第1図(a)〜
(e)に本発明の薄膜トランジスタの製造方法の一実施例
を示す。第1図において、p型Si基板1に選択研磨用
絶縁層2として熱酸化膜を700nm形成したのち、Si
H4ガスを用いた低圧CVD法により多結晶Si膜3を1
50nm形成し、島状にパターニングする(第1図
(a))。続いて、ゲート絶縁膜4として熱酸化膜を多結
晶Si膜3上に150nm形成し、さらに、この熱酸化
膜4の上に多結晶Si膜を300nm成膜し島状にパタ
ーニングしてゲート電極5を形成する。さらに160K
Vの加速電圧で5×1015cm-2の燐をゲート電極をマス
クとして用いて多結晶Si膜3に注入し、900℃,2
0分間アニールして、ソース、ドレイン領域6,7を形
成する。さらにゲート電極7としてAlを0.3nm形成し
パターニングする。その後、保護層としてCVD法によ
りSiO2膜8を500nm形成し800℃,30分アニー
ルしMOSFET構造にする(第1図(b))。
(Example) The Example of this invention is described using drawing. Figure 1 (a) ~
An example of the method of manufacturing a thin film transistor of the present invention is shown in (e). In FIG. 1, a p-type Si substrate 1 was formed with a 700 nm thermal oxide film as an insulating layer 2 for selective polishing.
The polycrystalline Si film 3 is formed by a low pressure CVD method using H 4 gas.
It is formed to a thickness of 50 nm and patterned in an island shape (Fig. 1
(a)). Then, a thermal oxide film is formed as a gate insulating film 4 on the polycrystalline Si film 3 to a thickness of 150 nm, and a polycrystalline Si film is formed to a thickness of 300 nm on the thermal oxide film 4 to form an island pattern to form a gate electrode. 5 is formed. Further 160K
Phosphorus of 5 × 10 15 cm -2 was injected into the polycrystalline Si film 3 by using the gate electrode as a mask at an accelerating voltage of V, and the temperature was set to 900 ° C. for 2 hours.
Anneal for 0 minutes to form the source and drain regions 6 and 7. Further, 0.3 nm of Al is formed as the gate electrode 7 and patterned. Then, a SiO 2 film 8 having a thickness of 500 nm is formed as a protective layer by the CVD method and annealed at 800 ° C. for 30 minutes to form a MOSFET structure (FIG. 1 (b)).

更に、透明接着材9(たとえばエポキシ樹脂)を用いて
MOSFETが形成されたSi基板をゲート電極4がガラス等
の透明絶縁性基板10と貼りあわせられるように接着す
る(第1図(c))。この後、Si基板1は化学研磨を用
いて除去し、薄膜化する(第1図(d))。化学研磨時の
研磨材としては20nm径の石英粒と有機アンモニアを
用いた。これにより、Si結晶1の方が選択研磨用絶縁
層2よりも約10倍研磨スピードが速くなり選択研磨用
絶縁層2の厚さで自動的に研磨が終了する。さらに、ド
ライエッチングによりコンタクトホールを選択研磨用絶
縁層2に開けた後、Alを800nm形成し島状にパタ
ーニングして400℃30分間アニールする。これによ
り、ソース、ドレイン電極11,12を形成すると同時
にソースドレイン領域6,7と電気的接続を図る(第1
図(e))。更に、液晶ディスプレイ用薄膜トランジスタ
アレイを形成する場合には、第2図に示すようにソース
電極12と接続されるように透明電極13として酸化イ
ンジウム(ITO)をスパッタ法で100nm形成し、
パターニングして画素電極を形成し、ディスプレイ用薄
膜トランジスタ(第2図)が完成される。
Furthermore, using a transparent adhesive 9 (for example, epoxy resin)
The Si substrate on which the MOSFET is formed is bonded so that the gate electrode 4 can be bonded to the transparent insulating substrate 10 such as glass (FIG. 1 (c)). After that, the Si substrate 1 is removed by chemical polishing to form a thin film (FIG. 1 (d)). Quartz grains with a diameter of 20 nm and organic ammonia were used as abrasives during chemical polishing. As a result, the polishing speed of the Si crystal 1 is about 10 times faster than that of the insulating layer 2 for selective polishing, and polishing is automatically completed with the thickness of the insulating layer 2 for selective polishing. Further, after forming a contact hole in the insulating layer 2 for selective polishing by dry etching, Al is formed to a thickness of 800 nm, patterned into an island shape, and annealed at 400 ° C. for 30 minutes. As a result, the source and drain electrodes 11 and 12 are formed, and at the same time, the source and drain regions 6 and 7 are electrically connected (first
(Figure (e)). Further, when forming a thin film transistor array for a liquid crystal display, as shown in FIG. 2, indium oxide (ITO) is formed to a thickness of 100 nm as a transparent electrode 13 by a sputtering method so as to be connected to the source electrode 12.
A pixel electrode is formed by patterning, and a thin film transistor for display (FIG. 2) is completed.

(発明の効果) 本発明による薄膜トランジスタの特性を調べた結果、移
動度〜10cm2/v・sec,OFF電流0.8〜4x10-12Aと液晶デ
ィスプレイ用として十分な性能を有する薄膜トランジス
タが簡単なプロセスで得られ、また、通常のSiFET
プロセスと類似しているため単結晶Siを周辺駆動回路
として使用することができることが確認できた。また、
光透過率も80%以上の透明性を有する高性能薄膜トラ
ンジスタが得られた。
(Effects of the Invention) As a result of investigating the characteristics of the thin film transistor according to the present invention, a thin film transistor having a mobility of 10 cm 2 / v · sec, an OFF current of 0.8 to 4 × 10 −12 A and sufficient performance for a liquid crystal display can be obtained by a simple process. Obtained, and also ordinary SiFET
It was confirmed that single crystal Si can be used as a peripheral drive circuit because the process is similar. Also,
A high performance thin film transistor having a light transmittance of 80% or more was obtained.

尚、本発明は実施例に限らず他の構造のトランジスタに
も有効である。
The present invention is not limited to the embodiment and is effective for transistors having other structures.

【図面の簡単な説明】[Brief description of drawings]

第1図(a)〜(e)は本発明の薄膜トランジスタの製造方法
の一実施例を示す工程図。第2図は本発明の製造方法に
より得られた薄膜トランジスタの概略図である。 図において、 1……単結晶Si基板、2……選択研磨用絶縁層、3…
…多結晶Si膜、4……ゲート絶縁膜、5……ゲート電
極、6……ドレイン領域、7……ソース領域、8……保
護層、9……接着層、10……ガラス等の透明絶縁基
板、11……ドレイン電極、12……ソース電極、13
……透明画素電極をそれぞれ示す。
1 (a) to 1 (e) are process diagrams showing an embodiment of a method of manufacturing a thin film transistor of the present invention. FIG. 2 is a schematic view of a thin film transistor obtained by the manufacturing method of the present invention. In the figure, 1 ... Single crystal Si substrate, 2 ... Insulating layer for selective polishing, 3 ...
... Polycrystalline Si film, 4 ... Gate insulating film, 5 ... Gate electrode, 6 ... Drain region, 7 ... Source region, 8 ... Protective layer, 9 ... Adhesive layer, 10 ... Glass transparent Insulating substrate, 11 ... Drain electrode, 12 ... Source electrode, 13
...... Indicates transparent pixel electrodes, respectively.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】Si基板上に選択研磨用絶縁層を形成する
工程と、該絶縁層上に多結晶Si薄膜を形成し必要以外
の多結晶Si薄膜を除去し島状化する工程と、該島状の
多結晶Si層にソース、ドレイン領域を含むTFTを形
成する工程と、形成された該TFT側に透明絶縁性基板
を接着する工程と、前記Si基板を研摩加工して除去
し、該選択研磨用絶縁層と該TFTと透明絶縁性基板を
残して薄膜化する工程と、該選択研磨用絶縁層に穴をあ
け該TFTのソース、ドレイン層と電気的接触せしめる
ようにソース、ドレイン電極を形成する工程とを少くと
も含むことを特徴とする薄膜トランジスタの製造方法。
1. A step of forming an insulating layer for selective polishing on a Si substrate, a step of forming a polycrystalline Si thin film on the insulating layer and removing an unnecessary polycrystalline Si thin film to form islands, A step of forming a TFT including a source / drain region on an island-shaped polycrystalline Si layer; a step of adhering a transparent insulating substrate to the formed TFT side; and a step of removing the Si substrate by polishing, A step of thinning the selective polishing insulating layer, the TFT and the transparent insulating substrate, and a source / drain electrode for making a hole in the selective polishing insulating layer to make electrical contact with the source / drain layer of the TFT. And at least a step of forming a film.
JP523388A 1988-01-12 1988-01-12 Method of manufacturing thin film transistor Expired - Lifetime JPH0642494B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP523388A JPH0642494B2 (en) 1988-01-12 1988-01-12 Method of manufacturing thin film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP523388A JPH0642494B2 (en) 1988-01-12 1988-01-12 Method of manufacturing thin film transistor

Publications (2)

Publication Number Publication Date
JPH01181570A JPH01181570A (en) 1989-07-19
JPH0642494B2 true JPH0642494B2 (en) 1994-06-01

Family

ID=11605470

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JPH0642494B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7167993B1 (en) 1994-06-20 2007-01-23 Thomas C Douglass Thermal and power management for computer systems

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Publication number Priority date Publication date Assignee Title
TW487958B (en) * 2001-06-07 2002-05-21 Ind Tech Res Inst Manufacturing method of thin film transistor panel
JP4019305B2 (en) * 2001-07-13 2007-12-12 セイコーエプソン株式会社 Thin film device manufacturing method
JP2003142666A (en) * 2001-07-24 2003-05-16 Seiko Epson Corp Element transfer method, element manufacturing method, integrated circuit, circuit board, electro-optical device, IC card, and electronic equipment
JP2004349513A (en) * 2003-05-22 2004-12-09 Seiko Epson Corp Thin film circuit device and method for manufacturing the same, electro-optical device, and electronic equipment
JP2005283688A (en) * 2004-03-29 2005-10-13 Ishikawa Seisakusho Ltd Method for manufacturing pixel control element forming substrate and flat display produced by the method
JP4940402B2 (en) * 2004-10-19 2012-05-30 セイコーエプソン株式会社 Method for manufacturing thin film device
KR101272097B1 (en) 2005-06-03 2013-06-07 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Integrated circuit device and manufacturing method thereof
US7820495B2 (en) 2005-06-30 2010-10-26 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US8105887B2 (en) * 2009-07-09 2012-01-31 International Business Machines Corporation Inducing stress in CMOS device
US20140124785A1 (en) * 2011-06-15 2014-05-08 Sharp Kabushiki Kaisha Semiconductor device and method for manufacturing same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7167993B1 (en) 1994-06-20 2007-01-23 Thomas C Douglass Thermal and power management for computer systems

Also Published As

Publication number Publication date
JPH01181570A (en) 1989-07-19

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