JPH0642671B2 - Data transmission device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission device, and more particularly to a data transmission device in which each of a plurality of data transmission devices connected by a bus type transmission line can exchange data in real time.

[Technical background of the invention and its problems]

In a transmission system in which a large number of transmission stations are connected by a bus type transmission line, it is easy to add or remove a transmission station, and since the failure of one transmission station does not spread to the entire system, it can be used in a relatively short distance. It is widely used as a transmission system.

Various methods have been considered as a method of controlling the transmission path use right of a data transmission device used in this type of transmission station, but the following two types are typical.

(1) CSMA / CD method (2) Token pass method CSMA / CD is Caria Sensa Multi Acces / Collision Detec
An abbreviation of t, represented by XEROX Ethernet, is a method in which each station freely uses the bus, but while there is little transmission data, there is no collision of transmission requests of each station, it is efficient, but collision occurs when transmission requests overlap. However, there is a drawback that the waiting time increases immediately. In a transmission station that requires real time, it is necessary to surely process a transmission request of an arbitrary station within a certain time, and this method is not suitable for a data transmission device that requires real time.

On the other hand, the token pass method is a method of transmitting a token packet which is typified by an arcnet of US data points and permits transmission so that batons are sequentially passed to each transmission station. When each transmission station receives the token packet, it acquires the right to use the transmission path, and if there is transmission data, it transmits the data to an arbitrary station, and when it is completed, it transmits the token packet to the next transmission station. Hand over. In this method, if the maximum data transmission amount at each transmission station is specified, the transmission service can be received within a fixed time, so that there is real-time property. However, in this method, token packets are passed one after another, so the transmission efficiency is not good and even when there is no transmission request, the micro computer that controls the transmission to receive the token packet and to send it further always processes these. However, there is a drawback that so-called overhead is increased.

Hereinafter, the token pass method will be described in detail with reference to the drawings. FIG. 1 shows each station (# 1 to # 1) on the bus 1.
4) Shows a state in which 2, 3, 4, 5 are connected. A station or station shall mean a transmission device here.

FIG. 2 is a block diagram of a transmission device using the token path method. In the figure, a transceiver circuit (TR) 6 connected to the bus 1
Receives a serial signal on the bus 1 and converts it to a logic level, or amplifies the logic level signal and sends it out on the bus 1 as a serial signal. The encoder / decoder (ED) 6A inputs normal digital data to TR6 as a logic level signal obtained by converting the digital data into a digital data munchister code including a clock component, or conversely inputs a munchiesta code logic level signal from TR6. Is converted to a normal digital signal. The transmission / reception control circuit 7 uses the CSMA / CD system or HDLC (High
Level Data Link Controt) method controls the send / receive data according to the communication protocol and generates an interrupt to CPU9, memory
Performs DMA (Direct Memory Acces) to (M) 8. In addition, an I / O 11 is provided if necessary, and these are connected by the control signal bus 10.

FIG. 3 is a time chart showing an example of a serial signal transmitted by each of the stations # 1 to # 4 when the transmission system is composed of four stations as described above. The first signal of station # 1 has no data to be transmitted, and only the token pass signal (TP) 13 is sent out on the bus. This TP13 designates station # 2, and when station # 2 receives this TP13, the transmission / reception control circuit 7 generates an interrupt, and the CPU 9 accepts this and determines that it is a token pass signal, and transmits it to the own station. Get the right to use the road.
Then, the data to be transmitted is transmitted to the bus as a data packet 18 via the transmission / reception control circuit 7, and then the TP14 designating the station # 3 is transmitted. Thereafter, in the same manner, the transmission channel use right is sequentially transferred to the stations # 3 and # 4, and the transmission right is returned to the station # 1. In FIG. 3, since there is no data to be transmitted even in station # 4, only the token pass signal 16 is transmitted. Thus, even when there is no data to be transmitted, it is necessary to send a token pass signal designating the next station in order to ensure real-time processing. This processing requires a processing time of 50 to 100 μs even with the current high-performance 16-bit microprocessor (for example, 8086 manufactured by Intel), and signals on the bus often cause wasteful time with no data and also the microprocessor. There is a problem that the overhead becomes large.

Further, as the LSI having the function of the transmission / reception control circuit 7, there are the LSI for CSMA / CD and the LSI for HDLC as described above, and the transmission station is easily configured by combining the transceiver for transmission / reception and the microcomputer for controlling the transmission flow. However, there is a problem that these LSIs do not have a function for controlling a transmission path.

[Object of the Invention]

The present invention has been made in view of the above circumstances, and an object thereof is a data transmission system in which each of a plurality of data transmission devices coupled to a bus type transmission line can exchange data,
A commercially available transmission control LSI is used, and a transmission path control additional circuit is provided, which has better transmission efficiency than the conventional token path method and has real-time characteristics. Even when it is added to a transmission device, it is used as software on the micro computer side. It is an object of the present invention to provide a data transmission device that can be easily added without affecting.

[Outline of Invention]

In order to achieve the above object, the present invention provides a data transmission device in which a plurality of transmission devices perform mutual transmission via a bus type transmission line, in which data is transmitted between a CSMA / CD or HDLC transmission control LSI and a transmission / reception circuit. An additional circuit for path control is provided. The additional circuit for transmission path control serves as a master station, a frame header for instructing the packet transmission timing, a dummy packet indicating that there is no data to be transmitted, and a dummy packet on the bus for a predetermined time or more. When there is no transmission signal, the transmission means for transmitting three kinds of transmission path control packets, which instead represents as a master station, is provided as the master station, and the frame header, the dummy packet, and the substitute packet are the headers of the data packet by the CSMA / CD or HDLC method. A packet format having a pattern different from that of the Ding format is used, and reception of the three types of transmission path control packets is performed. Transmission path control packet determination means, transmission path usage right determination means for starting transmission when a predetermined number of packets are received after receiving the frame header, setting switch for setting various constants for transmission path control, and A register for holding the setting value of the setting switch and an initial setting circuit for reading the setting value of the setting switch into the register are provided so that transmission efficiency is good and it can be easily added without affecting the software on the microcomputer computer side. Data transmission device.

Example of Invention

An embodiment of the data transmission device of the present invention is shown in FIG.
In FIG. 4, 1 is a bus type transmission line, and 6 is a transmission / reception circuit.
(TR), 8 is a memory (M), 9 is a central processing unit (CPU), 10
Is a control signal bus, 11 is a peripheral device and other input / output circuits (I /
O), 38 are additional circuits for transmission control, and 76 is an LSI for transmission control.

FIG. 5 is a detailed block diagram of the transmission control additional circuit 38, which shows three types of transmission control packets (frame headers).
(FH), dummy packet (DP), proxy packet (RP)) and the function of sending these packets, and when these packets are received, they are discriminated from each other and predetermined control (described later) is performed.

FIG. 6 is a time chart for explaining the operation of the data transmission apparatus of the present invention, which shows four transmission stations # 1 to #.
4 is an example in which the transmission system is configured by 4 and the # 1 station is the master station.

First, the master station (# 1 station) is Frame Hedda (FH)
21 is sent to a bus type transmission line (hereinafter simply referred to as a bus) 1. The other transmission stations # 2 to # 4 which have received this transmit the data to be transmitted by their own stations to the bus 1 as a data packet (DT) in a "precious" manner in a predetermined station order. If there is no data to send, it sends a dummy packet (DP). FIG. 6 shows # 1, # 2, # 3.
When the transmission order is determined in the order of # 4 stations, the stations # 1 and # 4 are DP22 in the first transmission cycle.
Is an example in which the stations # 2 and # 3 send out DT23, 24. When all the transmission stations make a round of transmission, the master station again sends out the frame header (FH) 21 to start the next transmission cycle. In this way, all transmission stations can send out their own data within a fixed time.

When an arbitrary transmission station becomes untransmittable for some reason, the master station detects that the packet is not sent for a certain period of time and sends a substitute packet (RP) to prevent the transmission system from stopping.

An example of the format of the data packet (DT) is shown in FIG. In the figure, 70 is a heading for synchronization.
(H), 71 is the destination address (DA), 72 is the source address (S
A), 73 is type field (TYP) or command (CMD),
74 is data (DATA), 75 is a frame check sequence (F
CS) and these form one data packet (DT). This data packet (DT) is CSMA / CD method or HDLC
It conforms to the communication protocol of the method.

Heading (H) 70 is 0101… and “1” in CSMA / CD system
And “0” are repeated alternately. Finally, 1011 and “1” are 2
Consists of less than 64 bits at the end. In the HDLC method, an 8-bit flag "7E" is used.

The three types of transmission control packets are defined by formats having conditions other than the pattern format of the above-mentioned heading (H) 70. For example, if a packet for transmission control is composed of 16 bits, frame header (FH) ... 3FCO dummy packet (DP) ... 3FFO proxy packet (RP) ... 3FFC is defined. When this packet is received, it is for transmission control.
It makes senseless data for LSI76. As a result, each transmission control LSI 76 can output and receive a signal 70 only when receiving a data packet (DT), interrupt input to the CPU 9, and perform data transmission / reception in the same manner as mutual one-to-one data transmission, The additional circuit 38 for transmission control efficiently controls the transmission line by the transmission control packet.

Hereinafter, a more detailed description will be given with reference to FIGS. 4 and 5. In the embodiment, an Intel 80186 is used as the CPU 9 and a transmission control LSI
When the data to be transmitted is on the memory (M) 8, the 82586 manufactured by the same company is used for the 76, and the CA signal (not shown) of the transmission control LSI 76 is set and notified via the control signal bus 10. As a result, the LSI 76 takes in the data in the memory (M) 8 and activates the transmission request signal (▲ ▼) 35.
Transmission line control addition circuit 38
Notify me and wait.

In the figure, a signal with a bar (-) above each of the English character signals indicates negative logic, and is "0" when active (energized).
A signal without a bar indicates positive logic and is "1" when activated.
Is shown.

On the other hand, serial data transmitted from another station via the bus 1 is received by the transmission / reception circuit (TR) 6 and input as the reception signal (RCV) 36 of the transmission path control addition circuit 38. The received signal is returned to the NRZ signal by the decoder (DEC) 40, separated into the received clock (▲ ▼) 30 and the received data (RXD) 31, extracted and input to the transmission control LSI 76. The received data (RXD) 31 is also input to the frame header detection circuit (FHD) 43, and when it is determined that it is a frame header, a reset signal
58 is output and the slot counter (SLC) 45 is reset. The FHD43 has a shift register inside, and the received data (RXD) 31 is loaded into this shift register to determine whether it is a combination of "0" and "1" bits (3FCO in the example of 16 bits). Judge to detect the frame header (FH).

The carrier detection circuit (CS) 41 detects the presence or absence of the reception signal (RCV) 36, and outputs the carrier detection signal 57 when the RCV 36 is present. This carrier detection signal 57 is input to the timer (TD) 44, and its output signal 59 is an off-delay signal which disappears after a certain period of time after the carrier detection signal 57 disappears.
Is incremented when this signal 59 changes from active to non-active. That is, the SLC 45 is reset when a frame header is detected, incremented to "1" when a fixed time elapses without the frame header, and then incremented after a fixed time elapses from the completion of reception of each packet.

The count value 60 of the SLC 45 is input to the coincidence detection circuit (COIN) 46 and compared with the station number signal 61 set by the station number setting register 48. If the station number signal 61 is set to "1", the SLC becomes "1" after a fixed time from the end of FH21 shown in FIG. 6, so that the COIN 46 outputs the coincidence detection signal 63 at this time. Transmission control circuit
When the transmission request signal (▲ ▼) 35 input from the LSI 76 is active when the signal 63 is active, the 56 activates the transmission permission signal (▲ ▼) 34 to permit the LSI 76 to transmit. Also, this transmission permission signal
(▲ ▼) 34 is also input to the transmission data control circuit 55 at the same time, whereby the clock signal from the clock generating circuit (not shown) is frequency-divided and a transmission clock (▲ ▼) 32 is output and supplied to the LSI 76. The transmission control LSI 76 is a memory (M)
The data fetched from 8 is output as the transmission data (TXD) 33 synchronized with the transmission clock (▲ ▼) 32. The transmission data control circuit 55 receives the transmission data (TXD) 33 and outputs the input signal 67 to the encoder (ENC) 42, and the ENC 42 transmits the transmission data.
(TXD) 33 converted to Mantiester code and transmitted signal (TRM)
The signal output as 37 and amplified via the transmission / reception circuit (TR) 6 is sent to the path 1 as the above-mentioned data packet DT.

Transmission request signal when the match detection signal 63 becomes active
If the (RTS) 35 is non-active, the transmission control circuit 56 outputs a dummy packet transmission request signal 68 to the dummy packet transmission circuit (DMS) 54, and the DMS 54 sends the above-mentioned dummy packet (DP) to the bus 1 via ENC42 and TR6. ) Is sent.

The count value 60 of the SLC 45 is also input to another coincidence detection circuit 47 and compared with the set value 62 set by the station maximum number setting register WRI49. This set value 62 is set in WRI49 of the station designated as the master station and the total number of stations +
Set to 1. In the embodiment shown in FIG. 6, station # 1 is used.
(WRI) 49 of is set to “5”, and after the reception of the transmission data of the final station (station # 4 in FIG. 6) is completed, the count value 60 becomes “5” after a fixed time, so the CO
The IN47 outputs the coincidence detection signal 64. This signal 64 causes the master station (station # 1) to send the frame header transmission circuit (F
HS) 52 is activated, the above frame header (FH) is sent to bus 1 via ENC42 and TR6, and all stations
Reset SLC to "0".

The carrier detection signal 57 of the carrier detection circuit (CS) 41 is also input to the substitute packet transmission timer (RPT) 51, and when the carrier detection signal 57 is not detected for a certain period of time, the substitute packet transmission request signal 66 is output to output the substitute packet transmission circuit. 53 is started, and the above-mentioned proxy packet (R
P) is sent. This function allows the master station to send a substitute packet in place of the station when the station cannot be transmitted due to a failure or some reason, so that data transmission can be performed only by the remaining healthy stations.

Further, the frame header detection signal 58 of the frame header detection circuit (FHD) 43 is also input to the frame header loss timer (FHLT) 50, and when the frame header is not received within a certain time, the FHLT 50 outputs the frame header transmission request signal 65 and outputs the frame header. The sending circuit (FHS) 52 is activated to send the frame header. The fixed time Td monitored by the FHLT50 is slightly different depending on the station Td = a + b. n
(However, n is the station number and a and b are constants). With this function, when the master station fails and the frame header cannot be transmitted, the station with the lowest number automatically transmits the frame header on behalf of the master station, and when the station with the lowest number also fails, the station with the next lowest number. The station will automatically transmit the frame header on behalf of.

Reference numeral 93 is a frame header (FH) transmission external synchronization circuit (FHSYN), which issues a frame header transmission request in response to a frame header transmission external synchronization command 15 and transmits the frame header from the FHS 52.
As a result, the transmission cycle of the data packet of the entire transmission system can be synchronized with the special signal and transmitted at a constant cycle.

Reference numeral 83 indicates the station number to be monitored by the monitor operation designation register (WR3). When the count value 60 of SLC45 reaches this value, the coincidence detection circuit 88 outputs a monitor operation command. A monitor control circuit 87 has two operation modes, a CPU mode and an AUTO mode. In the CPU mode, the monitor data is set in the status read register (RR1) 86 by the above monitor operation command, and INT2 signal 71 after the monitor operation is completed. Is output and CPU9 is interrupted. In the AUTO mode, the monitor control circuit 87 outputs the monitor data to the data signal 12 via the output buffer 94.

Reference numeral 89 is a proxy packet detection circuit, 90 is a dummy packet detection circuit, and 91 is a data packet detection circuit, which are related to the above-mentioned monitor operation function. Here, the monitor operation function is capable of monitoring what packet the station having the station number designated in the setting register 83 is transmitting on the bus. That is, the packet on the bus is received, the above-mentioned circuits 89, 90, and 91 discriminate whether it is a proxy packet, a dummy packet, or a data packet, and the discrimination result is held at the timing corresponding to the designated station number. This is output as a monitor result. It is output to the D0-D7 bus 12 in correspondence with the auto mode or the computer mode (AUTO / CPU), or held in the read register RR1 86.

A collision detection circuit 92 detects a collision of packet transmission by a plurality of stations at the time of packet transmission. That is, the transmission packet timing from the local station is input from the frame header transmission circuit 52, the dummy packet transmission circuit 54, the proxy packet transmission circuit 53, and the transmission data control circuit 55, and the transmission timing from other stations is described above.
The packet collisions on the bus are detected by using the numbers 90 and 91. The frame header emitted by the master station is always received and detected at all stations at a predictable period. Therefore,
If the frame header is not detected for a certain period of time or more, it means that the master station function abnormality or transmission path abnormality has occurred.
Abnormality recovery means is required for the additional circuit for controlling the transmission path or the entire transmission device. In this case, the longest frame header monitoring period 106 in a normal state is set by the monitoring timer setting register (WR5) 85. In each station, the length of the data packet that can be transmitted at one time is finite, and when the transmission operation continues for a fixed time or more, it corresponds to the occurrence of an abnormality in the transmission control circuit. When the transmission time exceeds a certain time, it is necessary to forcibly terminate the transmission by the additional circuit for controlling the transmission path and pass the order of transmission to the next station to avoid congestion of the transmission path. In this case, the maximum transmission time 107 under normal conditions is also set in the monitoring timer setting register (WR5) 85. Also, since the common transmission path is a bus type, when a station located at one end of the bus transmits, a propagation time determined according to the bus length is required until the signal propagates to the station located at the opposite end. Yes, it takes about 5 μs / km.

Therefore, when the station located in contact with the station located at one end detects the end of packet reception from the immediately preceding station and immediately transmits it while starting the transmission, the station located near the opposite end and the station located near the station. Then, the two packets are clearly separated and reception detection cannot be performed. That is, the station needs to provide a space time for packet transmission corresponding to the propagation delay time determined according to the bus length. This value is set by the transmission control constant setting register (WR4) 84.

Here, as the above-mentioned additional circuit 38 for controlling the transmission path,
There is no separate type for the master station and the slave station, and the functions of the master station and the slave station are included in one transmission path control additional circuit 38. Whether to function as a master station or a slave station is determined by a setting value given to the additional circuit 38 for controlling the transmission path.
In particular, it is determined in principle by the station number (station number) and the conditions for setting up a transmission system consisting of a plurality of stations. Of course, it is possible to include the conditions of the master station and slave stations in the external switch conditions and limit one station as the master station. However, backup of the master station is essential, so only one station is the master station. There is no limitation.

Here, whether it becomes a master station or a slave station is related to the operation of the frame header loss timer FHLT50 and its set value.

That is, when the master station becomes abnormal, the function of each station to send packets to the bus stops. Therefore, each slave station verifies that the master station has stopped functioning by checking that the frame header appears on the bus regularly. , One station selected from the slave stations functions as an alternative master station. The detection of the loss of the frame header is performed by the frame header loss timer FHLT50 described above. This frame header loss timer FHLT5
As described above, the monitoring set time of 0 is different for each station number of each station, and the smaller the station number, the earlier the abnormality of the master station is detected, and the station functions as a substitute master station.

If all stations are powered on at the same time when the system is started up, the station with the smallest station number will detect the loss of the frame header earliest and become the master station. In addition, when the power is turned on one by one, the one with the earliest power turned on normally becomes the master station and transmits the frame header. Further, the frame header is periodically transmitted by transmitting a proxy packet to a station that is not connected to the system. Stations that are turned on one after another detect frame headers that have already been transmitted, and function as slave stations assuming that the master station is functioning normally.

When the mobile station becomes a slave station, the proxy packet transmission timer 51
Does not work.

As described above, it is necessary to give the setting necessary for transmission line control to the transmission line control additional circuit 38, and in the present invention,
A RESET initial setting circuit 17 is provided which automatically reads the setting state of the switch provided outside the additional circuit and sets it to the corresponding register inside.

The switches provided outside are 100A, 100B, 100C,
It is 100D, and the registers that read and set the status of each switch are (WR1) 49, (WR2) 48, and (WR4) 8 in Fig. 5, respectively.
4 and (WR5) 85. The setting values for WR1, WR2, WR4, WR5 are
When the transmission device is operating, there is no change and only the setting operation needs to be performed. Fig. 8 shows each switch 100A, 100B, 10
The timing when the set values of 0C and 100D are read into the transmission path control additional circuit 38 is shown. RESET 18 becomes active when the power of the transmission device is turned on, or when the CPU 9 outputs an initialization command. When RESET18 becomes active, each select signal ▲ ▼, ▲ ▼, ▲
▼, ▲ ▼ and each strobe signal ST1, ST2,
ST3, ST4 are subordinate connexion occurred to the timing of FIG. 8, each switch 100A, 100B, 100C, a data input terminal the contents of 100D _(D 0 _{~D 7)} 12 via corresponding registers WR1, W
Take in to R2, WR4, WR5. While the switch state is being read, the MON signal 14 is at the high level, indicating that the reading operation is in progress.

〔The invention's effect〕

According to the data transmission device of the present invention, a data transmission device of a bus type transmission line which has a transmission efficiency higher than that of the token path system and which can be applied in real time is a commercially available LSI for data ring control such as LSI for CSMA / CD or LSI for HDLC. It can be easily realized by using, and the set values required for transmission control are automatically read and controlled by controlling the switch status, so the transmission line control can be performed without affecting the software on the microcomputer side. This is a data transmission device in which a circuit can be added and which can be easily realized.

[Brief description of drawings]

FIG. 1 is a general configuration diagram of a data transmission system using a bus type transmission line, FIG. 2 is a configuration diagram of a conventional data transmission device,
FIG. 3 is a time chart for explaining the operation of a conventional data transmission apparatus using the token path system, FIG. 4 is a block diagram of an embodiment of the data transmission apparatus of the present invention, and FIG. 5 is an additional circuit for controlling a transmission line. 38 detailed block diagram, Figure 6,
FIG. 8 is a time chart for explaining the operation of the present invention, and FIG. 7 is a configuration diagram of a data packet (DT). 1 ... Bus type transmission line, 2-5 ... Transmission station 6 ... Transceiver, 8 ... Memory circuit (M) 9 ... Central processing unit (CPU), 11 ... I / O circuit 17 ... RESET Initial setting circuit 38 …… Additional circuit for transmission path control, 76 …… Transmission control LSI 48 …… Station number setting register (WR2) 49 …… Station maximum number setting register (WR1) 84 …… Transmission control constant setting register ( WR4) 85 …… Monitoring timer setting register (WR5) 100A to 100D …… Setting switch

Claims (1)

[Claims] 1. A data transmission apparatus comprising a plurality of stations which are mutually connected via a bus type transmission line and serve as a master station or a slave station depending on a start-up condition, and these stations mutually transmit data. Station is CS
A transmission path control additional circuit is provided between the MA / CD or HDLC transmission control LSI and the transmission / reception circuit, and the transmission path control additional circuit includes a frame header for instructing packet transmission timing as a master station, and a master. In both the case of a station and a slave station, there is a dummy packet indicating that there is no data to be transmitted and a proxy packet indicating that when there is no transmission signal on the bus for a predetermined time or more as a master station. Three types of transmission path control packet transmission means are provided, and the frame header, the dummy packet, and the proxy packet have a packet format having a pattern different from the heading format of the data packet according to the CSMA / CD or HDLC method. A transmission path control packet discriminating means for discriminating the reception of the transmission path control packet; Transmission path usage right deciding means for starting transmission when a predetermined number of packets are received after receiving a frame header, and a monitoring cycle of the frame header in a normal time, which serves as a judgment criterion for the master station or transmission path abnormality, and once. A register in which various constants for transmission path control are set, including a maximum transmission time of a data packet that can be transmitted to a packet, a space time for packet transmission determined according to a propagation delay time determined by the length of the bus, and an external A data transmission device, comprising: an initial setting circuit for reading the various constants set in a switch into the corresponding registers.