JPH0644165B2 - Electronic copier control device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic copying machine control device, and in particular, it uses a small number of signal wires to transfer information between a plurality of input / output devices and a control unit. The present invention relates to an electronic copying machine control device adapted to exchange data.

(Prior Art) Various types of equipment such as electronic copying machines
With higher performance, various electric and electronic parts have come to be widely used as input / output devices.

The outline of one example is shown in FIG.

The central control device 30 may be a general-purpose device that is quite commonly known, and for example, a CPU 31 that executes various calculations for control, an R that mainly stores a control program, and the like.
The OM 32 is mainly composed of a RAM 33 for storing data and intermediate calculation results, a common bus 34 for transmitting information between the three parties, and an input / output interface 36 connected to the common bus 34.

Further, the input / output interface 36 includes various output devices such as clutches, solenoids, and relays, or loads 1.
0, and various detection sensors such as micro switches or input devices 11 are connected.

Needless to say, the load 10 and the detection sensor 11 are provided in an electronic copying machine which is a controlled device.

(Problems to be Solved by the Invention) As can be seen from FIG. 2, the load 10 and the detection sensor 11
Are connected to the input / output interface 36 by individual wire wiring pairs. Further, as the number of controlled devices increases and the number of performance sensors increases, the number of loads 10 and detection sensors 11 also increases.

Therefore, information detected by these components (for example, data detected by micro switches and various sensors) is transmitted to a control unit such as a microcomputer, or vice versa, various control signals obtained by the control unit are output. As a matter of course, the number of wires and the length of wiring for transmitting to the equipment will also increase.

As a result, not only the cost of the apparatus as a whole is increased, but also the reliability and maintainability of the apparatus are deteriorated.

The present invention has been made to solve the above problems.

(Means and Actions for Solving Problems) In order to solve the above problems, the present invention distributes an address / data bus whose one end is connected to a central control unit such as a microcomputer in an electronic copying machine. Wire them so that they pass near each I / O device that is placed, and exchange data and signals between each I / O device and the control unit in a time-division manner. It is possible to receive the detection signals from a large number of detection sensors by decoding the data and controlling the input interface to which the plurality of detection sensors are connected by the decoded output.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 3 is a schematic block diagram of an embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 2 represent the same or equivalent parts.

One end of the address / data bus 38 is connected to the common bus 34 in the central controller 30 via the bidirectional bus buffer 37. The address / data bus 38 is provided for each input / output device (for example, load 1) distributed in the electronic copying machine.
0, the detection sensor 11, etc.).

Then, from the address / data bus 38, branches B1, B2 ... B (n-1), B (n) each consisting of a decoding circuit 18 and an input / output interface 19 are provided.
Is branched, and the input / output interface 19
The detection sensor 11 and the load 10 are connected to the.

In FIG. 3, the address / data bus 38 can be composed of, for example, 12 signal lines, and its function sharing is designated as follows.

Signal line No. 0 to 7 ... Transmission of branch selection address, load on / off control data, and detection information by sensor Signal line No. 8, 9 ... Transmission of mode instruction (or designation) signals a and b Signal line No. 10: Transmission of strobe signal c Signal line No. 11 ... Transmission of Reset Signal FIG. 1 is a detailed block diagram of the decoding circuit 18 and the input / output interface 19 of FIG.

The bus buffer driver 20 receives the data transmitted on the address / data bus 38 from the address detection circuit 2
3, i / o program memory 26, and output latch 2
Transmit to 7.

The interface 21 supplies the mode instructing signals a and b and the strobe signal c to the decoder 24, and the interface 22 sends the reset signal to the control circuits 25 and i.
/ O to the program memory 26.

The address detection circuit 23 uses the bus buffer driver 20.
It is determined whether or not the address transmitted on the bus 38W via the address coincides with the own address 23A generated by the own address generator 29, and if they match, the address match signal 23B is output. .

The decoder 24 determines the operation mode of the input / output device or terminal based on the mode instruction signals a and b, and outputs control signals 24A (read data transmission), 24B (write data read) and 24C (program write). Occur.

The control circuit 25 controls the operation of the decoder 24 when the address match signal 23B is generated.

The i / o program memory 26 receives the program write signal 2
The program transmitted from the bus 38W is stored under the control of 4C.

The output latch 27 stores the data transmitted from the bus 38W under the control of the write data read signal 24B.
The buffer 28, in accordance with the program stored in the i / o program memory 26 (determines whether the terminal is an input or an output), transfers the data of the output latch 27 to the output interface 39 if necessary. To the load 10, the input interface selection decoder 42, etc.

The output interface 39 sends the data to the load 10 and inputs the input interfaces 41a and 41 to the input terminals a and b of the input interface selection decoder 42.
Sends data for selecting b, .... This data transmission is performed under the control of the write data read signal 24B.

The input interface selection decoder 42 operates when it is enabled by the read data sending signal 24A, and sends a signal according to the truth table of Table 1 to its output terminals A, B, C and D.

A maximum of eight detection sensors can be connected to each of the input interfaces 41a, 41b, ..., And when any one of the input interfaces 41a, 41b ,. The detection signal is read from the sensor. This detection signal is sent out onto the address / data bus 38 through the bus 38R.

Next, the operation of the embodiment of the present invention will be described with reference to the timing charts of FIG. 3, FIG. 1, and FIG.

(1) When the power is turned on, the reset signal is sent from the central control unit 30 onto the address / data bus 38.
As a result, the control circuit 25 and the i / o program memory 26 shown in FIG. 1 are all initialized.

The initialization of the i / o program memory 26 means that the buffer 28 is in the high impedance state, that is, the input mode.

(2) While the mode instruction signals a and b are both 0 and the strobe signal c is 1, the address / data bus 38 signal line No. An exclusive OR of the data on 0 to 7 and the self address 23A is executed by the address detection circuit 23.

If they match, then the address / data bus 38
The data transmitted over can be determined to be for itself. Therefore, the address match signal 23B is generated and held in the control circuit 25 for a necessary period.

In addition, the signal line No. of the address / data bus 38. 0-7
When the above data and the self address 23A do not match, the control circuit 25 does not operate.

(3) If the mode designating signals are a = 0 and b = 1, it means the program mode, and the address / data bus 38 has
Program data that determines the input / output mode of this terminal is transmitted.

Therefore, in this state, when the address coincidence signal 23B is further determined in the determination of (2), the decoder 24 sets the program write signal 24C to 1 while the strobe signal c is 1.

As a result, the data (program) on the bus 38W becomes i
/ O is stored in the program memory 26, and the input / output mode of the buffer 28 is set.

(4) Even in the next writing mode (Fig. 4),
The same judgment as in (2) is performed, and the address / data bus 38
Determine if the above data is for itself.

(5) If the mode instruction signals are a = 1 and b = 0, it means the write mode, and the write data is transmitted on the address / data bus 38.

Therefore, when the address match signal 23B is present and the strobe signal c is 1, the decoder 24 sets the write data read signal 24B to 1.

As a result, the data on the bus 38W is stored in the output latch 27, and the data is further transferred to the buffer 28.

At this time, if the terminal is instructed to be in the output mode by the program in the process of (3), the buffer 28
And “1” or “0” is output to the output terminal via the output interface 39. In this way
The load 10 becomes controlled based on the data on the bus 38W.

(6) Even in the read mode of FIG. 4, first, the same judgment as in (2) above is performed to judge whether the data on the address / data bus 38 is addressed to itself.

(7) If both the mode designating signals a and b are 1, it means the read mode. When the address match signal 23B is present and the strobe signal c is 1, the decoder 24
Sets the read data transmission signal 24A to 1.

As a result, the input interface selection decoder 42
Is enabled, and the input interface selection decoder 42 outputs a signal according to Table 1 from the output terminal based on the data obtained in the previous write mode. When a certain input interface is turned on by the signal, the detection signal is read from the detection sensor connected to the input interface, and the detection signal is the bus 38R.
And via bus 38 to central controller 30.

FIG. 5 is a schematic block diagram showing an example of the input interface selection decoder 42. It will be obvious, of course, that this circuit operates according to the truth table shown in Table 1.

In the above embodiment, 2 bits (out O, OUT 1) of the input / output interface 19 are used for controlling the input interface selection decoder 42, but the present invention is not limited to this, and the input / output interface is not limited to this. 8 of 19
Decoder 42 for inputting all bits
Can be used for control of. In this case, a maximum of 8 × 2 ⁸ detection sensors can be connected.

(Effect) As is apparent from the above description, according to the present invention, one address / data bus 38 is provided in the controlled electronic copying machine, and a required number of branches are arranged at appropriate places near the input / output device. , The decoding circuit in this branch decodes the data transmitted from the central control unit on the address / data bus 38 in a time division manner, and in accordance with the result, the address included in the data is matched with that of its own. At this time, the load 10 connected to each branch is drive-controlled or the detection information of the detection sensor 11 is sent to the central control device 30, so that the number of wirings is different from the conventional configuration. And the length can be reduced.

Moreover, since it is not necessary to increase the number of wires even if an input / output device is added, it is extremely easy to add an input / output device by preparing an extra branch or providing a connection part in advance. Can be done.

Furthermore, according to the present invention, the input / output interface 19
If the bus is 8 bits to be input, to the control of the equipment a large number of detection sensors for connect a number of sensor up to 2 ⁸ Up 8 × very effective in.

[Brief description of drawings]

FIG. 1 is a detailed block diagram of a decoding circuit and an input / output interface in FIG. 3, FIG. 2 is a block diagram showing a schematic configuration of a conventional electronic copying machine control device, and FIG. 3 is an outline of an embodiment of the present invention. FIG. 4 is a block diagram, FIG. 4 is a timing chart for explaining the operation of FIG. 1, and FIG.
FIG. 4 is a detailed block diagram of the input interface selection decoder shown in FIG. 10 ... Load, 11 ... Detection sensor, 18 ... Decode circuit, 19 ... Input / output interface, 20 ... Bus buffer driver, 21, 12 ... Interface, 23 ... Address detection circuit, 24 ... Decoder Two
5 ... control circuit, 26 ... i / o program memory, 2
7 ... Output latch, 28 ... Buffer, 29 ... Self-address generator, 30 ... Central control unit, 31 ... CP
U, 32 ... ROM, 33 ... RAM, 37 ... Bidirectional bus buffer, 39 ... Output interface, 41a
~ 41d …… Input interface, 42 …… Decoder for selecting input interface

Claims (1)

[Claims] 1. A central control unit comprising a CPU, a ROM, a RAM and a common bus for exchanging information between them, one end of which is connected to the common bus via a bus buffer and the other end of which is a controlled electronic device. Address extended in the copier /
A data bus and a plurality of input / output devices in the controlled electronic copying machine, and the address / data bus and the plurality of input / output devices for connecting the plurality of input / output devices to the address / data bus. An electronic copying machine control device comprising a plurality of branch means connected to an output device, wherein the branch means captures information transmitted on the address / data bus, and the branch means takes its own function. Means for deciding whether or not it is addressed to the station, an output interface for sending the selection data of the input interface to the own station and in the read mode, and an input for decoding the selection data output from the output interface The interface selection decoder and the duplication connected to it when selected by the output of the input interface selection decoder. Electronic copying machine control apparatus being characterized in that at least and a plurality of input interfaces in parallel connecting the input device to the bus.