JPH0644226B2 - Processor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an arithmetic processing device that performs numerical calculation, and more particularly to an arithmetic processing device that handles fixed-point data.

[Conventional technology]

A fixed-point data method is a data format often used in numerical calculations. With this fixed-point data method,
Two's complement representation is common. Conventionally, in the operation by the two's complement fixed-point data method, the range of numerical values that can be expressed is limited, so that the calculation result cannot be expressed if it exceeds this range. Conventionally, when the value exceeds the range that can be expressed as described above, correction processing as overflow has been performed. Here, a case of a data length of 8 bits in 2's complement display will be described as an example. When the data length is 8 bits (however, the most significant bit is a positive or negative sign bit), numerical data x
Is expressed in the range of 80 (H) ≦ x ≦ 7F (H) (H indicates hexadecimal notation). If expressed in binary, 1000000 ≦ x ≦ 01111111.
Two arbitrary values are added, and the addition result is the above range 8
When it exceeds 0 (H) or 7F (H), it is treated as an overflow. At this time, in the conventional arithmetic device,
As the calculation result, the result when the overflow occurs is taken as it is, and an overflow flag indicating that the overflow has occurred is set. The program detects the overflow flag, and the program corrects the calculation result to the maximum positive value (7F (H)). Here, it will be specifically shown by using numerical values. Two values to be calculated are 70
(H) and 2E (H), the addition result is 9E (H)
Becomes However, since the data length is 8 bits and is a two's complement representation, the result shows a negative value even though the most significant bit is a positive value because it shows a positive or negative sign sign. Become. Therefore, the overflow flag is set and an overflow correction process is required. In this correction processing, the overflow flag is detected by the program, and when the calculation result should be positive, it is replaced with the maximum positive value, and when it is negative, it is replaced with the minimum negative value. In the calculation of the above example, since the correct value is a positive value, the calculation result is replaced with the maximum positive value of 7F (H).

FIG. 3 is a block diagram showing an example of a conventional fixed-point-compatible arithmetic processing unit. In FIG. 3, registers 14 and 1
When the data stored in 5 is calculated by the calculator 16 and the result detection circuit 18 detects overflow,
Information on overflow is stored in the holding circuit 19. The information stored in the holding circuit 19 is detected by a program, and the above-described correction processing is applied to the calculation result stored in the register 17.

[Problems to be solved by the invention]

In the conventional arithmetic device described above, even if there is a difference in the arithmetic result when the overflow occurs, it is corrected to the same value. In other words, in the above example, when there are two types of calculation results at the time of overflow, 80 (H) and FE (H), both are 7F (H) even though the difference is 7E (H). ), The difference between the two disappears.
As described above, in the conventional arithmetic device, the arithmetic precision is extremely lowered, which is a big drawback. As a method for solving this conventional technique, the calculation result is considered in consideration of its sign bit, and 1
By shifting to the right by one bit, the result is reduced by one digit, but the precision of the data can be maintained. If one data in the data group that requires the same data processing as the data that causes the overflow of the above-mentioned operation, one digit lower than the carry due to the overflow processing is also added to the other data. It is necessary to align the digits of the entire group.

Therefore, an object of the present invention is to solve the above problem and to perform a correction process when an overflow occurs in the calculation of fixed-point data represented by 2's complement at the same time as the overflow occurs, and An object of the present invention is to provide an arithmetic processing device capable of preventing deterioration of data accuracy in processing.

[Means for solving problems]

The arithmetic processing unit of the present invention includes first and second registers for storing arithmetic data as fixed-point data, an instruction register for storing instruction data, a decoder for decoding the instruction register, and an output from the decoder. An arithmetic unit for inputting the output values of the first and second registers by a signal to perform arithmetic operation, a third register for storing the output value of the arithmetic unit, and a most significant digit generated in the arithmetic unit Processing including a detection circuit that receives the first carry signal to the first carry signal and the second carry signal from the most significant digit as input and detects an overflow, and a first holding circuit that holds the detection signal of this detection circuit In the device, first shift means for shifting an output value of the first register between the first register and the arithmetic unit. , Second to shift the output value of the second register between the computing unit and the second register
Shift means, third shift means for shifting the output value of the arithmetic unit between the third register and the arithmetic unit, and a second holding circuit for holding the correction request signal from the decoder. , A control circuit which receives each of the output signals of the first and second holding circuits and outputs a control signal for designating a correction process to each of the first, second and third shift means. To be done.

〔Example〕

Next, the arithmetic processing device of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an arithmetic processing unit according to an embodiment of the present invention.

Referring to FIG. 1, the arithmetic processing unit of this embodiment has registers 1 and 2 for respectively storing data to be arithmetically operated.
, Shifters 3 and 4 for shifting the values of registers 1 and 2, an arithmetic unit 5 for arithmetically operating the output data of the shifters 3 and 4 and outputting the arithmetic result in accordance with the instruction register 12 and the decoder 13, and the arithmetic result It has a shifter 6 for correction and a register 7 for storing the calculation result.

Further, this arithmetic processing unit holds a detection circuit 8 for detecting whether or not an overflow has occurred in the operation, a holding circuit 9 for holding the information for which the overflow has occurred, and information for whether or not to perform data correction due to the overflow. It has a holding circuit 10 and a control circuit 11 that generates a signal for data correction.

Next, the operation of the arithmetic processing unit of the present invention will be described.
The data to be calculated is stored in the register 1 and the register 2, and when the calculator 5 does not overflow, the data in the register 1 and the register 2 is not shifted in the shifter 3 and the shifter 4 and the input data of the calculator 5 is not changed. Becomes The input data is calculated by the arithmetic unit 5, and when an overflow does not occur in this arithmetic operation, the shifter 6 outputs the arithmetic result as it is to the register 7 without being shifted.
Next, a case where an overflow occurs in the arithmetic operation in the arithmetic unit 5 will be described. The detection circuit 8 detects an overflow by an exclusive OR of the carry from the most significant bit generated by the calculation in the arithmetic unit 5 and the carry from the next lower bit. The overflow signal detected here is held by the first holding circuit 9 as overflow information. Further, the signal from the second holding circuit 10 holding the information as to whether or not to perform the overflow processing and the signal from the first holding circuit 9 are logically ANDed by the control circuit 11 to obtain the overflow processing signal. Becomes By the overflow processing signal, the shift circuit 6 shifts the operation result right by 1 bit including the carry bit of the operation result. Further, in the shift circuit 3 and the shift circuit 4, 1-bit right shift by sign bit extension is performed on the data to be shifted to the right. By the above operation, the operation result can be corrected and the operation data after the operation can be right-shifted by 1 bit (corresponding to halving) at the same time, so that the overflow can be prevented from occurring and the operation result can be prevented. Also, the accuracy of (1) overflows and becomes the same as the accuracy of the operation result shifted by the shifter 6.

[Embodiment 2] In the embodiment, the shift circuit is used when the overflow processing is applied to the input data and the operation result, but a simple multiplexer circuit may be used as shown in FIG.
In this case, the shift control signal a due to the occurrence of overflow
Becomes a data select signal. The operation of the multiplexer circuit will be briefly described with reference to FIG. When the overflow process is not required, the value of the output O is the value of the input data I as it is and is output. If overflow processing is required, the bit H on the left of the input data I is selected and output. By this operation, the same function as the shift circuit can be achieved.

〔The invention's effect〕

As described above, according to the present invention, when an overflow occurs in the operation, the result of the operation is right-shifted by 1 bit including the sign bit, so that the accuracy of the data can be corrected without lowering the accuracy. With respect to the operation after the overflow has occurred, the input data of the operation can be shifted to the right by 1 bit including the sign bit, so that the same data accuracy as the output result of the operation can be obtained in terms of accuracy. Further, there is an effect that a series of correction processes accompanying the occurrence of overflow in the calculation can be performed faster than the process by the program.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a view showing an embodiment in which the shift register shown in FIG. 1 is used as a multiplexer, and FIG. 3 is an example of a conventional arithmetic processing unit. It is a block diagram showing. 1, 2, 7, 12, 14, 15, 17 ... Register,
3, 4, 6 ... Shifter, 5, 16 ... Operation unit, 8, 18
...... Detection circuit, 9, 10, 19 …… Holding circuit, 11 ……
Control circuit, 13 ... Decoder, O ... Output signal, a ...
Shift control signals, I, H ... Input signals.

Claims (1)

[Claims] 1. A first and a second register for storing operation data as fixed point data, an instruction register for storing instruction data, and a decoder for decoding the instruction register.
According to the output signal from this decoder, the first and second
, A third register for storing the output value of this arithmetic unit, and a first carry signal to the most significant digit generated by the arithmetic unit. And a detection circuit for detecting an overflow by inputting a second carry signal from the most significant digit and a first holding circuit for holding the detection signal of the detection circuit, wherein the first register And a calculator, the first shift means for shifting the output value of the first register, and the output value of the second register between the second register and the calculator. Second shift means, third shift means for shifting the output value of the arithmetic unit between the third register and the arithmetic unit, and a second holding unit for holding a correction request signal from the decoder. Circuit,
And a control circuit which inputs each of the output signals of the first and second holding circuits and outputs a control signal for designating a correction process to each of the first, second and third shift means. An arithmetic processing unit characterized by.