JPH0644259B2 - System for coordinating data transfer operations - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention is used to perform data transfer between a peripheral terminal device and a main host computer, and is used by an intermediate I / O subsystem to perform a housekeeping obligation for data transfer. It is related to the system.

BACKGROUND OF THE INVENTION The seamless area of evolving technology involves the technology of transferring data between a primary host computer system and one or more peripheral terminal devices. This alleviates the problems of monitoring and housekeeping of the main host computer, undertakes the burden of controlling the peripheral terminal equipment, and monitors the control of data transfer that occurs between the peripheral terminal equipment and the main host computer system. Have been developed for use with the I / O subsystem.

A specific embodiment of such an I / O subsystem has been developed which uses a peripheral controller known as a data link processor whereby a start command from the main host computer can be issued to one or more peripherals. It is advanced to a peripheral controller that manages data transfer operations with the device. In these systems, the primary host computer also provides a "data link word", which identifies each task initiated to the peripheral controller. After completion of the task, the peripheral controller informs the primary host system of the results / descriptor words for the completed, uncompleted or problem involved in the particular task.

These types of peripheral controllers are described in a number of patents issued to the assignee of the present disclosure, and these patents are hereby incorporated by reference as follows.

D. A. Invented by Millers, II, entitled "Interface System for Providing Interface to Central Processor and Modular Processor-Controller for Input-Output Subsystems", August 1978.
Published US Patent 4,106,09
No. 2.

D. J. Cook and D.C. A. U.S. Pat. No. 4,074,352, issued February 14, 1978, invented by Millers, II, entitled "Modular Block Unit for Input-Output Subsystems".

D. J. Cook and D.C. A. U.S. Pat. No. 4,162,520, issued July 24, 1979, invented by Millers, II, entitled "Intelligent Input-Output Interface Control Unit for Input-Output Subsystems".

D. J. Cook and D.C. A. Invented by Millers, II, entitled "Input-Output Subsystem for Digital Data Processing Systems", issued Feb. 19, 1980, U.S. Pat. No. 4,189,769.
issue.

K. W. Baun and J. G. Invented by Saunders and entitled "Data Ring Processor for Magnetic Tape Data Transfer Systems", issued July 21, 1981, U.S. Pat. No. 4,280,193.
issue.

K. W. Baun and D.C. A. U.S. Pat. No. 4,313,162, issued January 26, 1982, invented by Millers, II, entitled "I / O Subsystem Using Data Link Processor".

K. W. Invented by Baun, entitled "Common Front-End Control for Peripheral Controllers Connected to Computers", issued March 30, 1982,
United States Patent 4,322,792.

The above-incorporated patent, incorporated herein by reference, is known as a "data link processor", or DLP, for the use of this type of peripheral controller used in a data transfer network between a main host computer and peripheral terminal equipment. , Bring about a background understanding.

In the Baun patent mentioned above, a peripheral controller made up of modular components is described, which has universal properties for all types of peripheral controllers and is connected to peripheral dependent board circuits. And a common front end control circuit. The peripheral dependent circuit is specialized to handle the characteristics of a particular peripheral terminal device.

This disclosure also operates in a manner equivalent to peripheral dependent circuits, particularly suitable for handling certain types of peripheral terminal equipment, such as tape control units (TCUs) that connect to one or more magnetic tape devices. In that the peripheral controller uses a common control circuit or common front end that
It uses a peripheral controller (data link processor) that follows the general pattern of the system described above.

SUMMARY OF THE INVENTION The present invention includes a data transfer network,
There, a peripheral controller, known as a data link processor, is used to manage and control data transfer operations between a peripheral device, such as a magnetic tape device (or tape controller), and a main host computer system. , Whereby the data is transferred rapidly in large blocks, such as blocks of 256 words.

The data link processor is an R, for temporarily storing data transferred between the peripheral and the host system.
An AM buffer memory means is provided. In this case, RAM
The buffer can hold at least 6 blocks or units of data, each of which consists of 256 words, each word being 16 bits.

(A) data is often "shifted" into the RAM buffer memory means from either the peripheral device or the main host computer; and (b) the data in the RAM buffer memory is, for example, either a magnetic tape peripheral device or the main host computer. To facilitate and control these activities, such as being “shifted out” of the RAM buffer memory, the peripheral controller and the system are concerned about the amount of data present in the RAM buffer memory during any period of time. It is necessary to have data that informs the status.

Thus, a system for coordinating data transfer operations between a host and a peripheral device is disclosed whereby the peripheral controller provides a routine for data transfer appropriate to the state of the data in the RAM buffer. Detect the block of data stored in that RAM buffer for selection. The peripheral controller uses a block counter monitoring system, which is the RA
Informs the peripheral controller and the main host system of the "numerical block status" of the data in the M-buffer memory means.

In particular, the present invention is characterized in that a common front end (common control) circuit is used for inserting or extracting data.
A system is disclosed that uses a routine to provide address registers with microcode instructions that access locations in an AM buffer memory. There are two address registers, one taken from the peripheral /
It is for the address of the data provided to the peripheral device, and the other is for the address of the data which is / is to be advanced to / from the main host computer.

The block counter logic circuit receives inputs from the peripheral address register and the system address register. In addition, the flip-flop output to the block counter logic is either "write" (host to peripheral) or "read".
It shows the direction of data flow (peripheral to host). The block counter logic circuit provides two output logic signals that control the block counter. this is,
The block counter is activated to be upshifted or downshifted so that the internal signal data indicates the number of blocks of data present in the RAM buffer memory. When the total amount of data in the RAM buffer memory drops below a certain number, certain parameters are set to trigger the signal output condition.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a block counter system according to this disclosure used to inform a data transfer system of the status of buffer memory means.

FIG. 2 is a system diagram showing a host computer cooperating with a peripheral controller to control data transfer to and from the peripheral device.

FIG. 3 is a diagram showing an 8-bit shift register that can be shifted up or down according to the conditions that occur between certain logic and clock signals.

FIG. 4 shows that the block counter logic unit of FIG.
FIG. 6 illustrates the effect of how it is configured to operate during a read or write operation, and either upshifting or downshifting a shift register.

FIG. 5A is a schematic diagram showing the weight of each bit position in the block counter.

FIG. 5B is a diagram showing various "shift" relationships of the block counter for "read" and "write" operations.

The "read" operation takes the data from the peripheral tape drive and then reads it for later transfer to the host system.
Store it temporarily in the AM memory buffer.

The "write" operation takes data from the main host system,
Temporarily stored in RAM buffer memory for subsequent transfer to the selected magnetic tape unit via the TCU or tape controller.

Overall System Operation To begin operation, the host system 10 of FIG.
Sends the I / O descriptor and descriptor link word to the peripheral controller (data link processor 20t). I
The / O descriptor identifies the operation to be performed. The descriptor link contains routing information and further identifies the task to be performed so that when the report is later sent back to the primary host system 10, the primary host system will identify which task was included. Can be recognized. After receiving the I / O descriptor link, the data link processor (DLP) causes a transition to one of the following message level interface states.

(A) Result descriptor: This state transition indicates that the data link processor 20t returns the result descriptor immediately without being disconnected from the host computer 10. For example, this transition is used when the DLP detects an error in the I / O descriptor.

(B) DISCONNECT: This state transition is a magnetic tape-data link processor (MT-DL).
P) indicates that no further operations can be accepted at this time and that the I / O descriptor and descriptor link were received without error. This state also indicates that a data transfer or result descriptor transfer can occur.

(C) IDLE: This state transition is DL
P20t indicates that other legal I / O operations could be received immediately, and that the I / O descriptor and descriptor link were received without error.

When the operation is complete, the DLP 20t returns a result descriptor indicating the status of the operation on the primary host system. If the DLP detects a parity error on the I / O descriptor or descriptor link, or
However, if it cannot recognize the I / O descriptor it received, then the DLP cannot continue executing the operation. In this case, the DLP returns a 1-word result descriptor to the host. DL in all other cases
P returns a 2-word result descriptor.

The data link processor 20t is a multi-descriptor data link processor, and can hold one I / O descriptor for each magnetic tape device to which it is connected. Not there, but DLP
Some descriptors (test / channel; test / discontinuity; and test / I) that can be accepted at any time by
D) is present. Test / channel and test / suspend OPs occur in a wait state for a single tape drive dedicated to its peripherals, and the I / O descriptor for that particular tape drive is in the DLP. You need to already exist. If an I / O descriptor is received and violates this rule, the DLP immediately returns the result descriptor to the host. This result descriptor indicates "descriptor error" and "incorrect state".

As already discussed in the incorporated patents, M
The T-DLP utilizes the following status state (STG) transitions when "disconnected" from the host.

STC = 3 to STC = 1 Disconnect from Idle This indicates that the DLP is attempting to process a pending OP.

STC = 1 to STC = 3 Disconnect to Idle This indicates that the DLP is ready to receive a new I / O descriptor.

STC = 3 to STC = 5 Idle to Transmit Descriptor Link This indicates that the DLP is performing an OP, and
Is requesting access to the host computer.

STC = 1 to STC = 5 Disconnect to Send Descriptor Link This indicates that the DLP is performing an OP and that the DLP
Is requesting access to the host computer.

The DLP status condition may be represented in a shortened notation such as STC = n.

Upon completion of the I / O operation, the data link processor forms a result descriptor and sends it to the host system. This descriptor contains in the result status word the information sent to the DLP by the tape controller 50tc and the information that occurred in the DLP. This result descriptor represents the result of an attempt to perform the requested operation.

Descriptor Management All communication between the DLP 20t and the host system 10 is controlled by standard DLP status states, as described in the above-incorporated patents. These status states activate the information to be transferred in sequence. Host computer 10 is DLP2
When connected to 0t, the DLP has two different states:
It can be in one of (a) ready to receive a new descriptor, or (b) in use.

When STC = 3 (idle), the DLP can receive a new I / O descriptor. When STC = 1 (Disconnect) or STC = 5 (Transmit Descriptor Link), the DLP is busy and performs the already forwarded operation.

When the DLP receives an I / O descriptor and a descriptor link that does not require immediate attention, the DLP stores the descriptor in its descriptor wait state. The DLP can then receive other I / O descriptors from the host system.

When the host system 10 is "disconnected" from the DLP 20t after issuing one or more pending I / O descriptors, the DLP begins searching its descriptor queue. This search continues until the DLP finds an I / O descriptor that requires the DLP's attention, or until the host "reconnects" to send additional I / O descriptors. If the DLP finds an I / O descriptor that requires attention, then the descriptor is in the test / wait state for a unit available OP or the test / wait state for a unit unavailable OP. If none of these is specified, then DL
P confirms that the host is still "disconnected". If these conditions are met, the DLP will
= 1 (disconnect), and the execution of the descriptor is started. Once D
When LP goes to STC = 1, no more I / O descriptors will be received from the host until the initiated operation is complete and the result descriptor is returned to the host.

The DLP searches its descriptor queue on a rotation basis. The search order is one or more new I's.
Neither by receipt of the / O descriptor nor by execution of the operation. This means that all pending entries are taken in order, and all units have equal priority, regardless of DLP activity.

When cleared, the DLP halts all operations in progress for the peripheral and invalidates all pending I / O descriptors, and status ST
Return to C = 3 (idol).

DLP-Data Buffer and Data Transfer The DLP data buffer 22 (FIG. 1) provides a storage means for 6 blocks of data, used in a "circular" fashion. Each of the 6 blocks holds a maximum of 512 bytes of data. Data is transferred, block by block, to or from the host system via buffer 22, followed by a vertical parity word (LPW). The data is always the whole block (5, except the last block of data for a particular operation.
12 bytes). This last block can be 512 bytes or less, as required by the particular operation.

As shown in FIG. 1, logic circuitry (described below) is used to provide information to the block counter, which registers the number of blocks of data present in the buffer 22 at any given moment. The counter 34c should be set to trigger a flip-flop 34e which signals the common control circuit unit 10c when certain conditions occur, such as full buffers, or blank buffers, or the number of blocks "n". And initiate the necessary routines to either transfer data to host 10 (after reconnecting the host) or to get data from host 10 and transfer to buffer 22; or 1
0c is D for receiving data or transmitting data.
The LP 20t can be prepared for connection to a peripheral device (such as a tape controller 50t).

During the write operation, the block counter 34c counts the number of blocks of data received from the host system 10. Once the DLP receives the 6 buffers, the Data Link Processor is "disconnected" from the host system;
Alternatively, it disconnects when it receives an "end" command from the host system (end indicates "end" of write data for the entire I / O operation). After disconnecting from the host, the data link processor connects to the peripheral tape controller (TCU50tc). Once a proper connection has been established between the data link processor and the tape subsystem, the data link processor activates the logic circuit and causes the tape controller 50tc to use the D that is used to transfer the data.
Directly access the LP RAM buffer 22.

After the datalink processor has transmitted one block of data to the tape controller, the datalink processor attempts to "reconnect" to the host system by a "polling request" (the host 10 is "terminating" operation). Unless) Once this reconnection is established, the host
Transfer additional data to the Data Link Processor. This transfer may be due to the 6 blocks of RAM buffer memory 22 being refilled (the buffer in the process of being transferred to the tape controller is considered full during this procedure), or the host 10 "terminating." Continue until you either send a command. The data transfer operation between the data link processor 20t and the tape controller 50tc continues at the same time that the host data transfer occurs (via the buffer 22) between the host 10 and the DLP 20t.

If the data link processor has not successfully reconnected to the host before the DLP has transmitted, for example, 3 blocks of data to the tape controller 50tc, the data link processor will not be able to access the data link interface 20i of FIG. Set "urgent request" to. Hello D
1 LP left to transmit to tape controller
If the "urgent request" is not well serviced before having only the block of data, the data link processor sets a "block error" condition by a signal from flip-flop 34e to circuit 10c. this is,
It is reported to the host system as a "host access error" in the result descriptor.

The last block of data for any I / O operation is
It is transferred directly to the tape controller 50tc under microcode control. During a "read" operation, the data link processor first attempts to connect to the tape controller 50tc. Once the good connection is complete, the data link processor causes the logic circuit to begin receiving data from the tape subsystem. Once the datalink processor receives 2 blocks of data (or its total length is 2
Once the DLP has received all the data from the operation below the block), the Data Link Processor will attempt to connect to the host using a "Pol Request". The data link processor will continue to receive tape data while simultaneously affecting this host connection.

If the host does not respond to the "Pol Request" before four blocks of data are present in the DLP RAM buffer 22, the Data Link Processor will set "Emergency Request" on the Data Link Interface 20i. If the connection to the host system is not made before all six RAM buffers are filled,
The Data Link Processor then sets "Host Access Error" in the Result Descriptor.

Once the host system responds to the "poll request",
The data link processor 20t is the host system 10
Starts sending data to the tape controller 5 while
Continue receiving data from 0tc at the same time. After the host 10 of FIG. 2 receives a block of data, the data link processor checks whether all two blocks of data remain to be transferred to the host. If so, DLP uses "break activation". If the "activate break" request is acknowledged, then the transmission of the next data buffer to the host continues to occur. If it is less than the data of all two blocks in the RAM buffer 22 (or
If "break enable" is rejected), the data link processor disconnects from the host and waits until there are two more full blocks of data. If the "break activate" is rejected, the data link processor initiates another "polling request" immediately after disconnection.

When the data link processor completes the data transfer, the tape controller 50tc enters the result stage and also sends a two word result status to the data link processor 20t. The DLP then combines this information with the internal result flag to create a result descriptor,
Sends it to the host.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 2, a general system diagram is shown by which the host computer 10 can perform I / O.
It connects through the subsystem to a peripheral device, here illustrated as tape controller 50tc. This tape control unit (TCU) comprises a plurality of magnetic tape units (M
TU) used to manage the connection to the terminal device.
According to the description in the above-referenced patents incorporated herein by reference, the I / O subsystem includes a distribution control circuit 20od and a data link interface 2.
It consists of a base module that supports one or more peripheral controllers, as well as other connection and distribution circuits such as 0i.
The peripheral controller 20t is the common front end circuit 1
And 0c, in this case, as composed of a peripheral dependent circuit shown to be composed of two peripheral dependent boards designated as 80p ₁ and 80p _2, is shown in modular form.

In this network context, it is often desirable for data from the main host computer to be transferred onto a peripheral device, such as a magnetic tape device, for recording on tape. This is done via a peripheral tape controller TCU such as 50tc. Similarly, it is often desired that data from a magnetic tape drive be passed through a tape control unit so that it can be read by a host computer. In this way, data is transferred bi-directionally, i.e. in two directions at different times in the activity of the network.

The basic monitoring and control device is the data link processor 20t, which, when initiated by a particular command of the host computer, prepares to transfer the desired data in the desired direction.

As shown in FIG. 1, the RAM buffer 22 is
Used to temporarily store data that is transferred between peripheral devices and the main host computer. In the preferred embodiment, this RAM buffer is capable of storing at least six "blocks" of data, each block consisting of 256 words.

Referring again to FIG. 1, block counter logic unit 33c is used to receive inputs from two address registers designated as peripheral address register Pa and system address register Sa. The peripheral address register Pa handles an address required when data is retrieved from the peripheral tape device or when data is sent to the peripheral tape device. This system address register Sa is used when data is received from the host system into the buffer 22 or data is sent from the buffer 22 to the host system.
It can be seen that these two address registers in FIG. 1 receive their address data via microcode signals from the common front end circuit 10c of FIG.

The address data outputs from Pa and Sa are provided to the RAM buffer 22 to address the desired location in the buffer memory. Further, the block counter logic unit 33c includes a read-write flip-flop 33.
1 shown as "P carry" from the peripheral address register in addition to the read / write control signal from f
It receives one input and also receives the other input "S carry" from the system address register. The flip-flop 33f is controlled by a microcode signal from the peripheral controller common front end device 10c. The block counter logic unit 33c includes a first logic signal LS ₁ provided to the OR gates G ₁ and G _0.
And a second logic signal LS ₀ . These gates also have additional inputs from the microcode of the common front end card 10c which are used to simulate the LS ₁ and LS ₀ signals for diagnostic or other control purposes. Can be used. This OR gate provides two output signals, labeled S ₁ and S ₀ , which are applied to the block counter 34c. As shown in FIG. 3, in order to provide a condition for the block counter to be either "shifted up" or "shifted down" or "not shifted", the output signal S ₁ And S ₀ are combined.

Referring to FIG. 3, the block counter 34c of FIG.
A schematic diagram illustrating the use of is shown.

Referring to FIG. 3, there is shown schematically an 8-bit shift register which is affected at a selected point where the clock signal is in its "rising" state, as indicated by the arrow in FIG. Referring to the leftmost schematic of the shift register, it is shown that there are two "1" s indicating that the RAM buffer 22 has been loaded with two full blocks of data.
It can be seen that at time T ₁ , "no shift" occurs and two "1" s remain in the shift register. At time T _2, it is "shifted up" and the shift register has 3 bits with a "1" signal. At time T ₃ ,
This results in a "shift down" signal, and the shift register is returned so that the two bit positions contain a "1".
At time T _4, "upshift", and further the shift register is "1" has the three-bit position indicating a signal, it is the buffer 2 at the moment
2 shows all three blocks of data present in 2.

Referring to FIG. 4, in order to show the overall operating state,
A diagram is shown in which the block counter logic unit 33c is constructed. Therefore, as shown in FIG.
The state of S-carry and P-carry during the "read" state shifts or changes when S-carry and P-carry are the same, that is, they are both 0 or both are 1. Indicates that does not happen.

However, when S-carry is "0" and P-carry is equal to "1", an upshift occurs, while if S-carry is "1" and P-carry is "0". , A downshift occurs during the "read" operation period.

Referring to FIG. 4, during the "write" operation period, S
No changes or shifts occur in the shift register when the carry and P carry are again equal to each other (both "0" or both "1"). However, when S carry is equal to "0" and P carry is equal to "1", a downshift occurs in this state, and when S carry is equal to "1" and P carry is equal to "0". It will be an upshift.

When data is being retrieved from the magnetic tape device to be provided to the RAM buffer 22 ("read" operation),
The block counter buffers 22 for transfer to the main host computer system, which in this case is downshifted.
The block counter 34c reflects the situation where the block counter is shifted up if there is no data removed from it at the same time. Therefore, the numerical state of the block counter indicates the difference between the number of data leaving the buffer 22 and the number of data entering the buffer 22.

Referring to FIG. 4, if the "write" operation is performed,
This determines that the data should be written to the magnetic tape drive. The block counter then shifts down as data is removed from the RAM buffer towards the magnetic tape unit, but if
If more data is transferred from the main host computer to the RAM buffer 22, the block counter will be shifted up. Therefore, the placement of a "1" at various bit positions results in a dynamic difference in the fetched data block with respect to the fetched data block during any given time period.

Referring to FIG. 4, the block counter logic unit 3
Several logical equations are shown to illustrate the logic used in 3c.

In the logical equations below, * indicates an AND logical operation, while + indicates an OR logical operation.

(A) If the signal counter S ₁ is equal to “1” and the signal S ₀ is equal to “0”, a so-called “up activation” state occurs, which is (read * S carry * P Carry) + (Write * S carry * P carry).

(B) In the state where the signal S ₁ is equal to “0” and the signal S ₀ is equal to “1”, this is “down activation”.
And is further equal to (read * S carry * P carry) + (write * S carry * P carry).

(C) In the state where the signal S ₁ is equal to “0” and the signal S ₀ is equal to “0”, a state called “unchanged” occurs. This is equal to (read * S carry * P carry) + (write * S carry * P carry).

(D) A condition known as "host access error", or He, sets the flip-flop 34e of FIG. 1 (this is also called a block counter error). Therefore, the host access error signal or block counter error signal is the result of He = (read * 6 all blocks (BLKFUL)) + (write * 1 all blocks (BLKFUL)).

Therefore, in a read operation, all RAM buffers (6 blocks of data) signal an error condition.

Similarly, in a write operation, the signal (1) remaining on the block of data triggers an error condition.

Referring to FIG. 5A, a schematic diagram of the block counter 34c is shown, in which when a "1" is present in a series of bit positions, it indicates how many blocks of data are present in the RAM buffer 22 (FIG. 1). It means that it is indicating that you are doing.

For example, when there is a "1" in each of bit positions 1, 2, 3, 4 this is a "4 block" of data.
Is present in the RAM 22. Each "block" is composed of 256 words (512 bytes for every 8 bits).

In FIG. 5, the figure illustrates the following operations during a data "read" operation from the peripheral tape device to the main host system.

(A) As the P carry of "1" increases (when data is being transferred from the peripheral tape device to the buffer memory 22), the block counter 34c is "shifted up" and the buffer is being "loaded". Indicates.

(B) As the S carry of "1" increases (when data is transferred from the buffer memory to the main host system), the block counter 34c "shifts down".
To indicate that the buffer memory is being "blanked".

In FIG. 5B, the figure shows the following during a "write" operation of data from the main host system to the peripheral tape device.

(C) As the S carry of "1" increases (when data is being loaded from the primary host system into the buffer memory), the block counter 34c "shifts up" to indicate the number of blocks of data in the buffer.

(D) As the P carry of "1" increases (when the data in the buffer is unloaded for transfer to the peripheral tape device), the block counter 34c "shifts down" and how much data is available. Indicates whether the buffer 22 is left.

In FIG. 5B, the flip-flop circuit 34e (FIG. 1) is set when the "1" appears at the sixth bit position of the block counter 34c during the "read" operation, and the main system To the common front-end circuit 10c. This is because the primary host system cannot receive the data quickly enough.
2 means "overfilled".

During the "write" operation, when the buffer memory 22 receives 6 blocks of data from the host system and the first bit position (1BLKFUL) becomes "0", this causes the buffer memory to completely fill. It is shown to be unloaded (cleared) and then flip-flop 34e is set to signal common front end circuit 10c that more data is requested from the host. This indicates that the host does not provide data to RAM buffer 22 quickly enough.

Responds to the status of the passing data present in the RAM buffer memory. And thereby allowing monitoring of blocks of data transferred between the peripheral device and the main host computer when there is a concurrent flow of data provided to or retrieved from the RAM buffer means. A system for control has been described.

Although the disclosure herein describes one embodiment of the system described above, the system described above is not limited thereto, but rather in all of these as defined in the following claims. Should be considered to include the system of.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Sees Jei Shiu Buoy United States 92630 El Toro Rimgate Drive, Calif.・ Viejo-Via Erbus Street 23281 (56) Reference JP-A-57-120144 (JP, A) JP-A-57-62438 (JP, A) JP-A-57-62432 (JP, A) Actual exploitation Sho 57-123537 (JP, U)

Claims (12)

[Claims] 1. A system for adjusting bidirectional data transfer operation in a network in which data is bidirectionally transferred between a main host computer and a magnetic tape peripheral device via a peripheral controller, said system comprising: The peripheral controller is activated by a command from the host computer to execute a bidirectional data transfer operation, and the peripheral controller manages a common control circuit device for ordering microcode instructions and the tape peripheral device. A system for coordinating bidirectional data transfer operations comprising: (a) buffer memory means in the peripheral controller for temporarily storing blocks of data being transferred. And the buffer memory means includes the tape peripheral device and the disk. A status means in the peripheral slave circuit device which has a channel of connection to a storage computer, and (b) provides information data for indicating the number of blocks of data existing in the buffer memory means at any given time. The status means further comprises: (i) a block for detecting the number of blocks of data entering and leaving the buffer memory means and supplying a block increment signal or a block decrement signal to an associated block counter. A counter logic circuit, wherein the block increase signal and the block decrease signal are controlled by the common control circuit device that specifies whether a read operation or a write operation is being performed, and (ii) the related block The counter is the data existing in the buffer memory means. The count value of the block at any arbitrary time is held, and the block counter is (iia) whether the data block should be put into the buffer memory means or should be outputted from the buffer memory means. (C) signal output means connected to the status means and functioning to give a status signal to the common control circuit device; and (d) the host computer to the buffer memory. Means for simultaneously transferring a block of data to the means while simultaneously transferring a block of data from the buffer memory means to the tape peripheral device; and (e) simultaneously transferring a block of data from the tape peripheral device to the buffer memory means. From the buffer memory means to the host Further comprising a system and means for transferring a block of data to the computer. 2. The host system initiates a write operation command to the peripheral controller in order to transfer data from a main host computer, and the common control circuit device causes the buffer memory means from the host computer. The system of claim 1, wherein the system initiates a routine for transferring data to. 3. The system according to claim 2, wherein said status means includes: (a) shift register means for counting up the number of blocks of data received in said buffer memory means and shifting up. 4. The shift register causes the signal output means to pass information data to the common control circuit device when the buffer memory is filled with data from the host computer in blocks, and 4. The system according to claim 3, wherein the common control circuit device disconnects the host computer from the buffer memory means. 5. The system of claim 4 wherein said common control circuit device connects said peripheral tape device to said buffer memory means after disconnecting said host computer. 6. The method according to claim 5, wherein the common control circuit device executes data transfer from the buffer memory means to the peripheral tape device when the peripheral tape device is connected to the buffer memory means. The system described in paragraph. 7. The system of claim 6 wherein said shift register shifts down each time a block of data is removed from said buffer memory means to said peripheral tape device. 8. When the shift register decrements by one block, the signal output means passes information to the common control circuit and reconnects it to the main host computer to the buffer memory means. 8. The system of claim 7, which enables more data transfer of. 9. The system of claim 1 wherein said host system initiates a read operation command to said peripheral controller to transfer data from said peripheral tape device to said buffer memory means. 10. The status means includes: (a) shift register means operable to shift up one unit for each block of data received by the buffer memory means from the peripheral tape device. The system according to item 9. 11. When the shift register means indicates that two blocks of data have been received, the signal output means gives a signal to the common control circuit device to cause the buffer memory means to the main host computer. The system according to claim 10, wherein the system is connected. 12. The shift register shifts up for each block of data received by the buffer memory means, and the shift register shifts down for each block of data transferred to the main host computer. The system of claim 11 in the scope of.