JPH0644272B2 - Arithmetic unit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic device, and more particularly to a vector arithmetic device equipped with a summation calculator.

2. Description of the Related Art An example of a conventional summation operation will be described with reference to FIG.
First operand A stored in vector register 10
i and the second operand Bi (where i = 1, 2, 3, ...
.., n) is stored in the instruction register 30, the instruction is decoded by the decode circuit 40 and outputs a logic "1" to the signal line 204, and the sum calculation control circuit.
Instruct 20 to start calculation operation. The summing arithmetic control circuit 20 instructs the vector register 10 to read n-element data, whereby the first operand Ai and the second operand Bi are read to the signal line 200 1 and the signal line 201 2, respectively. In the adder circuit 50, the addition operation of the first operand Ai and the second operand Bi is performed, and the addition result is output to the signal line 203. From the operation result, 1 to n / 2 elements are added to the first operand section of the vector register 1. , N + 1/2 to n
Each element is stored in the second operand part.

The above is the first calculation operation, and the second calculation operation is 1
The same operation as the first time is performed for the n / 2 elements stored in the second time operation, and the total is obtained by performing the operation up to (Log2n + 1) times.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention However, as described above, in the conventional arithmetic unit having the sum operation function, the sum operation of the first operand and the second operand is always performed, and only one of the operands is operated. When the sum is calculated, the other operand must be cleared to 0 in advance, so there is a drawback that the performance is reduced.

The present invention has been made in view of the above-mentioned conventional circumstances,
Therefore, it is an object of the present invention to provide a novel arithmetic unit capable of solving the above-mentioned drawbacks inherent in the conventional technique.

Means for Solving the Problems In order to achieve the above-mentioned object, an arithmetic unit according to the present invention has a vector register for storing a first operand and a second operand and a first arithmetic operation or a second or more arithmetic operation. Operation number identification circuit for identifying whether the operation operation is the operation operation of only one operand at the time of the sum operation, the first selection circuit for selecting the first operand or the logic "0", and the second operand or the logic "0". And a summing circuit connected to the first and second selection circuits, and performs a summation operation only on the first operand or the second operand. It is possible.

EXAMPLES Hereinafter, the present invention will be specifically described with reference to the drawings with respect to a preferred example thereof.

FIG. 1 is a block diagram showing an embodiment of the present invention, and is a diagram for explaining a summation operation of an arithmetic unit according to the present invention.

Referring to FIG. 1, an embodiment of the present invention is such that a vector register 1, a summation operation control circuit 2 and an instruction register 3 are provided.
A decoding circuit 4, an addition circuit 5, a selection circuit 6 for selecting a first operand or a logic "0", a selection circuit 7 for selecting a second operand or a logic "0", and an operation number identification circuit. 8 and.

First operand A stored in vector register 1
i and the second operand Bi (where i = 1, 2, 3, ...
,, n), an instruction for calculating the sum total is stored in the instruction register 3, the instruction is decoded by the decode circuit 4, and a logic "1" is output to the signal line 104, and the sum calculation control circuit 2 is output. Instruct the start of calculation.

Here, in the sum operation, the data read from the vector register 1 is added by the adder circuit 5, the n / 2 element of the addition result is in the first operand part of the vector register 1, and the remaining n / 2 elements are in the second operand part. The calculation operation is performed once until it is stored in, and this operation is performed (Log2n + 1) times.
However, the number of calculation elements is reduced to half each time a calculation operation is executed.

When the summation calculation control circuit 2 receives the summation calculation start instruction, the summation calculation control circuit 2 causes the signal line 103 to have a logic “1”.
Is output, the first operand Ai and the second operand Bi stored in the vector register 1 are read, and the signal line 100
And 101 respectively. The signal line 100 is connected to the selection circuit 6, and the signal line 101 is connected to the selection circuit 7. The output signal lines 110 and 111 of the number-of-operations identification circuit 8 are always logic "0" because they are the sum operation of two operands, and the selection circuits 6 and 7 select the signal lines 100 and 101, respectively, and the signal line 11
Output to 2 and 113 respectively. The signal lines 112 and 113 are respectively connected to the first input and the second input of the adder circuit 5, the addition operation of both is performed, and the addition result is output to the signal line 102. The calculation result of elements 1 to n / 2 is the signal line 10.
When it is output to 2, the summation operation control circuit 2 sets the output signal line 105 to logic "1", stores the operation result in the first operand part of the vector register 1, and outputs the element n + 1/2.
When the calculation results of ~ n are output to the signal line 102, the output signal line 104 of the summation calculation control circuit 2 is set to logic "1".
Then, the calculation result is stored in the second operand part of the vector register 1.

As described above, the n-element data read from the vector register 1 is subjected to the addition operation, and n / 2 elements are stored in the first operand section and the second operand section of the vector register 1 one by one.
In the second arithmetic operation, the same operation is performed for the n / 2 element stored in the vector register 1 in the second arithmetic operation. Below, the same thing is done (Log2n + 1) times to find the sum.

Next, when an instruction for calculating the sum of only the first operand Ai stored in the vector register 1 is stored in the instruction register 3, the instruction is decoded with the decoding count of 4 and a logical "1" is output to the signal line 107. Is output to instruct the total operation control circuit 2 to start the operation and to instruct the operation number identifying circuit 8 to identify the number of operations.

In the first arithmetic operation, a logical "0" is always output to the output signal line 110 of the arithmetic operation number identifying circuit 8 regardless of the number of arithmetic operations, and the output signal line 111 of the total arithmetic operation control circuit 2 indicating the number of arithmetic operation operations. The logic "1" is output only while the content of the output signal line 109 indicates the first arithmetic operation. Selection circuit 6
Since the signal line 110 is logic "0", the signal line 100 is selected and the first operand Ai read from the vector register 1 is output to the signal line 112. In the selection circuit 7, the signal line 11
Since 1 is a logical "1", select a logical "0" to select the signal line 113
Output to. Elements 1 to n / 2 are stored in the first operand portion of the vector register 1 and elements n + 1/2 to n are stored in the second operand portion of the vector register 1 as a result of the addition of the two data in the adder circuit 5.

In the second operation, the output signal lines 110 and 111 of the operation number identification circuit 8 are both logic "0", and the selection circuit 6
Now, let the first operand of the vector register 1 be the signal line 112.
In addition, the selection circuit 7 outputs the second operand to the signal line 113, and the same operation as the first operation is performed.

The same arithmetic operation as the second time is performed until the (Log2n + 1) th time, and the sum of only the first operand Ai is obtained.

When the sum of only the second operand Bi of the vector register 1 is calculated, the output signal line 110 of the operation number identification circuit 8 is set to logic "1" and the signal line 111 is set to logic "0" in the first calculation operation. The difference is that, when the number of selection times is 6, the logic "0" is selected to the signal line 112, the selection circuit 7 selects the signal line 101, and the second operand Bi is output to the signal line 113, and the other is the first operand Ai. By performing the same operation as the total sum calculation of the above, the total sum of only the second operand Bi is obtained.

EFFECTS OF THE INVENTION As is apparent from the above description, according to the arithmetic unit of the present invention, it is possible to calculate the sum of only the first operand or only the second operand of the vector register with the sum calculation instruction, and not perform the sum calculation in advance. Since it is not necessary to clear the other operand to 0, it is possible to obtain an effect that the performance can be improved as compared with the conventional arithmetic unit.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG.
The figure is a block diagram showing a circuit for performing a summation operation used in a conventional arithmetic unit. 1 ... Vector register, 2 ... Sum operation control circuit, 3
... instruction register, 4 ... decoding circuit, 5 ... addition circuit, 6 ..., selection circuit 7 ... selection circuit, 8 ... number of operations identification circuit,

Claims (1)

[Claims] 1. An arithmetic unit having a sum operation function, wherein n is one of a vector register for storing a first operand and a second operand, and n as a result of an addition operation of n element data read from the vector register. When the / 2 element is stored in the first operand section of the vector register and the remaining n / 2 elements are stored in the second operand section as one operation operation, it is the first operation operation or the second operation or more. An operation number identification circuit for identifying whether it is an operation operation at the time of the sum operation of only one operand, a first selection circuit for selecting the first operand or the logic "0", and a second operand or the logic "0" A second selection circuit for selecting, and an addition operation circuit connected to the first and second selection circuits, and connected to the second operand when the sum of only the first operand is calculated. A logical "0" is output to the output of the second selection circuit, and a logical "0" is output to the output of the first selection circuit connected to the first operand when the sum of only the second operand is calculated. An arithmetic unit characterized in that a summation operation of only the first operand or the second operand is performed by outputting only during the first arithmetic operation.