JPH0644572B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device in which MOSFETs are integrated and formed.

[Technical background of the invention and its problems]

Advances in microfabrication technology for integrated circuits have enabled the production of MOSFETs with an effective channel length of 1 μm or less. MO
Various problems arise when the SFET is miniaturized. For example, the characteristics become unstable due to the short channel effect, and punch-through easily occurs between the source and drain, resulting in a low breakdown voltage. In addition, due to collision ionization in the pinch-off region near the drain, the substrate current flows and the source junction becomes forward biased, and the carrier injected from the source further promotes collision ionization, which in turn leads to a breakdown between the source and drain. The phenomenon of doing also occurs. Further, in the case of CMOS, the latch-up phenomenon due to the parasitic bipolar transistor is also a big problem.

The structure shown in FIG. 1 has been proposed as a structure for solving these problems. This example is an n-channel MOSFET,
A P-type Si substrate 11 is used, a gate electrode 13 is formed in a region separated by a field oxide film 16 via a gate oxide film 12, and a source / drain diffusion layer is formed in self alignment with the gate electrode 13. . As shown in the figure, the source / drain diffusion layers are respectively formed in the n ⁻ layers 14 ₁ and 14 ₂ which are self-aligned with the gate region and have a low concentration and a shallow depth, and the n ⁻ layers 14 ₁ and 14 ₂ which are separated from the gate region. It is composed of high-concentration and deep n ⁺ layers 15 ₁ and 15 ₂ formed so as to partially overlap each other. Reference numeral 17 is a SiO ₂ film formed by CVD, and the source electrode 18 and the drain electrode 19 are respectively n ⁺ layer 1 through the contact holes formed in the SiO ₂ film 17.
It is in contact with 5 ₁ and 15 ₂ .

Thus source, shallow n gate region side of low concentration of the drain diffusion layer ^- by a layer 14 _1, 14 _2, to reduce the distortion of the equipotential lines of channel regions, also the electric field concentration near the drain Can be reduced, and the above problems can be improved to some extent. In FIG. 1, the n ⁺ layers 15 ₁ and 15 ₂ are provided because only the n ⁻ layers 14 ₁ and 14 ₂ have the source electrode 18,
This is because the drain electrode 19 is likely to slip through and the resistance is high.

However the structure of the first figure, said that provided an ^{n +} layer ₁₅ 1, 15 _2, the gate region side n ^- layer ₁₄ 1, 1
4 ₂ can not be neglected the resistance of this part for but retained, the drain current is decreased, there has been a drawback that results in gm decrease of the MOSFET.

[Object of the Invention]

It is an object of the present invention to provide a method of manufacturing a semiconductor device that solves the above-mentioned difficulties.

[Outline of Invention]

The method of the present invention comprises the steps of forming a gate electrode on a semiconductor substrate via a gate insulating film, and doping impurities with the gate electrode as a mask to form a low-concentration first diffusion layer in the source and drain regions. A step of forming an insulating film to be a side wall gate insulating film on the entire surface, and a step of forming a mask material in a side wall step portion of the gate electrode in a self-aligned manner
The mask material, the gate electrode, and the insulating film serving as the sidewall gate insulating film on the sidewall portion of the gate electrode are used as a mask to dope impurities and have a higher concentration than that of the first diffusion layer overlapping the first diffusion layer. A step of forming a second diffusion layer, a step of removing the mask material, and a step of removing an insulating film to be the sidewall gate insulating film other than the sidewall portion of the gate electrode to form a sidewall gate insulating film. A step of disposing a conductor film so as to extend from the surface of the second diffusion layer to the middle of the surface of the first diffusion layer.

Further, the method of the present invention comprises a step of forming a gate electrode on a semiconductor substrate via a gate insulating film, and doping impurities with the gate electrode as a mask to form a low-concentration first diffusion layer in the source and drain regions. And a step of forming an insulating film to be a sidewall gate insulating film on the entire surface, and a step of removing the insulating film to be the sidewall gate insulating film other than the sidewall portion of the gate electrode to form a sidewall gate insulating film. A step of disposing a conductor film on the surface of the first diffusion layer in a self-aligned manner with the sidewall gate insulating film, a step of forming a mask material in a side wall step portion of the gate electrode in a self-aligned manner, and the mask A material, the gate electrode, and an insulating film serving as the sidewall gate insulating film on the sidewall portion of the gate electrode, which is used as a mask to be doped with impurities and which has a higher concentration than the first diffusion layer overlapping the first diffusion layer; Diffusion And forming a. The step of disposing the conductor film may be performed, for example, by depositing a metal film on the entire surface of the substrate in a state where the side walls of the gate electrode are covered with an insulating film and the surfaces of the first and second diffusion layers are exposed. By forming a metal-semiconductor compound on the surface of the drain diffusion layer and etching away the unreacted metal film, it is possible to dispose the metal-semiconductor compound in a self-aligned manner only on the source and drain diffusion layers without a mask alignment step. it can.

〔The invention's effect〕

By making the portion of the source / drain diffusion layer on the gate region side a low concentration first diffusion layer, many problems can be solved by miniaturization of the MOSFET, and the MOSFET due to the large resistance of the first diffusion layer. The deterioration of the characteristics is compensated by disposing the conductor film over the second diffusion layer and the first diffusion layer, and excellent MOSFET characteristics can be obtained.
In addition, the contact resistance is reduced by contacting the source and drain electrodes with the conductor film.
Contributes to the improvement of characteristics. Further, according to the present invention, since the surface of the first diffusion layer region is not completely covered with the pre-conducting film, the first diffusion layer region near the gate electrode due to the potential of the conductor film. The potential rise at is not so large, and the problem of gate breakdown does not occur.

According to the method of the present invention, in the MOSFET having the above-described structure, the first and second diffusion layers and the conductor films provided on these can be formed by self-alignment, which is excellent in fine dimension. An integrated circuit composed of characteristic MOSFETs can be realized with high reliability and high yield. Further, according to the method of the present invention, the surface of the first diffusion layer region in the vicinity of the gate electrode is covered with the gate insulating film below the sidewall gate insulating film. It is possible to easily form a conductor film that extends partway on the surface of the first diffusion layer region. By forming the conductor film extending only from the surface of the second diffusion layer to the middle of the surface of the first diffusion layer region, gate breakdown due to the potential of the conductor film can be prevented.

Example of Invention

Examples of the present invention will be described below. FIG. 2 shows the structure of one embodiment, and FIGS. 3 (a) to 3 (f) show the manufacturing process thereof. This will be described according to the manufacturing process. First, the field oxide film 22 is formed on the P-type Si substrate 21, and the field oxide film 22 is formed on the element region.
A gate electrode 24 made of a polycrystalline silicon film containing phosphorus of about 4000Å is formed through a gate oxide film 23 of about 0Å. Next, using the gate electrode 24 as a mask, an acceleration voltage of 70 Ke
An n ⁻ layer (first diffusion layer) 25 is formed in the source and drain regions by ion-implanting As under the conditions of V and a dose amount of 1 × 10 ₁₂ / cm ^2.
₁ , 25 ₂ are formed (FIG. 3 (a)). After that, a SiN film 26 to be a sidewall gate insulating film is formed on the entire surface by a CVD method using dichlorosilane and ammonia to a thickness of about 500 Å, and then a SiO ₂ film 27 is 3,000 Å by a CVD method using silane gas.
To some extent (Fig. 3 (b)). Then, the entire surface is etched by a reactive ion etching (RIE) method using CF ₄ gas and H ₂ gas to leave the SiO ₂ film 27 in self-alignment with the step portion of the side wall of the gate electrode 24, and to leave the SiO ₂ film 27. Using the gate electrode 24 and the SiN film 26 on the side wall of the gate electrode 24 as a mask, an acceleration voltage of 100 KeV and a dose of 5 × 10 ¹⁵ / cm
As is ion-implanted under the condition of ² to form n ⁺ layers (second diffusion layers) 28 ₁ and 28 ₂ (FIG. 3 (c)). After that, for example, heat treatment is performed at 1000 ° C. in N ₂ for 20 minutes to activate As in the n ⁻ layers 25 ₁ and 25 ₂ and the n ⁺ layers 28 ₁ and 28 ₂ . Thus, a shallow n at low concentrations that are self-aligned to the gate region ^- the layer ₂₅ 1, 25 ₂ and high-concentration deep ^{n +} layer ₂₈ 1, 28 ₂ which source consisting of overlapping thereto, the drain diffusion layer.

After that, the SiO ₂ film 27 used as the mask material is removed, and then the entire surface is etched by the RIE method containing CF ₄ gas and H ₂ gas to leave the SiN film 26 only on the sidewall of the gate electrode 24 and the sidewall gate insulating film. Are formed, and in this state, the surfaces of the gate electrode 24 and the source / drain diffusion layers are exposed. Then, a platinum (Pt) film 29 is 500 Å on the entire surface by the sputter method.
About 550 ℃ in an atmosphere containing N ₂ gas and H ₂ gas
By performing heat treatment for 20 minutes, the Pt silicide film 3 is formed on the surface of the source / drain diffusion layer and the surface of the gate electrode 24.
0 ₁ to 30 ₃ are formed (FIG. 3 (d)). After that, the unreacted Pt film 29 is removed by etching with aqua regia (Fig. 3).
(e)). Thus, the Pt silicide films 30 ₁ to 30 are self-aligned on the source / drain diffusion layer and the gate electrode 24.
₃ can be formed.

After that, the entire surface is covered with a SiO ₂ film 31 by CVD as in the conventional case, a contact hole is opened, and a source electrode 32, a drain electrode 33 and other wiring made of an Al—Si film are formed to complete the process (FIG. 3). (f)).

According to this embodiment, on the source / drain diffusion layers, from the low resistance n ⁺ layers 28 ₁ and 28 ₂ to the high resistance n ⁻ layer 25.
Pt silicide films 30 ₁ , 30 straddling over ₁ , 25 _2
2 is provided, the n ⁻ layers 25 ₁ , 2 are provided on the gate region side.
5 ₂ and decline in gm of the drain current due to the provision is compensated. Therefore, excellent characteristics of the MOSFET can be secured while solving various problems due to miniaturization. Further and Pt silicide 30 ₃ is superimposed also on the gate electrode 24 in this embodiment, by reducing the gate electrode resistance, and summer and can higher speed operation of the MOSFET. Further, since the source and drain electrodes 32 and 33 are in contact with the Pt silicide films 30 ₁ and 30 ₂ , respectively,
The contact resistance of this portion is small, which also contributes to the improvement of MOSFET characteristics.

Further, according to the method of this embodiment, the source and drain diffusion layers and the Pt silicide film provided thereon can all be formed by self-alignment, and the reliability and the yield of the integrated circuit using the fine MOSFET can be improved. Improvement is achieved. Further, in the MOS transistor thus formed, the n ⁺ layer 2
The surfaces of 8 ₁ and 28 ₂ are Pt silicide films 30 ₁ and 30 _2.
Since it is not completely covered with, the potential increase of the n ⁻ layers 25 ₁ and 25 ₂ due to the potential of the Pt silicide films 30 ₁ and 30 ₂ is not so large, and the problem of gate breakdown does not occur.

The present invention is not limited to the above embodiment. For example, the step of forming the n ⁺ layers 28 ₁ and 28 _{2 in} the above embodiment can be performed after the step of forming the Pt silicide films 30 ₁ to 30 ₃ .
The main steps of the embodiment will be described below with reference to FIGS. 4 (a) to 4 (c). P-type Si substrate 2 as in the previous embodiment
1 to form a gate electrode 24 made of polycrystalline silicon through a gate oxide film 23, n by ion implantation using the gate electrode 24 as a mask ^- the layer 25 _1, 25 ₂ after forming a, SiN film by CVD on the entire surface 26 (FIG. 4)
(a)).

Then, SiN is formed only on the sidewall of the gate electrode 24 by the RIE method.
The n ^- layers 25 ₁ and 25 ₂ are removed through the steps of depositing the Pt film, heat-treating, and removing the unreacted Pt film while removing the film 26 and others.
Pt silicide film 3 only on the surface and the surface of the gate electrode 24
0 ₁ to 30 ₃ are formed (FIG. 4 (b)). After that, a SiO ₂ film 27 is deposited by the CVD method and is removed by RIE, leaving only the side wall of the gate electrode, and ion implantation is performed to form n ⁺ layers 28 ₁ and 28 ₂ (see FIG. 4 (c )). In this way, a structure similar to that of the previous embodiment can be obtained.

According to this embodiment, the SiO ₂ film 27 used as a mask material for diffusing the n ⁺ layers 28 ₁ and 28 ₂ can be left as it is. Therefore, the subsequent process can be performed in a state where the side wall of the gate electrode is tapered, so that disconnection of wiring can be prevented, and reliability and yield can be further improved as compared with the previous embodiment.

Further, according to the present invention, not only the order of the steps of forming the Pt silicide films 30 ₁ to 30 _{3 and} the steps of forming the n ⁺ layers 28 ₁ and 28 ₂ but also the n ⁻ layers 25 ₁ and 25 ₂ and the n ⁺ layers 28 ₁ and 28 2 ₂ and the formation process of the Pt silicide films 30 ₁ to 30 ₃ can be arbitrarily exchanged.

Furthermore, the present invention can be implemented in various modifications as listed below.

Instead of the Pt silicide film, W silicide, Ti silicide, Mo silicide or the like can be used by the same method.

Instead of the Pt silicide film, a W film that can be selectively deposited on Si by the CVP method can be used.

The gate electrode materials include polycrystalline silicon, W, Mo,
MoSi, Al, etc. can be used.

Various materials can be selected for the SiN film 26 left on the side wall of the gate electrode and the SiO ₂ film 27 serving as a mask material for diffusing the n ⁺ layer. For example, Al ₂ O ₃ , polycrystalline silicon, SiN directly nitrided polycrystalline silicon that is the gate electrode, S by thermal oxidation
An appropriate combination of iO ₂ , resist and the like can be used.

In the embodiment, the source and drain have the same structure,
The source side may have the same structure as the conventional one.

As a method for forming the silicide, a so-called ion beam mixing method can be used which implants ions of As, Si, Ar or the like into a region including the interface between the metal film and Si, without using heat treatment.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a conventional MOSFET structure, FIG. 2 is a diagram showing a MOSFET structure of one embodiment of the present invention, and FIGS. 3 (a) to (f) are diagrams showing the manufacturing process thereof, and FIG. (A)-(c) is a figure which shows the principal part manufacturing process of another Example. 21 ... P-type Si substrate, 22 ... Field oxide film, 23
...... gate oxide film, 24 ...... polysilicon gate _electrode, 25 1, 25 ₂ ...... n ^- layer (first diffusion layer), 26
...... SiN film, 27 …… SiO ₂ film, 28 ₁ , 28 ₂ …… n ⁺
Layer (second diffusion layer), 29 ... Pt film, 30 ₁ to 30 ₃ ...
... Pt silicide film, 31 ...... SiO ₂ film, 32 ...... source electrode, 33 ...... drain electrode.

Front page continuation (56) Reference JP-A-57-121278 (JP, A) JP-A-57-124476 (JP, A) JP-A-55-125649 (JP, A)

Claims (2)

[Claims] 1. A step of forming a gate electrode on a semiconductor substrate via a gate insulating film, and a step of doping impurities with the gate electrode as a mask to form a low-concentration first diffusion layer in source and drain regions. A step of forming an insulating film to be a sidewall gate insulating film on the entire surface, a step of forming a mask material in a side wall step portion of the gate electrode in a self-aligned manner, the mask material, the gate electrode and the gate electrode. Forming a second diffusion layer having a higher concentration than the first diffusion layer overlapping the first diffusion layer by doping impurities with the insulating film serving as the sidewall gate insulating film of the side wall as a mask; A step of removing the mask material, a step of removing an insulating film to be the sidewall gate insulating film other than the sidewall portion of the gate electrode to form a sidewall gate insulating film, and a step of removing the first diffusion layer surface from the first diffusion layer surface. Diffusion The method of manufacturing a semiconductor device, wherein a conductive film to span to the middle of the surface and a step of a self-aligned manner provided. 2. A step of forming a gate electrode on a semiconductor substrate via a gate insulating film, and a step of doping impurities with the gate electrode as a mask to form a low-concentration first diffusion layer in the source and drain regions. A step of forming an insulating film to be a sidewall gate insulating film on the entire surface, a step of removing the insulating film to be the sidewall gate insulating film other than the sidewall portion of the gate electrode to form a sidewall gate insulating film, A step of disposing a conductor film on the surface of the first diffusion layer in a self-aligned manner with a side wall gate insulating film; a step of forming a mask material in a side wall step portion of the gate electrode in a self-aligned manner; From the first diffusion layer that overlaps the first diffusion layer that is doped with impurities by using the gate electrode and the insulating film that serves as the sidewall gate insulating film on the sidewall portion of the gate electrode as a mask, High concentration The method of manufacturing a semiconductor device characterized by comprising a step of forming a second diffusion layer.