JPH0644628B2 - Method of manufacturing nonvolatile semiconductor memory device - Google Patents

Description

The present invention relates to a semiconductor memory, and more particularly to an electrically erasable / rewritable read-only memory (EEPROM) and a method for manufacturing the same, and more particularly to a method for manufacturing the same. The present invention relates to an insulating film on an erase gate of an EEPROM having a layer gate structure and capable of simultaneously (batch) erasing all memory cells and a method for forming the same.

(Prior Art) FIG. 4 shows a cross-sectional structure taken along the channel width direction of one memory cell in a conventional simultaneously erasable EEPROM. A semiconductor substrate 40 has a drain region, a source region, and a channel region of a memory cell transistor, and a field oxide film 41 formed as an element isolation region (memory cell isolation region). A three-layer polysilicon gate structure is provided. That is, the floating gate 43 made of polysilicon is formed on the channel region of the memory cell transistor via the first gate insulating film 42.
The lower surface of one end of the floating gate 43 is formed on the field oxide film 41 in contact with the erase gate 44 made of polysilicon, and the second gate insulating film 45 is formed on the upper surface of the erase gate 44.
Are facing through. A control gate 47 made of polysilicon is formed on the floating gate 43 via a third gate insulating film 46, and an interlayer insulating film is formed on the control gate 47.

The operating principle of the EEPROM cell with the above structure is well known, and
Similar to an EPROM (ultraviolet ray erasable / rewritable read-only memory) memory cell, a high voltage (write voltage) is applied to the drain of the selected memory cell and the control gate 47 at the time of writing to apply hot electrons to the floating gate 43. Is applied to change the threshold voltage of the cell transistor, and at the time of erasing, a high voltage (erasing voltage) is applied to the erasing gate 44 so that electrons are emitted from the floating gate 43 by its electric field. It is possible to erase all cells at the same time by applying an erase voltage to the memory cells at the same time.

Conventionally, a high temperature (for example, 1000) is formed after the erase gate 44 is formed to form the second gate insulating film 45.
The thermal oxidation is performed at (° C.), and the thermal oxidation is performed at a high temperature similarly to the above after the formation of the floating gate 43 to form the third gate insulating film 46. In this case, it is preferable that the third gate insulating film 46 has a high insulating property in order to effectively retain the electrons injected into the floating gate 43 by writing. Provides the required insulation.

The quality of the erase characteristic is determined by the film quality and thickness of the second gate insulating film 45, the processing conditions of the erase gate 44 and the floating gate 43, and the like. That is, in order to improve the erase characteristic, it is important to reduce the film thickness of the second gate insulating film 45 and increase the electric field applied between the floating gate 43 and the erase gate 44. In addition, in order to suppress fatigue breakdown of the insulating film due to erroneous erasing, erroneous writing, and repeated writing / erasing, the second
It is necessary to increase the thickness of the gate insulating film 45. Further, in order to improve the erasing characteristics, it is desirable that the second gate insulating film 45 has a low insulating property, but since the erasing gate 44 is thermally oxidized at a high temperature when the second gate insulating film 45 is formed. The surface of the erase gate 44 becomes smooth, and the insulating property of the second gate insulating film 45 increases.

As described above, the requirement for improving the erasing characteristics with respect to the film thickness of the second gate insulating film 45 and the requirement for preventing erroneous erasing and erroneous writing fatigue damage are contradictory. Was a problem. Further, it has been a subject to materialize a forming method for obtaining a desirable film quality as the second gate insulating film 45.

(Problems to be Solved by the Invention) The present invention is of an electrically erasable / rewritable type capable of forming a gate insulating film satisfying the requirement for the gate insulating film between the erase gate and the floating gate as described above. A method for manufacturing a nonvolatile semiconductor memory device is provided.

[Structure of Invention]

(Means for Solving the Problems) According to the method of manufacturing an EEPROM of the present invention, the memory cell is formed when each region of the memory cell transistor is formed on the surface of the semiconductor substrate and then a gate having a three-layer structure is formed on the semiconductor substrate. An erase gate made of polysilicon is formed directly on the field oxide film for the isolation region, then a gate insulating film is formed on the erase gate by a thermal oxidation method, and then a channel of the memory cell transistor is formed on the semiconductor substrate. A floating gate made of polysilicon is formed so as to face the region and the erase gate, and a thermal oxidation method at a higher temperature than a thermal oxidation method for forming a gate insulating film on the erase gate is then applied to the floating gate. A gate insulating film is formed, and then a control gate is formed so as to face the floating gate. , When forming the gate insulating film on the erase gate, make the film thickness almost 1/4 or more of the film thickness of the gate insulating film on the floating gate 1/2
It is characterized in that setting control is performed as follows.

(Operation) According to the above-described method of manufacturing the EEPROM, when forming the gate insulating film on the erase gate, the gate insulating film is formed to have an appropriate film thickness in terms of improving erase characteristics and preventing fatigue damage. Moreover, since the thermal oxidation method which is lower than the temperature when forming the gate insulating film on the floating gate is used,
As the film quality of the gate insulating film on the erase gate, a low insulating property can be obtained, and the erase characteristic is improved.

(Embodiment) An embodiment of the method for manufacturing the EEPROM of the present invention will be described in detail below with reference to the drawings.

FIGS. 1 (a) to 1 (c) show cross-sectional structures of semiconductor wafers at respective stages of the process for forming the three-layer polysilicon gate structure of the EEPROM. That is, as shown in FIG. 1 (a), a field oxide film 2 for a memory cell isolation region is formed on a surface of a semiconductor substrate (for example, a silicon substrate) 1, and drain regions are formed on both sides of a channel region of a memory cell transistor. After forming the source region and the source region, the first gate insulating film 3 is formed on the surface of the substrate by a high temperature oxidation method. Next, a polysilicon film is deposited on the entire surface of the substrate by a CVD method (chemical vapor deposition method) so as to have a constant film thickness, and then the erase gate 4 is left on a part of the field oxide film 2. The polysilicon film is etched. Then, the entire surface of the substrate is thermally oxidized by, for example, a thermal oxidation method at 950 ° C. to form the second gate insulating film 5 having a constant film thickness on the erase gate 4. In this case, if a diluting oxidation method in which an inert gas (for example, N ₂ gas, Ar gas) is mixed at a predetermined ratio in an oxidizing atmosphere for thermal oxidation, the second gate insulating film 5 has a constant film thickness. Can be stably formed. Next, as shown in FIG. 1 (b), a polysilicon film is deposited on the entire surface of the substrate by a CVD method so as to have a constant film thickness, and then a field oxide film is formed from above the channel region of the memory cell transistor. The polysilicon film is etched so that the floating gate 6 is left over a part above 2 and a part of the erase gate 4. Next, the upper surface of the substrate is thermally oxidized by a thermal oxidation method at a high temperature (for example, 1000 ° C.) to form a third gate insulating film 7 having a constant film thickness on the floating gate 6. In this case, the above-mentioned gate insulating film can be stably formed to have a constant film thickness by using the above-described dilution oxidation method using an inert gas. Next, as shown in FIG. 1 (c), a polysilicon film is deposited on the entire surface of the substrate by a CVD method so as to have a constant film thickness, and then the control gate 8 facing the floating gate 6 is left. Thus, the polysilicon film is etched. After that, an interlayer insulating film is deposited and formed on the upper surface of the substrate by the CVD method, and a contact hole for making a contact with the control gate 8 and a contact hole for making a contact with the erase gate 4 are opened to form a metal film. After forming (for example, an aluminum film) by vapor deposition, wiring patterning is performed.

In the present embodiment, the thickness of the third gate insulating film 7 is set to about 750Å in order to form an EEPROM cell that uses, for example, 21.0 V as a write voltage and an erase voltage and 5.0 V as a read voltage. The thickness of the second gate insulating film 5 is set to 1/4 or more of the thickness of the third gate insulating film 7 to 1/2.
It is set within the range up to the following (for example, 250Å).

According to the EEPROM having the three-layer polysilicon gate structure as shown in FIG. 1 (c) formed by the method of the above embodiment, the third gate insulating film 7 has a sufficient film thickness by thermal oxidation at high temperature. Since it is formed of, the insulating property is very good, and it is possible to effectively retain the electrons injected into the floating gate 6 by writing. Further, the second gate insulating film 5 is the third gate insulating film 7 described above.
Is formed by thermal oxidation of the erase gate 4 under the condition of a temperature lower than 1000.degree. As a result, the surface state of the erase gate 4 is not smooth, and the film quality of the second gate insulating film 5 is low. Therefore, when the erase gate 4 is applied with a high voltage (erase voltage), it floats. The electric field generated between the gate 6 and the erase gate 4 is increased, and the characteristic (erase characteristic) in which electrons are emitted from the floating gate 6 to be in an erased state is improved.

In addition, the thickness of the second gate insulating film 5 is 3 as described above.
For the EEPROM of 00Å, the relationship between the erase voltage application time (erase pulse width) and the number of memory cells (bit number) that have not been erased out of the entire memory cells was measured.
The characteristics shown by the solid line in FIG. 2 were obtained. Further, as a result of measuring the relation between the erase voltage application time and the memory cell transistor threshold voltage for one memory cell in the EEPROM, the threshold voltage before programming is restored in a short time as shown by the solid line in FIG. The characteristic (that is, the erase speed is fast) was obtained. On the other hand, for comparison, the characteristics of the EEPROM in which the film thickness of the second gate insulating film 5 is 1/2 or more of the film thickness of the third gate insulating film 7 (for example, 750Å), for example, 400Å are shown in FIG. , Each of which is shown by a dotted line in FIG. As can be seen from the comparison of the above characteristics, the EEPR of this example
According to OM, the film thickness of the second gate insulating film 5 is appropriate in terms of improving erase characteristics. Further, according to the EEPROM of this embodiment, it was confirmed that the second gate insulating film 5 has sufficient resistance to fatigue damage due to repeated writing / erasing. The prevention of such fatigue damage and the improvement of the erasing characteristics are achieved by setting the thickness of the second gate insulating film 5 within the range of 1/4 to 1/2 of the thickness of the third gate insulating film 7. It was confirmed that it can be realized by setting to.

〔The invention's effect〕

As described above, according to the method of manufacturing the EEPROM of the present invention, the film of the gate insulating film on the erase gate is formed so as to satisfy the requirements in terms of improving the erase characteristics and preventing fatigue breakdown with respect to the gate insulating film on the erase gate. The thickness and film quality can be formed.

[Brief description of drawings]

FIGS. 1 (a) to 1 (c) are views showing a cross-sectional structure of a semiconductor wafer in respective steps in forming a three-layer polysilicon gate structure according to an embodiment of the method for manufacturing an EEPROM of the present invention, and FIG. FIG. 1 (c) is a characteristic diagram showing the relationship between the erase voltage application time and the number of unerased cells of the EEPROM having the EEPROM cell, and FIG. 3 is the same as the erase voltage application time of the EEPROM cell of FIG. 1 (c). FIG. 4 is a characteristic diagram showing a relationship with a change in cell transistor threshold voltage,
The figure is a cross-sectional view showing a conventional EEPROM cell. 1 ... Semiconductor substrate, 2 ... Field oxide film, 3 ... First gate insulating film, 4 ... Erase gate, 5 ... Second gate insulating film, 6 ... Floating gate, 7 ... Third gate insulating film Membrane, 8 ... Control gate.

Claims (2)

[Claims] 1. When forming a region of a memory cell transistor on a surface of a semiconductor substrate and then forming a gate having a three-layer structure on the semiconductor substrate, a polysilicon is directly formed on a field oxide film for a memory cell isolation region. And a step of forming a gate insulating film on the erase gate by a thermal oxidation method, and so as to oppose the channel region of the memory cell transistor and the erase gate on the semiconductor substrate. The film thickness of the gate insulating film on the erase gate is formed on the floating gate by a thermal oxidation method at a higher temperature than the step of forming the floating gate made of polysilicon and the step of forming the gate insulating film on the erase gate. And a step of forming a gate insulating film whose setting is controlled within a range of approximately 2 times or more and 4 times or less. A method of manufacturing a nonvolatile semiconductor memory device, comprising: forming a control gate so as to face the swing gate. 2. The non-volatile according to claim 1, wherein when forming a gate insulating film on the erase gate, a diluting oxidation method in which an inert gas is mixed in an oxidizing atmosphere is used. Manufacturing method of semiconductor memory device.