JPH0644632B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a semiconductor memory device, and is particularly used for a fine non-volatile memory.

(Prior Art) A conventional non-volatile memory will be described with reference to FIGS. FIG. 5 is a pattern plan view, and FIG. 6 is A- in FIG.
In the sectional view taken along the line A ′, 20 is a semiconductor substrate, 21 is a source region, 22 is a drain region, 23 is an element isolation region, 24 is a floating gate, 25 is a control gate, and 26 is an insulating film. That is, in the conventional non-volatile memory, the floating gate 24 and the control gate 25 are formed on a plane. The source 21 of the transistor has a common potential, and the bit line 2 to the drain 22
Writing is performed by the contact 28 of No. 7. The drain 22 is electrically isolated from the drain of the adjacent cell by the element isolation region 23. Reference numeral 29 represents one memory cell.

(Problems to be Solved by the Invention) A conventional nonvolatile memory requires an element isolation 23 in order to form a gate electrode on a substrate surface and a drain 22 which is an independent terminal on the substrate surface. For these reasons, it was not suitable for high integration.

The present invention has been made in view of the above circumstances, and an object of the present invention is to solve the above problems of the related art and to provide a semiconductor memory device suitable for high integration.

[Structure of the Invention] (Means and Actions for Solving Problems) The present invention relates to a first conductivity type semiconductor substrate, a hole formed on the substrate, and electrically isolated from a side wall portion of the hole. A first gate electrode formed in a state, a first gate insulating film disposed between a sidewall of the hole and the first gate electrode, and a state of covering the first gate electrode. A second gate electrode, a second gate insulating film disposed between the first gate electrode and the second gate electrode, and an end facing the first gate electrode at the bottom of the hole. And a second semiconductor of the second conductivity type formed in a depth that partially opposes the first gate electrode on the surface of the semiconductor substrate. A wiring layer and a wiring layer formed in contact with the first semiconductor layer through the hole. A transistor is formed in which one of the first and second semiconductor layers is a source, the other is a drain, and the sidewall of the hole is a channel, and the first gate electrode is a hot transistor generated near the channel. It is characterized in that it becomes a floating gate into which carriers are injected. That is, the object of the present invention is to form a vertical transistor of a hole-embedded type in a semiconductor substrate, insert a drain (or source) having an independent potential into the bottom of the hole, and eliminate an element isolation region. Is to achieve.

Embodiment An embodiment of the present invention will be described below with reference to the drawings. First
The figure is a cross-sectional view showing the same embodiment, 1 is a P-type substrate, 2 is a first gate oxide film, 3 is a first gate electrode, and 4 is a second gate electrode.
Gate oxide film, 5 is a second gate electrode, 6 is an N-type drain (or source) layer, 7 is an N-type source (or drain) layer, 8 is an interlayer insulating film, 9 is a metal wiring layer (bit line). ) 10 is a hole and 11 is a channel region.

That is, the structure of this device is such that the P-type substrate 1 is provided with the hole 10, the side wall of the hole 10 is provided with the first gate electrode 3 formed in an electrically isolated state, and the side wall of the hole 10 is provided. A first gate oxide film 2 between the first gate electrode 3 and the first gate electrode 3, a second gate electrode 5 is provided so as to cover the first gate electrode 3, and the first gate electrode 3 and the second gate electrode 3 are provided. The second gate oxide film 4 is provided between the electrode 5 and the drain layer 6 at the bottom of the hole 10 so that the end of the first gate electrode is in contact with the first gate electrode 3 on the surface of the substrate 1. A source layer 7 formed to a part of such a depth is provided, and a metal wiring layer 9 in contact with the drain layer 6 through a hole 10 is provided. As a result, a transistor having the side wall of the hole 10 as the channel region 11 is formed, the first gate electrode 3 becomes a floating gate into which hot carriers generated immediately below the channel are injected, and the second gate electrode 5 becomes the control gate. It will be.

FIG. 2 is an explanatory diagram of how to make FIG.
Opening 1.0 × in the semiconductor substrate 1 of Ωcm (specific resistance)
A hole 10 having a depth of about 1.0 μm ² and a depth of about 1.5 μm is formed with a taper angle of 3 °, and a first gate oxide film 2 is formed on the surface of the substrate to a thickness of about 400 Å (FIG. 2 (a)). Then first
The gate electrode (for example, polysilicon) 3 is formed on the side wall of the hole 10 (FIG. 2 (b)). Next, an N-type layer (drain) 6 and an N-type layer (source) 7 having an impurity concentration of about 10 ²⁰ cm ⁻³ are formed on the bottom of the hole 10 and the substrate surface (FIG. 2).
(c)). Next, a second gate oxide film 4 is formed on the surface of the first gate electrode 3 to a thickness of about 200 Å (FIG. 2 (d)). After that, a second gate electrode (for example, polysilicon) 5 is patterned and used as a word line (FIG. 2 (e)). Next, after the interlayer insulating film 8 is formed as shown in FIG. 1, the insulating films 8 and 2 on the drain layer 6 are removed in a self-aligning manner by RIE (reactive ion etching) method. The metal wiring 9 is formed so as to be in contact with.

With such a configuration, when the opening of the hole 10 is 1.0 × 1.0 μm ² and the depth is 1.5 μm as described above,
The coupling ratio (C ₁ + C ₂ / C ₂ ... Numerical value indicating the quality of the device performance) is Becomes Where θ is the taper angle, _tox1 is the thickness of the first gate oxide film 2, and _tox2 is the second gate oxide film 4.
Thickness, C ₁ is the capacitance due to the first gate oxide film 2, C ₂
Is the capacitance due to the second gate oxide film 4. As described above, the taper angle θ = 3 °, _tox1 = 400Å, _tox2 =
If it is 200Å, the coupling ratio becomes 1.57,
It is almost the same as that of the configuration according to the related art.

FIG. 3 is a pattern plan view around FIG. 1, and 31 indicates one cell as shown in FIG.

In FIG. 1, the substrate surface is only the N-type layer 7, which has a common potential, and thus does not require an element isolation region. Further, since the N-type layer 6 and the metal wiring 9 are in contact with each other in a self-aligning manner, the minimum size that can be produced by the IC as shown in FIG. 4 is only the size l ₁ of the hole 10 and the space l ₂ between the holes. Well, if the minimum size that can be manufactured by IC is F, the cell area can be reduced to 4F ² . On the other hand, in the conventional technique, as shown in FIG.
As shown in FIG. 6, the vertical direction is 2F (control gate 25
Is F and the distance between the control gates 25 is considered to be F, which is 2F in total. In the lateral direction, the width of the element isolation region is F, the distance between the element isolation regions is F, and the total is 2F.
Since there is an overlapping portion α between the floating gate 24 and the element isolation region 23, the total is 2 (F + α). Therefore, the cell area is limited to “4F ² + 4Fα”. Further, when the same minimum dimension F is used, the conventional technique has a large restriction due to the design of the transistor, whereas the present invention has a vertical channel, so that the effective channel length is about the depth of the hole 10. Therefore, the minimum size of transistor that can be manufactured by IC is F
It can be designed independently.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a semiconductor memory device having advantages such as being suitable for high integration.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention, FIG. 2 is a manufacturing process drawing thereof, FIG. 3 is a pattern plan view thereof, FIG. 4 is a substrate surface view for explaining its effect, and FIG. FIG. 6 is a plan view of a conventional device, and FIG. 6 is a sectional view taken along the line AA '. 1 ... semiconductor substrate, 2 ... first gate oxide film, 3 ...
First gate electrode, 4 ... Second gate oxide film, 5 ...
Second gate electrode, 6, 7 ... Drain, source region,
8 ... Insulating film, 9 ... Metal wiring layer, 10 ... Hole, 31 ...
... 1 cell.

Claims (2)

[Claims] 1. A semiconductor substrate of a first conductivity type, a plurality of holes formed in the substrate, and a first gate electrode formed in a side wall portion of each hole in an electrically arcuate state. A second gate electrode formed in a state of covering the first gate electrode, a second conductivity type first semiconductor layer formed in an island shape at the bottom of each hole, and a surface of the semiconductor substrate And a wiring layer in contact with the first semiconductor layer through the hole, and a second conductive type second semiconductor layer commonly formed in each memory cell. 2. The first semiconductor layer is a drain layer, the second semiconductor layer is a source layer, and the sidewall of the hole is a channel region. The semiconductor memory device according to claim 1.