JPH0644702B2 - Digital filter device - Google Patents

Description

The present invention relates to a digital filter device for musical tone signals, and is used in electronic musical instruments and other devices having a musical tone generating function, digital voice processing devices, and the like.

[Conventional technology]

The use of a digital filter in the tone color circuit of an electronic musical instrument is disclosed in, for example, Japanese Patent Laid-Open No. 59-44096.

[Problems to be solved by the invention]

In the conventional digital filter, if the filter order is set to a predetermined order by design, the order of the filter circuit is fixed to that order in terms of hardware.

Therefore, there is a problem that the filter characteristics (amplitude-frequency characteristics) that can be realized are limited according to the order fixed by hardware. For example, the frequency response characteristic of an odd-order filter having an impulse response as shown in FIG. 6 is as shown in FIG. 8, whereas the frequency response characteristic of an even-order filter having an impulse response as shown in FIG. The response characteristics are as shown in FIG. Eighth if order N is odd
As shown in the figure, ω = π (where π is the sampling frequency c
(corresponding to 1/2 of s) is not fixed to 0 and can be set arbitrarily. When N is an even number, the level at ω = π necessarily becomes 0 as shown in FIG. As is clear from this, when the order N is odd, it is possible to realize the high-pass filter characteristic by setting the filter coefficient, but when N is even, it is difficult to realize the high-pass filter characteristic. . As described above, there is a problem that there is a filter characteristic that cannot be realized (or is difficult) with an order fixed in terms of hardware. One solution to this problem would be to include multiple filters with different characteristics in parallel or in series, which would result in another problem of increased hardware configuration.

The present invention has been made in view of the above points, and an object thereof is to provide a digital filter device capable of realizing more filter characteristics with an extremely simple hardware configuration.

[Means for solving problems]

The digital digital apparatus according to the present invention inputs digital sample value data of a musical tone signal sampled in accordance with a predetermined sampling period, sequentially delays the data, and provides a maximum of n digital sample value data with sampling points sequentially shifted. A digital filter circuit having a delay means for performing a filter operation by calculating a plurality of digital sample value data whose sampling times are sequentially shifted and a filter coefficient provided by the delay means, and a filter operation. Parameter generating means for generating an even-odd parameter for setting the order of the even number or the odd-numbered degree, and the plurality of digital sample value data used in the filter calculation in the calculating means, depending on the even-odd parameter. The following predetermined even or odd Select the number of sampled data, the other delayed sample value data is characterized in that comprises the excluded switching means from said filter operation.

This is schematically shown in FIG. 110
Is a digital filter circuit, 111 is a parameter generating means, and 112, 113 and 114 are gates or selectors as switching means. 1 (a), (b),
(C) illustrates different embodiments of the switching means 112, 113, 114, respectively, and the parameter generating means 111 is not shown in (b) and (c). D is a unit delay element, a circular box with an X symbol is a multiplication element,
A round box with a + sign indicates an addition element. The digital filter circuit 110 has a hardware configuration capable of performing a predetermined n-th order (for example, n = even number) filter operation. Parameter generating means 111, steady tone color selection information, the key touch, generates filter coefficients k ₁ to k _n and even-odd parameter E / O that realizes a predetermined tone according to the tone color determining factors range like. The filter coefficients k _{1 to} k n corresponding to the respective orders _{1 to n} are given to the digital filter circuit 110, and are multiplied by the musical tone signal delayed by the delay time corresponding to the order.

[Action]

The digital filter circuit selectively operates as an even-order filter or an odd-order filter according to the delay order switching operation performed by the switching means according to the even-odd parameter. As a result, the digital filter circuit can be operated by switching to either the even-order filter or the odd-order filter according to the tone color to be realized, and any filter characteristic suitable for the tone color can be realized. For example, if you want to achieve a timbre that is suitable to be controlled by the high-pass filter characteristics, set it to an odd-order filter, and if you want to achieve a timbre that is suitable to be controlled by the bid-pass filter or low-pass filter characteristics, set it to an even-order filter. To do.

In the case of FIG. 1A, the gate 112 as the switching means is provided between the delay element corresponding to the (n-1) th order and the delay element corresponding to the nth order, and the even / odd parameter E / O indicates the even order. The gate 112 is opened when the value is "0", and the gate 112 is closed when the value is "0". When the gate 112 is opened, the digital filter circuit 110 operates as an nth-order or even-order filter, and when the gate 112 is closed, it operates as an n-1th-order or odd-order filter.

In the case of FIG. 1 (b), the output A of the addition element obtained by summing all the filter operation results for the nth order and the output B of the addition element obtained by summing the filter operation results for the n-1th order are the switching means. It is input to the selector 113, and either A or B is selected according to the value of the even / odd parameter E / O. When A is selected, it becomes an nth-order filter, that is, even-order filter, and when B is selected, it becomes an n-1th-order filter, that is, odd-order filter.

In the case of FIG. 1 (c), the nth-order filter coefficients Kn and O
One of them is selected by the selector 114, which is the switching means, according to the even / odd parameter E / O, and this selected output is multiplied by the output musical tone signal of the delay element corresponding to the n-th order. When Kn is selected, the filter is an nth-order filter, that is, an even-order filter, and when “0” is selected, the filter is an n−1th-order filter, that is, an odd-order filter.

〔The invention's effect〕

Therefore, according to the present invention, the delay order of the sample value data used in the filter operation in the digital filter circuit is switched to the even order or the odd order according to the even / odd parameter, so that the hardware configuration of the filter circuit is not increased. It is now possible to realize even-order or odd-order filter characteristics, and it is possible to realize an even richer tone color control with a filter circuit that is saved in terms of both configuration and cost. Play.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

<Description of Overall Configuration of One Embodiment> In FIG. 2, the keyboard 10 is provided with a plurality of keys for designating the pitch of a musical tone to be generated. The key touch detector 11 detects a touch applied to the key pressed by the keyboard 10, and may detect either an initial touch or an after touch. The tone color selection device 12 comprises a group of operators for selecting the tone color of a musical tone to be generated. The pitch bend operator 13 is for continuously modulating the pitch of the musical sound to be generated according to the operation amount thereof, and is composed of, for example, a dial type operator. The microcomputer 14 includes a CPU (Central Processing Unit) 15, a ROM (Read Only Memory) 16 for storing programs and other data, and a RAM (Random Access Memory) 17 for working and storing data. Data is exchanged with each circuit in the electronic musical instrument via the address bus 28, key press detection processing in the keyboard 10 and sound pressure key sound allocation processing for a plurality of sound generation channels, and tone color selection operation in the tone color selection device 12. Detection processing, the operation amount detection processing in the pitch vent operator 13, and other various processings.

The tone generator 18 is capable of independently generating digital musical tone signals in a plurality of tone generation channels, and a key code K indicating a key assigned to each channel.
C and a key-on signal KON indicating ON / OFF of the key and other necessary data from the microcomputer 14 to the bus 2
8 via which the digital tone signal is generated in each channel. The tone generator 18 includes a pitch synchronization signal generation circuit 19 therein and generates a pitch synchronization signal for each channel in synchronization with the pitch of the tone signal generated in each channel.

In the specifications of this embodiment, the tone generator 18
Generates a digital tone signal in a time division manner on a total of 16 channels of the first to 16th channels (Ch1 to Ch16). Digital tone waveform sample value data output from the tone generator 18 in a time-division multiplex manner is TDX
Indicate. The master clock pulse φ generated from the master clock generator 20 controls the basic operation time of the tone generator 18. One cycle of time division multiplexing of the digital tone waveform sample value data TDX is 64 cycles of the master clock pulse φ, and one time slot in each cycle in this one cycle 64 cycles is 1 cycle.
It is as shown in FIG. The figure also shows the specifications of the channel timings 1 to 16 of the multiplexed digital tone waveform sample value data TDX. For example, the first channel data TDX is assigned to the four slots of the time slots 33 to 36.

According to the specifications of this embodiment, the tone waveform sampled value data TDX is commonly output with 16 channels of data multiplexed as described above, but the pitch synchronization signals PS1 and PS2 of each channel are divided into two systems. And is time-division multiplexed for every eight channels and output. One of the pitch synchronization signals PS1 is a time division multiplexed first to eighth (Ch1 to Ch8) pitch synchronization signals, and its channel timing is as shown in FIG. The other pitch synchronization signal P
S2 is the time division multiplexed 9th to 16th (Ch9 to Ch16) pitch synchronization signals, and its channel timing is as shown in FIG. As is clear from the figure, the pitch synchronization signals PS1 and PS2 of each channel are generated with a width of one time slot, and one cycle of the time division multiplexing is eight time slots.

Two series of adaptive and digital filter devices (hereinafter A
DF (which may be abbreviated as DF) 21 and 22 are digital filter devices configured to be suitable for filtering musical tone signals. According to the specifications of this embodiment, musical tone signals for eight channels each can be filtered. , One ADF 21 filters the tone signals of the 1st to 8th channels, and the other ADF 21 filters the 9th to 16th.
Filters the tone signal of the channel. This A
Inside the DFs 21 and 22, a digital filter circuit of a predetermined type, a filter parameter memory, various circuits for controlling the supply of filter parameters, and a control circuit for performing a filter calculation operation in synchronization with the pitch of a tone signal to be filtered. , A circuit for various functions such as a pitch-synchronized output circuit for outputting a filtered musical tone signal in synchronism with the pitch, and a configuration suitable for filtering the musical tone signal.

The digital musical tone sample value data TDX output from the tone generator 18 is input to the ADFs 21 and 22. The pitch synchronization signals PS1 of the first to eighth channels are input to the ADF 21, and the pitch synchronization signals PS2 of the ninth to 16th channels are input to the ADF 22. In the ADFs 21 and 22, the pitch synchronization signal PS1,
The data TDX of the channel corresponding to the time slot in which the PS2 is generated (becomes a signal "1") is taken in internally, and the filter operation is executed on the one sample value data of that channel. Therefore, in one ADF21,
The tone signals of the first to eighth channels are filtered according to the pitch synchronizing signal PS1, and the other ADF 22 performs the filter computation of tone signals of the ninth to sixteenth channels according to the pitch synchronizing signal PS2. Thus AD
The unit time of the filter calculation in F21 and F22 (the signal delay time synchronized with the sampling cycle) becomes synchronized with the pitch of the musical tone signal to be filtered, and the filter calculation unit time varies according to the pitch, so that the moving formant characteristic is changed. The filtering of is realized. In order to control the basic operation timing of the circuit, the master clock pulse φ and the system synchronization pulse SYN
C is provided to ADFs 21 and 22. The system sync pulse SYNC is a pulse generated in a 64 time slot cycle as shown in FIG. 3, and is synchronized with one cycle of time division multiplexing of a digital tone signal. Also, A
Various data for controlling the filter operation are given to the DFs 21 and 22 via the bus 28 under the control of the microcomputer 14.

Further, in the ADFs 21 and 22, not only the actual filter calculation operation is performed in synchronization with the pitch of the musical tone signal to be filtered, but also the filtered musical tone waveform sample value data is resampled in synchronization with the pitch. , It is designed to output in the state of being completely pitch synchronized. In order to resample the filtered data in synchronization with the pitch, the pitch synchronization signals PS1 and PS
2 is used.

The digital tone waveform sample value data of each channel outputted from the ADFs 21 and 22 are summed by the accumulator 23, and tone waveform sample value data obtained by summing the sample value data of 16 channels is obtained. Accumulator 2
The output data of No. 3 is converted into an analog musical tone signal by the digital / analog converter 24, and is sounded via the sound system 25.

In the specifications of this embodiment, the supply of filter coefficients is controlled in two modes. One is "static mode"
This is a mode in which the filter coefficient is not changed during the musical tone generation period. The other is a "dynamic mode", which is a mode in which the filter coefficient is temporally changed during the tone generation period of a musical tone, and temporal changes in tone color due to filtering can be obtained. The filter coefficients for the static mode are stored in the filter parameter memory inside the ADFs 21 and 22. The filter coefficient for the dynamic mode is stored in the parameter memory 26 for dynamic control, which is read out while being switched under the control of the microcomputer 14 and given to the ADFs 21 and 22 via the bus 28. To be Dynamic / static selection switch 27
Is a switch for selecting in which mode the supply of the filter coefficient is controlled.

As an example of the clock frequency, the master clock pulse φ is about 3.2 MHz, the repetition frequency of one time division cycle (8 time slots) of the pitch synchronizing signals PS1 and PS2 is 400 kHz, and the digital tone waveform sample is used. The repetition frequency of the time-division 1 cycle (1 operation cycle in the filter) (64 time slots) of the value data TDX is 50 kHz.

Next, a detailed example of each circuit in FIG. 2 will be described.

<Regarding Generation of Pitch Synchronization Signal> FIG. 4 shows an example of the pitch synchronization signal generation circuit 19, which generates the pitch synchronization signal PS1 of one system (first to eighth channels). The other pitch synchronizing signal PS2 is also generated by the same configuration as that shown in FIG.

The pitch synchronizing signal PS1 is generated based on the P number read from the P number memory 29 being counted by the counter 30 in a time division manner for each channel. The P number is a number indicating the number of sample points in one period of a tone waveform having a frequency corresponding to each note name C to B in a certain reference octave. When the pitch synchronizing signal PS1 is generated in time division of 8 channels as shown in FIG. 3, its basic sampling frequency (in other words, the resolution of the pitch synchronizing signal PS1) is 1/8 of the master clock pulse φ.
Frequency (for example, 400 kHz), which is common to all note names. On the other hand, since the basic sampling frequency is common, the P number of each note name shows a different value corresponding to the note name frequency. When the frequency of a certain note name in the reference octave is fn and the common sampling frequency (400 kHz) is fc, the P number corresponding to the note name is determined as follows.

P number = fc ÷ fn (1) Here, the common sampling frequency fc is fc = 400 kHz,
Assuming that the frequency fn of the note name A is fn = 440 Hz (that is, A4 note), the P number of the note name A is P number of the note name A = 400000 ÷ 440 = 909 from the above formula.

On the other hand, assuming that the number of sampling points of different sampling point amplitude values per one cycle of the tone waveform that can be generated in the tone generator 18 is 64, the effective sampling frequency fe of the frequency fn is fe = fn × 6 (2) , Fn = 440 Hz, fe = 440 × 64 = 28160 Hz.

Similarly, the P number and effective sampling frequency fe of each note name in a certain reference octave can be determined as shown in the table below. In this case, the reference octave is one octave from the G4 note to the F # note.

In the counter 30 of FIG. 4, the pitch synchronization signal PS1
Is obtained by dividing the common sampling frequency fc established based on the master clock pulse φ according to the P number. As is clear from the above, the P number is 1.
It is the number of cycles of the common sampling frequency fc in the periodic waveform, that is, the number of sampling points. On the other hand, the effective number of sampling points per period of the tone waveform that can be generated by the tone generator 18 is 64 as described above. Therefore, if the frequency division number for dividing the common sampling frequency fc is frequency division number = P number / 64 (3), 64 pulses can be obtained per tone cycle of the musical tone as the frequency division output. Can establish all 64 effective sample points. When the common sampling frequency fc is divided by the division number determined in this way, fc ÷ division number = (fn × P number) ÷ (P number ÷) from the equations (1), (2), and (3) above. 64) = fn × 64 = fe (4), and the effective sampling frequency fe can be established by changing the sampling point address by this frequency division output. The effective sampling frequency fe thus established is in harmony with the pitch name frequency fn, and pitch synchronization is realized. The pitch synchronizing signal PS1 of each channel generated from the counter 30 corresponds to the note name of the key assigned to that channel, and is a frequency-divided output signal as shown in the above equation (4), that is, a signal having an effective sampling frequency fe. Is.

By the way, the frequency division number determined by the above equation (3) is not always an integer, and often includes a decimal. For example, in the case of the note name A, the frequency division number = 909 ÷ 64≈14.20. Therefore, the frequency division operation in the counter 30 is appropriately divided by two integers close to the frequency division number determined by the equation (3), and an average result of the frequency division number determined by the equation (3) is described later. I am trying to get the same result as dividing by.

In FIG. 4, the P number memory 29 stores in advance the P number of each note name in the reference octave as shown in Table 1 above. The key code KC of the key assigned to each channel is transmitted via the bus 28 to the tone generator 1
8 and the key code KC of the first to eighth channels is provided inside the tone generator 18 as P of FIG.
The time division multiplexing is performed at the timing shown in the channel timing of S1, and the key codes KC of the 9th to 16th channels are time division multiplexed at the timing shown in the channel timing of PS2 in FIG. Thus, the time-division multiplexed key codes KC of the first to eighth channels
Is input to the P number memory 29. P number memory 2
9 is the input key code KC of the first to eighth channels
The P number is read out in a time-divisional manner corresponding to the note name.

The counter 30 inputs an P-number read from the P-number memory 29, an adder 31 that inputs the output of the adder 31 to a “0” input, and an output of the select 32 that inputs 8 Stage shift register 3
3, a gate 34 that gates the lower bit (fractional part) of the output of the shift register 33 and supplies it to the other input of the adder 31, and an upper bit (integer part) of the output of the shift register 33 that inputs all bits Includes an adder 35 for adding with an all "1" signal consisting of 7 bits of "1".
Although the P number itself is a 12-bit binary coded signal, the output of the adder 31 is made up of a 13-bit signal including one extra bit as a carry signal bit.

The inverted key-on pulse {circle over ()} and the signal output from the carry-out output CO of the adder 35 are input to the AND circuit 36, and the output of the AND circuit 36 is added to the selection control input of the selector 32. When the output signal of the AND circuit 36 is "0", the signal given to the "0" input of the selector 32 from the adder 31 is selected, and when it is "1", the signal given to the "1" input is selected. To be done. To the “1” input of the selector 32, a 13-bit signal composed of the lower bit (fractional part) of the output of the shift register 33 and the 7-bit output (integer part) of the adder 35 is given. The key-on pulse KONP is a signal which becomes "1" only once when the key is pressed, and signals corresponding to the first to eighth channels are time-division multiplexed. Reverse key-on pulse ▲
▼ is a signal obtained by inverting the key-on pulse KONP.

The parts of the selector 32, the shift register 33, and the adder 35 establish the frequency division number as shown in the equation (3) according to the P number, and the common sampling frequency fc of the common frequency fc according to the integer part of this frequency division number. This is a circuit for frequency division. Adder 31
Is for adjusting the value of the integer part according to the decimal part of the frequency division number.

Since the divisor 64 is 2 ⁶ in the above formula (3), the lower 6 bits of the P number are simply handled as the decimal part to deal with the P number without performing any special division in order to obtain the frequency division number. It is possible to establish a frequency division number. Therefore,
Of the 13 bits of the output signal of the adder 31, the selector 32, and the shift register 33, the lower 6 bits are the weight of the decimal part, and the upper 7 bits are the weight of the integer part.

Adding all "1" signals in the adder 35 is equivalent to subtracting one. Therefore, the adder 35 effectively subtracts 1 from the integer value of the output of the shift register 33. The subtraction result of the adder 35 is returned to the “1” input of the selector 32 together with the uncalculated fractional 6-bit data, and is input again to the adder 35 via the shift register 33. Since the shift register 33 is shift-controlled by the master clock pulse φ, the cycle in which the signal of the same channel is output from the shift register 33 is eight times the cycle of the master clock pulse φ, that is, the cycle of the common sampling frequency fc.

At the beginning of pressing a key, the inverted key-on pulse ▲ ▼ becomes “0” only once in the channel timing system to which the key is assigned. At this time, the selector 32 outputs “0”.
The P number of the key is selected via the input. The integer part of this P number is given from the shift register 33 to the adder 35, and 1 is repeatedly subtracted from the integer part at the cycle of the common sampling frequency fc. When the result of the subtraction of the integer part is 1 or more, the carry-out signal "1" is continuously output from the carry-out output CO of the adder 35, and the condition of the AND circuit 36 is satisfied. Therefore, the selector 32 is "1". Continue selecting inputs. The adder 3 will eventually be added by repeating the subtraction.
When the output of 5 becomes "0", that is, when the period of fc equal to the number of integer parts of the P number elapses, the carry-out signal of the adder 35 is not output and the condition of the AND circuit 36 is not satisfied. . At that time, the selector 32 selects the “0” input, and the lower 6 of the P number and the output of the shift register 33 are selected.
The output of the adder 31 which is added with the bit (fractional part data) is selected. In this way, the P number having a value slightly changed by the addition of the fractional part is given to the shift register 33, and the subtraction of 1 from the integer value of the changed P number is repeated. The gate 34 has a reverse key-on pulse ▲
It is disabled only when the key is pressed by ▼, and the decimal part data is always given to the adder 31 at other times. The integer value of the frequency division number actually used for frequency division by the addition of the fractional part data to the P number in the adder 31 may become one larger than the integer value of the frequency division number obtained from the P number. For example, the P number of the note name A is 909, and the frequency division number is 14.20. At first, the frequency division is performed according to the integer value 14, but next, 14.20 + 0.2.
0 = 14.40, and eventually 15.00, and the frequency division is performed according to the integer value 15. Thus, P
The common sampling frequency fc is divided according to a number equal to or larger than the integer value of the division number obtained by the number, and as a result, the dividing operation according to the division number obtained by the P number is achieved. To be done. The signal of the carry-out output CO of the adder 35 corresponds to the frequency-divided output thereof, and the signal obtained by inverting this by the inverter 37 is output as the pitch synchronization signal PS1.

For better understanding, take note name A as an example and select selector 32
An example of a change in the output of is shown. The change timing is the cycle of the common sampling frequency fc. The first is P number 909
The division number corresponding to is 14.20, and then the integer value is decreased by 1 to 13.20. Below, 12.20, 11.20, 10.20,… 2.2
0, 1.20 and its integer value decrease by one. fc 14
The value added to the "1" input of the selector 32 in the cycle is 0.
20, the carry-out signal becomes "0", the pitch synchronization signal PS1 becomes "1", and the selector 3
In 2, the "0" input is selected. To the "0" input of the selector 32, a value 1 obtained by adding the fractional value 0.20 given from the shift register 33 to the frequency division number 14.20 corresponding to the P number 909 1
4.40 is given. Therefore, 14.40 is the selector 32
Is output from. After that, the output of the selector 32 is 13.40, 1
2.40, 11.40 ,. And the pitch synchronization signal PS1 is generated. At this time, the output of the adder 31 is 14.20 + 0.40 = 14.60
Which is given to the shift register 33 via the “0” input of the selector 32. Thus, in the case of the note name A, the frequency division is performed with 14 or 15 as the frequency division number, and 14 or 15 of the common sampling frequency fc (for example, 400 kHz) is performed.
The pitch synchronization signal PS1 becomes "1" every cycle.

The pitch synchronization signal PS2 corresponding to the other 9th to 16th channels is also generated in the same manner as described above.

<Explanation of Tone Generator> The tone generator 18 uses the pitch synchronization signals PS1 and PS2 of each channel generated as described above to generate the tone signal in accordance with the sampling timing synchronized with the pitch of the tone to be generated. You can Of course, the present invention is not limited to this, and it is also possible to generate the musical tone signal according to the sampling timing which is not synchronized with the pitch.

The address data designating the salpuru point address (instantaneous phase angle) of the musical tone to be generated can be generated by independently counting the pitch synchronization signals PS1 and PS2 of each channel for each channel. However, the pitch synchronization signals PS1 and PS2 are the same as the reference octave (G
4 to F # 5 tone), when the address data is generated, the count rate at the time of counting the pitch synchronizing signals PS1 and PS2 is set in accordance with the octave range of the musical tone to be generated. Need to switch.
For example, when a tone of G3 to F # 4 octave is generated, 0.5 is counted each time the pitch synchronization signals PS1 and PS2 are generated, and when a tone of G4 to F # 5 octave is generated, Each time the pitch synchronization signals PS1 and PS2 are generated, 1 is counted, and when the tone of G5 to F # 6 octave is generated, the pitch synchronization signals PS1 and PS2 are generated.
Every time 2 occurs, 2 is counted. In this way, address data that changes in synchronization with the pitch and octave of the musical tone to be generated is generated for each channel, and a digital musical tone signal is generated based on this address data.

Any tone signal generation method in the tone generator 18 may be used. For example, the tone waveform sample value data stored in the waveform memory according to the above address data is sequentially read out (memory read system), or a predetermined frequency modulation operation is executed using the above address data as phase angle parameter data to perform tone waveform sample processing. A method of obtaining the value data (FM method) or a method of obtaining the tone waveform sample value data by executing a predetermined amplitude modulation operation using the address data as a phase angle parameter (A).
Any known method such as M method) may be used.
Further, when the memory reading method is adopted, the musical tone waveform stored in the waveform memory may be only one period waveform,
It is preferable that the waveform has a plurality of periods because the sound quality can be improved. A method of storing a plurality of periodic waveforms in a waveform memory and reading the waveforms is, for example, as shown in Japanese Patent Laid-Open No. 52-121313, all waveforms from the start to the end of sound generation are stored and stored in 1
A method of reading once, or as shown in JP-A-58-142396, a plurality of periodic waveforms of the attack portion and one or more periodic waveforms of the sustain portion are stored and the waveform of the attack portion is read once and then the waveform of the sustain portion is read. A method of repeatedly reading a waveform, or a plurality of discretely sampled waveforms are stored as shown in Japanese Patent Laid-Open No. 147793/1985, and the waveforms to be read are designated by sequentially switching the designated waveforms. Various methods such as a method of repeatedly reading are known,
You may employ these suitably.

<Preliminary Description of Adaptive Digital Filter> The finite impulse response (FIR) filter and the infinite impulse response (IIR) filter are basically available as operation types of the digital filter, but the adaptive digital filter device 21 of this embodiment is used. , 22 use FIR filters. First, a general description relating to the FIR filter will be given.

(A) Basic Circuit Configuration of FIR Filter FIG. 5 is a basic circuit configuration diagram of the FIR filter, where x
(n) is digital tone waveform sample value data at an arbitrary n-th sample point, which is an input signal of the FIR filter. z ⁻¹ is a unit time delay element, which sets a time delay of one sampling cycle. Therefore, x
(n-1) is digital tone waveform sample value data at the (n-1) th sample point, and x (n-N + 1) is n-N +
It is the digital tone waveform sample value data of the first sample point. N is the duration of the impulse response and corresponds to the order of the FIR filter. h (0) to h (N-1)
Is an Nth-order filter coefficient. The triangular block to which this filter coefficient is input is a multiplication element, and the data x (n) to x (n−N +) of each sample point delayed by the delay element
1) corresponding filter coefficients h (0) to h (N
-1) is multiplied. The block to which the + sign is added, to which the multiplication output is input, is an addition element, and the multiplication outputs are added together to obtain the output signal y (n).

The z-transform or transfer function of the impulse response {h (n)} of such an FIR filter is Is represented.

(B) Linear phase characteristic of FIR filter One feature of such an FIR filter is that the phase characteristic can be a linear phase. When the linear phase is used, the phase of the input and output waveforms of the filter corresponds perfectly with a linear characteristic, and the output waveform is not distorted. Therefore, it is suitable for filter processing of signals such as musical sounds, voices and audios. In the linear phase FIR filter, it is required that the phase characteristic is θ (ω) = − αω ... (6) as a function of the angular frequency ω. Here, α is a constant called phase delay. The necessary and sufficient conditions for the FIR filter having the above-mentioned linear phase characteristic are that the impulse response has symmetry as shown in the following formula (8), and the phase delay α is the duration as shown in the following formula (7). (The order of the filter) N is uniquely defined.

α = (N−1) / 2 (7) h (n) = h (N−1−n) (8) where 0 ≦ n ≦ N−1 (c) Filter coefficient symmetry (8) The fact that the impulse response has symmetry as in the equation means that the filter coefficients h (0) to h (N-1) have symmetry. That is, the linear phase characteristic described above can be realized by setting the filter coefficient with the symmetrical characteristic.

An example of the symmetry of the impulse response is as shown in FIG. 6 when the order N is odd and as shown in FIG. 7 when N is even. As is clear from the figure, n = (N-
It shows a symmetrical characteristic centered on 1) / 2. When N is an odd number, the (N-1) / 2 order is centered and the impulse responses on both sides thereof are symmetrical. When N is an even number, (N-2) / 2
The impulse response on both sides is symmetrical with the center between the next and N / 2 as the center. Since the filter coefficients of the orders at the symmetrical positions have the same value, it is not necessary to prepare the filter coefficients of all orders N, and only half of them is required. Specifically, N
Is an odd number, from the 0th order to the (N-1) / 2nd order {(N
-1) / 2} +1 filter coefficients may be prepared,
As the filter coefficients from the {(N-1) / 2} +1 order to the N-1 order, the filter coefficients at the symmetrical positions from the 0 order to the {(N-1) / 2} -1 order may be used. That is, 0th order and N
The same filter coefficient is used in −1st order, and in 1st order and N−2
Use the same filter coefficients as When N is an even number, it is sufficient to prepare N / 2 filter coefficients from the 0th order to (N-2) / 2nd order, and the filter coefficients from the N / 2th order to the N-1th order are 0. It suffices to use the filter coefficients at symmetrical positions from the next to (N−2) / 2.

(D) Frequency response of linear phase FIR filter As shown in FIGS. 6 and 7, the characteristic of frequency response H ^* (e ^jω ) of the linear phase FIR filter whose impulse response shows symmetry is illustrated in FIG. 8 and FIG. It looks like Figure 9. When N is an odd number, the level at ω = π (where π corresponds to 1/2 of the sampling frequency fs) is not fixed to 0 as shown in FIG. 8 but can be set arbitrarily. When N is an even number, the level when ω = π necessarily becomes 0 as shown in FIG. As is clear from this, when the order N is odd,
It is possible to realize the high-pass filter characteristic by setting the filter coefficient, but it is impossible to realize the high-pass filter characteristic when N is an even number. But,
When N is an even number, filter design is easier and is suitable for designing a low-pass filter or a band-pass filter.

Therefore, it is preferable to switch the even / odd order N of the filter according to the filter characteristics to be realized. In the adaptive digital filter devices 21 and 22 of this embodiment, such even / odd order N order switching is performed. It is designed so that That is, the order N is set to an even number when filtering the characteristics of the bandpass filter or the lowpass filter, and the order N is set to an odd number when the filtering of the highpass filter characteristics is performed.

(E) Other Features of FIR Filter Another feature of the FIR filter is that it has good stability because it has no feedback loop.

That is, when there is a feedback loop like the IIR filter, problems such as oscillation occur, but the FIR filter does not cause problems such as oscillation and is easy to design.

The FIR filter is also advantageous when the filter characteristics are changed with time. In this case, usually, it is necessary to prepare a set of filter coefficients corresponding to each of the filter characteristics that differ in time, but in that case, a large number of filter coefficient sets are required to reduce the time variation of the filter characteristics. It is said that To solve this problem,
Prepare two sets of filter coefficients that are separated to some extent in time,
By interpolating between the two sets of filter coefficients, a set of filter coefficients is densely generated with the lapse of time between the two sets of filter coefficients, and thus a filter characteristic that temporally changes is set by the filter coefficients generated by the interpolation. Can be considered. When the time-varying filter characteristic is realized while the filter coefficient is interpolated in real time as described above, it is not necessary to devise the filter coefficient in consideration of the instability in an FIR filter having good stability, Very advantageous.

Also, since the word length of the signal in the digital filter is finite, the signal data must necessarily be rounded within the limited word length. Such rounding causes noise, but since the FIR filter has no feedback loop, errors are not accumulated due to the rounding, which is advantageous for noise countermeasures.

Regarding the characteristics of the FIR filter as described above, for example, the book "Theory and Application of Digital"
Signal Processing "(Author: Lawrence, R. Rabiner; Bern
ard, Gold, publisher: Prentice-Hall Inc).

Next, some features of the adaptive digital filter devices 21 and 22 in this embodiment will be briefly described in advance.

(F) Method of obtaining filter coefficient The filter coefficient is obtained by analyzing an actual musical tone. Tenth Example of Procedure for Obtaining Filter Coefficient
Explaining with reference to the drawings, first, two kinds of musical tone waveforms (original musical tone waveforms) showing different tone colors are prepared by sampling from a natural musical instrument sound. For example, the original musical sound waveform 1 is a waveform of a piano sound played with a strong key touch, and the original musical sound waveform 2 is a waveform of a piano sound played with a weak key touch. Next, a fast Fourier transform is performed, and the original musical sound waveform 1,
2 Fourier components are analyzed, and based on this, both waveforms 1, 2
Find the spectral characteristics of. Next, the difference between the spectral characteristics of the waveforms 1 and 2 is obtained. Next, the spectral characteristic of the difference is quantized, and the filter coefficient is calculated based on this. The finally obtained filter coefficient is stored in the memory.

The filter coefficient for realizing the time variation of the filter characteristic is stored in the dynamic control parameter memory 26 (FIG. 2), and the filter coefficient for realizing the stationary filter characteristic which does not change with time is ADF 22 and 22 (FIG. 2). ) In the parameter memory.

The reason why the filter coefficient is obtained based on the spectral characteristic of the difference between the two waveforms is that the tone generator 18 (FIG. 2) uses a tone signal corresponding to one original musical tone waveform (for example, a waveform corresponding to a strong key touch). This is to generate a tone signal corresponding to the other original tone waveform (for example, a waveform corresponding to a weak touch) by performing filtering according to the difference spectral characteristic.
When performing filtering according to key touch, do not prepare filter coefficient sets corresponding to all the key touch strength stages, but prepare filter coefficient sets corresponding to several steps, The filter coefficient corresponding to the unprepared key touch strength may be obtained by the same interpolation as described above.

Of course, not only the filter coefficient corresponding to the key touch, but also the filter coefficient corresponding to the pitch (or range) or tone color or other various factors are prepared by the same method as described above.

(G) Filter Calculation Synchronized with Pitch The filter calculation timing for each sample point in the ADFs 21 and 22 (FIG. 2) is set by the pitch synchronization signals PS1 and PS2. This means that the unit time delay (z ^{−1 in} FIG. 5) in the filter calculation is set by the pitch synchronization signals PS1 and PS2.
That is, the sampling frequency fs in the filter calculation
Is set by the pitch synchronization signals PS1 and PS2.
Specifically, the pitch synchronization signal P corresponding to each note name G to F #
Since the frequencies of S1 and PS2 are the same as the effective sampling frequency fe shown in Table 1 above, ADF21 and 2
The sampling frequency fs of the filter operation in 2 is different as shown in the table according to the note name of the inputted tone signal. The sampling frequency fs in the filter calculation corresponds to ω = dπ in the frequency response characteristics shown in FIGS. 8 and 9. As is clear from this, when the sampling frequency fs changes according to the note name,
The frequency corresponding to ω = 2π in the frequency response characteristic also changes accordingly, and the obtained filter characteristic becomes a moving formant characteristic. Such a moving formant characteristic is very suitable for tone color control of a tone signal.

On the other hand, when the sampling frequency in the filter calculation is constant regardless of the pitch of the input signal, the obtained filter characteristic has a fixed formant.

(H) Pitch-Synchronous / Asynchronous Switching As described above, the moving formant filter is suitable for controlling the tone color of a musical tone, but a fixed formant filter may be preferable depending on the tone color or effect to be obtained. A fixed formant filter is also preferable when the pitch vent operator 13 (Fig. 2) is operated to greatly slide the pitch of the generated sound. for that reason,
The ADFs 21 and 22 of this embodiment are designed so that the filter calculation can be switched between pitch-synchronous and asynchronous. Also, such pitch synchronization /
Asynchronous switching is not uniform for all channels, and pitch synchronization or asynchronous designation can be performed independently for each channel.

Incidentally, the reason why the fixed formant filter is preferable during the pitch vent operation is as follows. The pitch control by the pitch vent operator 13 can be performed not only a slight pitch deviation control but also a large pitch slide control over several tones, and in that case, the octave of the note names G to F # shown in Table 1 above can be used. Pitch control may be applied across the boundary. At this time, if the filter calculation synchronized with the pitch is performed, the sampling frequency fs changes abruptly, and the cutoff frequency also changes abruptly (because it is a moving formant), resulting in an unnatural timbre change. For example, if the musical tone being produced is slid from the F # 5 note to the G5 note by the pitch vent operation, the sampling frequency changes rapidly from 47.359 kHz to 25.088 kHz (see Table 1 above).
The cut frequency also changes rapidly by the same amount as the difference. In order to prevent such an inconvenience, it is preferable to use a fixed formant (filter calculation that is not synchronized with the pitch) instead of a moving formant (filter calculation that is synchronized with the pitch) during the pitch vent operation. In the case of pitch-asynchronous filter calculation, the sampling frequency of the filter calculation in the ADFs 21 and 22 is 50 kHz in the example of FIG.

(I) Switching of Filter Order According to Dynamic / Static As described above, in the dynamic mode, dynamic control is performed from the dynamic parameter memory 26 (FIG. 2) under real-time control of the microcomputer 14 under the control of the microcomputer 14. It is necessary to read the parameter data for use and transfer it to the inside of the ADF 21, 22. Therefore, if the data transfer time is limited and the order of the filter coefficient is large, there is a possibility that the filter coefficient parameter data of all orders cannot be transferred within the limited time. Therefore, the filter order in the dynamic mode must be a limited order commensurate with the real-time data transfer time.

On the other hand, in the static mode, there is no need to change the filter coefficient during sounding, so there is no such problem.
In addition, the larger the filter order, the finer filter characteristics can be realized, which is preferable. Therefore, the filter order is set to be sufficiently large in the static mode.

For the above reason, in the specification of this embodiment, the filter order is switched according to the dynamic mode or the static mode. For example, the filter order in the static mode is the 32nd order (however, this is the case of the even order characteristic and the 31st order in the case of the odd order characteristic), and the filter order in the dynamic mode is half the 16th order ( In the case of odd-order characteristics, it is set as 15th order).

(J) Weighting Control of Filter Coefficient The binary digital data format of one filter coefficient is 1
It consists of a 2-bit filter coefficient data part and a 3-bit weighting data part. The 3-bit weighted data portion consists of 6 of 0, +1, +2, +3, +4, and +5 bits.
One of the above shift amounts is designated, and the filter coefficient data portion is shifted according to this shift amount.
The weighting is done. By performing weighting control capable of shifting the 12-bit filter coefficient data portion by 5 bits at the maximum, the dynamic range of the filter coefficient is substantially expanded to 17 bits. With such weighting control, while securing a sufficient dynamic range,
Since the number of bits of the filter coefficient stored in the memory is small, it is useful for saving the capacity of the filter coefficient memory.

<Overall Description of Adaptive Digital Filter> FIG. 11 is a block diagram schematically showing an internal configuration example of the adaptive digital filter device (ADF) 21 corresponding to the first to eighth channels, and the other ADF 22 is also the same as the whole section. Can be configured to.

The input interface 38 is the tone generator 18
It receives the pitch synchronization signal PS1 from (FIG. 2) and shapes the pitch synchronization signal PS1 of each channel into a state adapted to the operation timing inside the ADF 21,
A detailed example thereof is shown in FIG.

The timing signal generation circuit 39 generates a timing signal for controlling various operations inside the ADF 21, and various operations necessary for the filter operation based on the signal corresponding to the pitch synchronization signal of each channel given from the input interface 38. A timing signal is generated, a detailed example of which is shown in FIG. As will be described later, since the filter calculation for each channel is performed in a time-division manner, the timing signal generating circuit 39 gives a timing signal for controlling the filter calculation operation for each channel at an appropriate timing. .

The state memories 40 and 42 and the multiplier and accumulator units 41 and 43 are digital filter circuits that execute the filter operation of the FIR filter. The digital filter circuit including the state memory 40, the multiplier and the accumulator unit 41 (this is referred to as an A-series digital filter circuit) has first to fourth channels (Ch1 to Ch).
The digital filter circuit which performs the filter operation of 4) and comprises the state memory 42, the multiplier and the accumulator section 43 (this is referred to as a B-series digital filter circuit) is a filter operation of the fifth to eighth channels (Ch5 to Ch8). Is to do. In each of the digital filter circuits of the series A and B, the filter operation for four channels is time-divisionally performed. The reason why the filter operation of the first to eighth channels is divided into two series A and B and performed is because of the circuit design. The state memories 40 and 42 are digital tone signal sample value data TD given from the tone generator 18 (FIG. 2).
X is taken in in synchronization with the pitch synchronization signal PS1 and the pitch synchronization signal PS1 is acquired by the number of stages corresponding to a predetermined filter order.
Is delayed at a timing corresponding to, and corresponds to a set of unit delay elements z ⁻¹ in the FIR filter basic circuit of FIG. Multiplier and accumulator section 41, 43
Is for multiplying the digital tone signal sample value data delayed by the state memories 40 and 42 by the filter coefficient of the order corresponding to the delay order, and accumulating and summing the multiplication results of the respective orders. This corresponds to the multiplication element and the addition element in the FIR filter basic circuit in the figure. A-series state memory 40, multiplier and accumulator unit 4
A detailed example of No. 1 is shown in FIG. 14, and the B series can be configured in the same manner.

The microcomputer interface 44 is the microcomputer 1
Data and address bus 28 under control of 4 (FIG. 2).
It receives various kinds of data provided via the and supplies them to each circuit in the ADF 21. This interface 4
The types of data accepted via 4 are as follows.

Key code KC: Indicates a key assigned to each channel.

Key-on pulse KONP: A signal "1" is generated only once when a key assigned to each channel is pressed.

Touch code TCH: Indicates the strength of touch when the key assigned to each channel is pressed.

Tone code VN: Indicates the tone color (voice) selected for the key assigned to each channel.

The above-mentioned KC, KONP, TCH, and VN are output from the interface 44 in a state where each channel is time-division multiplexed according to a predetermined time-division timing, and a parameter processing unit (sometimes referred to as PPU) 4
Given to 5.

Pitch synchronous / asynchronous designation signal PASY: This ADF2
This is a signal for designating whether the digital filter operation in 1 is performed in pitch synchronization or asynchronously. This signal P
ASY can also be provided in a time-divisional manner for each channel, and pitch synchronization / asynchronous control of filter calculation can be independently performed for each channel. The signal PASY is generated according to the selected tone color, the operation content of the pitch vent operator 13 (FIG. 2), the operation state of the dedicated or appropriate operator, and the like.
8 to the interface 44. The pitch synchronization / asynchronization designation signal PASY output from the interface 44 is applied to the input interface 38 and is used to control whether or not the input interface 38 should generate a signal according to the pitch synchronization signal PS1. It

Dynamic filter parameter DPR: A filter parameter (filter coefficient) read from the dynamic control parameter memory 26 (FIG. 2) under the control of the microcomputer 14. As described above, the content of the filter parameter DPR for the dynamic mode changes with the passage of time during sound generation. The data format of the filter parameter DPR for the dynamic mode is also composed of a 12-bit filter coefficient data portion and a 3-bit weighting data portion, and further includes data for identifying even / odd order as described above. As described above, the set order of the dynamic mode filter parameter DPR is the 16th order (or the 15th order). Further, as is clear from the above, due to the symmetry of the filter coefficient in the linear phase characteristic, the set of the dynamic mode filter parameters DPR to be actually prepared need only be of the eighth order.

Dynamic / static selection signal DS: This signal is generated in response to the operation of the dynamic / static selection switch 27 (FIG. 2), and indicates whether the filter operation is performed in the dynamic mode or the static mode.

The DPR and DS are given to the parameter selector 46 from the interface 44.

The parameter memory 47 stores filter parameters (filter coefficients) for the static mode.

The parameter processing unit 45 functions to read out the filter parameters for the static mode from the parameter memory 47. That is, when the key-on pulse KONP is given, the address of the parameter memory 47 to be read out is calculated based on the contents of the tone color code VN, the touch code TCH, and the key code KC, and the filter parameter stored at this address is used as the memory 47. Read from. The read static mode filter parameter SPR is provided to the parameter selector 46. The data format of this static mode filter parameter SPR is the same as that of the above-mentioned DPR.
As described above, the set order of the static mode filter parameter SPR is the 32nd order (or the 31st order). Furthermore, as is clear from the above, the set of static mode filter parameters SPR actually prepared is 1 due to the symmetry of the filter coefficient in the linear phase characteristic.
Only the 6th order is required.

The parameter selector 46 has a filter parameter DPR for a dynamic mode or a static mode according to the content of the dynamic / static selection signal DS.
Select one of the SPRs. The selected parameters are input to the A-series and B-series parameter supply circuits 48 and 49. In the A-series parameter supply circuit 48, the first to fourth
The channel filter parameter DPR or SPR is accepted, stored, and supplied to the state memory 40 and the multiplier / accumulator unit 41 in synchronization with the filter calculation timing. The B-series parameter supply circuit 49 performs the same with respect to the filter parameters of the fifth to eighth channels.

The filter parameter SPR for static mode is
It is read from the parameter memory 47 only once when the key is pressed, and thereafter stored in the parameter supply circuits 48 and 49. Therefore, in the static mode, the filter coefficient does not change during the sound generation period and maintains a constant filter characteristic. On the other hand, the filter parameter DPR for the dynamic mode is stored in the parameter supply circuits 48 and 49 until a new content parameter is given via the microcomputer interface 44, and the stored content is changed every time the content of the parameter DPR changes with time. Is rewritten as

Of the filter parameters output from the parameter supply circuits 48 and 49, even-odd identification data EOA1 to EOA4 and EOB1 to EOB4 for identifying even and odd orders are given to the state memories 40 and 42, and the filter coefficient data unit CO
EA, COEB and weighting data section WEIA, WEI
B is given to the multiplier and accumulator units 41 and 43. In the reference numerals in the figure, A or B at the end indicates the distinction between the A series and the B series. Data EOA1 to EOA
4, EOB1 to EOB4 are provided in parallel for each channel, but data COEA, COEB, WEI
A and WEIB are given for each channel in a time division manner.

A detailed example of the parameter processing unit 45, the parameter selector 46, the parameter memory 47, and the parameter supply circuits 48 and 49 is shown in FIG.

The pitch synchronization output circuit 50 is a circuit that inputs the filtered musical tone signal sample value data of each channel output from the multiplier and accumulator units 41 and 43, and resamples them at the timing synchronized with each pitch. . The signal used for sampling control here is given from the input interface 38. Pitch sync signal PS
1D, which is the pitch synchronization signal PS of each channel
1 is delayed by a predetermined time. Delayed pitch synchronization signal PS1 for pitch-synchronized resampling
The reason for using D is to match the time delay of the tone signal of each channel in the digital filter calculation in the preceding stage. In this way, the process of re-sampling the output signal of the digital filter in synchronization with its pitch adjusts the sampling frequency to the musical tone pitch, thus solving the problem of aliasing noise. When performing digital filter calculation in synchronization with the pitch, since the digital filter output signal has a sampling period in synchronization with the pitch, pitch synchronization can be realized even if the pitch synchronization output circuit 50 is not provided. When the digital filter operation is performed asynchronously with the above, the pitch synchronization output circuit 50 is required to realize the pitch synchronization. A detailed example of the pitch synchronization output circuit 50 is shown in FIG.

Next, a detailed example of each part of the adaptive digital filter device 21 will be described.

It should be noted that in each figure, a circuit in which a number such as "1D" or "8D" and a letter D are included in a block is a delay circuit or a shift register, and the preceding number indicates the number of delay stages or the number of stages. Further, in this delay circuit or shift register block, if the delay control clock pulse or the shift control clock pulse is not shown as input, the delay or shift is controlled by the master clock pulse φ (see FIG. 3). It

<Input Interface 38: FIG. 12> In FIG. 12, the pitch synchronizing signal PS1 is the OR circuit 5
It is input to the shift register 53 via 1, 52. As shown in FIG. 3, the pitch synchronization signal PS1 is time-division multiplexed for eight channels with eight time slots as one cycle. The signal "1" occurs in the corresponding one time slot. Shift register 53
Is returned to the input side via the AND circuit 54 and the OR circuit 52, and the pitch synchronization signal PS1 for 8 channels is 8
It is circulated and held in the stage shift register 53. Eight latch circuits 55 corresponding to the respective channels are provided in parallel, and the pitch synchronization signal output from the shift register 53 is input in parallel to the data input D thereof. The latch control input L of each latch circuit 55 has a latch timing signal φFS1 (25) corresponding to each channel,
.phi.FS2 (29), ... .phi.FS8 (56) are respectively input and removed. The number next to φFS indicates the channel number, and the number in parentheses next to it indicates the time slot number in one operation cycle (64 time slots shown in FIG. 3) and corresponds to that time slot number. In the time slot, the latch timing signal becomes the signal "1". For example, the signal φFS1 (25) is the time slot 2
At 5, the signal becomes "1", which corresponds to the first channel. As apparent from FIG. 3, the time slot 25 corresponds to the time division timing of the first channel in the pitch synchronization signal PS1. Therefore, in the portion of the latch circuit 55 which is latch-controlled by this signal φFS1 (25), the pitch synchronization signal PS of channel 1 is provided.
The content of 1 (a signal "1" at the timing synchronized with the pitch, and a signal "0" at the other timings) is latched. The same applies to the other channels 2 to 8, and the pitch synchronization signal of each channel is latched in parallel in the latch circuit 55 at a predetermined timing.

The latch timing signal φ corresponding to each channel
FS1 (25) to φFS8 (56) are generated from the decoder 56 shown in FIG. The decoder 56 is a counter 57
And decode the output of to generate various types of timing signals. The counter 57 is a modulo 64 counter that counts the master clock pulse φ, and is periodically reset by the system synchronization pulse SYNC (FIG. 3). It will be apparent from the display of FIG. 13 in which time slot the latch timing signals φFS1 (25) to φFS8 (56) corresponding to the respective channels 1 to 8 occur.

Returning to FIG. 12, each timing signal φFS1 (25) to φ
FS8 (56) is multiplexed and inverted by NOR circuit 58. The output of the NOR circuit 58 is input to the AND circuit 54. As a result, the storage of the shift register 53 regarding the channel taken into the latch circuit 55 is cleared.

On the other hand, the signal "1" latched by the latch circuit 55 corresponding to the channel for which the pitch synchronization signal PS1 becomes "1"
Is held until the corresponding latch timing signals φFS1 (25) to φFS8 (56) are generated in the next cycle. In this way, the latch circuit 55 holds the signal "1" for the time corresponding to 64 time slots corresponding to the channel in which the pitch synchronization signal PS1 becomes "1". The output of the latch circuit 55 corresponding to each channel is given to the timing signal generating circuit 39 of FIG. 13 as filter operation request signals φF1 to φF8. As will be described later, when the filter calculation request signals φF1 to φF8 become “1”, the filter calculation for one sample point is executed. Since the filter calculation request signals φF1 to φF8 become “1” only when the pitch synchronization signal PS1 is generated, the digital filter calculation synchronized with the pitch of the tone signal to be filtered is eventually performed.

For example, as shown in FIG. 17, if the pitch synchronization signal PS1 becomes "1" at time slot 9 (in this case, the signal "1" is the channel 1 pitch synchronization signal), this is the shift register. It is circulated and held at 53, and the timing signal φFS1 (2
When 5) occurs, it is latched by the latch circuit 55, and the filter operation request signal φF1 corresponding to channel 1 rises to "1" in the time slot 25. This signal φF1 has a total of 6 until the time slot 24 of the next cycle.
The signal "1" is maintained for the time width of four time slots.

<Timing Signal Generation Circuit 39: FIG. 13> In FIG. 13, the timing signal generation circuit 39 is a filter calculation request for each channel provided from the input interface 38 of FIG. 12 in addition to the decoder 56 and the counter 57 described above. The operation timing generation circuits 391 to 398 for generating the timing signals for controlling the filter operation operation according to the signals .phi.F1 to .phi.F8 are connected to the respective channels (Ch1 to Ch1.
It is provided for each Ch8). In the figure, channel 3 circuit 3
Although only 91 is shown in detail, the circuits 392 to 398 of the other channels 2 to 8 have the same configuration, and only the time relationship of the timing signals T (33), T (49), ... The timing signals T (33), T (49), ... Are generated from the decoder 56. Similarly to the above, the number in parentheses in the code indicating the timing signal indicates the time slot number in one operation cycle (64 time slots shown in FIG. 3), and the timing in the time slot corresponding to the time slot number. It indicates that the signal becomes "1". The same applies to other timing signals generated from the decoder 56, and by referring to the numbers in parentheses, it is easy to know in which time slot the timing signal is generated (whether it becomes "1").
For example, the timing signal T (33) is a signal "1" in the time slot 33 as shown in FIG. 17, and the signal T (3-18) is a signal "1" between the time slots 3 and 18. It is something that becomes.

Explaining the operation timing signal generation circuit 391 of channel 1, the filter operation request signal φF1 and the timing signal T (33) are given to the AND circuit 59. Therefore, if it is required to perform the filter operation, the AND circuit 59 is operated at the timing of the time slot 33.
Output becomes "1". The output signal of the AND circuit 59 and the signal obtained by delaying this signal by one time slot in the delay circuit 60 are given to the OR circuit 61. This OR circuit 6
The output of 1 is the filter data sampling clock signal R
It is used as LA1 to control the unit delay in the digital filter circuit. This signal RLA1 is the first
As shown in FIG. 7, it becomes "1" in the time slots 33 and 34.

The AND circuit 62 is provided with an output of the AND circuit 59 and a signal obtained by inverting the even / odd identification data EOA1 of channel 1 (this is output from the parameter supply circuit 48 of FIG. 11) by the inverter 63. This data EO
A1 is a signal "1" when the order of the filter characteristics to be realized is an even order and a signal "0" when the order is an odd order. The output of the AND circuit 62 is delayed by 2 time slots in the delay circuit 64 and output as the inhibit signal INHA1. When the filter order is odd, the output signal of the AND circuit 62 becomes "1" in the time slot 33, and
Signal IN at time slot 35 after the time slot
HA1 becomes “1” (see FIG. 17). If the filter order is even, the signal INHA1 is always "0". The in-bit signal INHA1 is used to realize an odd-order filter characteristic by prohibiting an even-order highest order (32nd-order) operation in the operation of the digital filter circuit.

The timing signals T (3-18) and T (35-50) are input to the OR circuit 65, and the output thereof and the output of the AND circuit 59 are input to the OR circuit 66. The output of the OR circuit 66 is delayed by one time slot by the delay circuit 67 and output as the first shift clock signal φFFA1 (see FIG. 17). Further, a signal obtained by inverting the output of the OR circuit 66 and the output of the delay circuit 64 by the inverter 68 is added to the AND circuit 69, and the signal obtained by delaying the output by one time slot by the delay circuit 70 is the second shift clock signal φFLA1.
Is output (see FIG. 17). Signal φFLA1
Is "1" at time slot 36 if the filter order is even, but "0" if it is odd. These shift clock signals .phi.FFA1 and .phi.FLA1 are musical tone signal sample value data corresponding to each delay stage in the state memory 40 (FIG. 11) for time-divisionally performing arithmetic operation for each order in the digital filter circuit. Used to sequentially shift the.

The multiplication timing signal PDOA1 (see FIG. 17), which becomes "1" between the time slots 35 and 50 in accordance with the timing signal T (35-50), is multiplied by the tone signal sample value data and the filter coefficient in the digital filter circuit. It indicates the period for which

Timing signals T (49), T (19-34), T used in the operation timing signal generation circuits 392-394 corresponding to the other channels 2-4 in the A-sequence.
(51-2), ... Are timing signals T of channel 1
It is shifted by 16 time slots in order from the timing of (33), T (3-18), T (35-50). Therefore, signals RLA2 to PLA1 similar to the signals RLA1 to PDOA1 output from the circuit 391 of channel 1 are used.
DOA2, ... RLA4 to PDOA4 are other channel 2
Are generated from the circuits 392 to 394 of FIG. 4 through timings sequentially shifted by 16 time slots. Based on this, in the A-series digital filter circuit (in particular, the multiplier and accumulator unit 41), one operation cycle = 6
The filter calculation operation of the four channels 1 to 4 can be performed in a time division manner in the time interval of every 16 time slots among the 4 time slots.

Also in the operation timing signal generation circuits 395 to 398 corresponding to the channels 5 to 8 of the B series, the timing signals T (49), T (19-34), and T (19-34), T at the predetermined timings shifted by 16 time slots between the channels. (51
-2), ... Are used, and various signals RLB1 similar to those described above are used.
~ PDOB1, ... RLB4 ~ PDOB4 are generated.

Operation timing signal generation circuits 391 to 391 corresponding to the A series
The signals RLA1 to PDOA4 generated in 394 are applied to the state memory 40 of the A series, and the signals RLB1 to PDO generated in circuits 395 to 398 corresponding to the B series.
OB4 is provided to the B-series state memory 42 (FIG. 11).

<State Memory 40: FIG. 14> In FIG. 14, an A-series state memory 40 is a state memory 40 corresponding to each channel 1 to 4 of the A-series.
1 to 404 are provided in parallel. Although only the state memory 401 of the channel 1 is shown in detail, the state memories 402 to 404 of the other channels 2 to 4 have the same configuration and the signals input thereto are different. Each signal RL generated from the operation timing signal generation circuits 391 to 394 (FIG. 13) corresponding to each of the above channels 1 to 4
A1 to PDOA1, ... RLA4 to PDOA4 are input to the state memories 401 to 404 corresponding to their own channels, respectively.

Before describing the details of the state memory 40 and the multiplier / accumulator unit 41 shown in FIG.
This will be described with reference to the drawings and the schematic diagram shown in FIG.

<Basic operation of even-order filter calculation: FIG. 18> FIG.
9A and 9B are schematic diagrams for explaining the basic operation of the IR type filter operation, in which (a) is a block diagram, (b) is each stage Q0 to Q15, Q16 to Q31 of the shift registers SR1 and SR2 of (a) at each operation timing. The following shows the state of the tone signal sample value in.

The first shift register SR1 has 16 stages, and digital tone signal sample value data X _n to be filtered is input via the selector SEL1. As the signal for fetching the new sample value data x _n via the selector SEL1, the above-mentioned filter data sampling clock signal RLA (in the case of channel 1, RLA is used).
1) is used, and the first shift clock signal φFF is used as the shift clock pulse of the shift register SR1.
A (φFFA1 for channel 1) is used.
Each stage Q0 to Q15 of the first shift register SR1
16 sampled data x _n ~x ^n-15 to n-15 are retained from Samburu point n in. The output of the final stage of the shift register SR1 is returned to the first stage via the selector SEL1 when the sampling clock signal RLA is not present. This shift register SR1 is shifted only to the right.

The second shift register SR2 also has 16 stages, and the output of the first shift register SR1 is input via the selector SEL2. The filter data sampling clock signal RLA described above is used as a signal for fetching the output of SR1 into SR2 via the selector SEL2,
As the shift clock pulse of the SR2, the above-mentioned second shift clock signal φFLA (φF in the case of channel 1 is used).
LA1) is used. This second shift register SR
2 from each stage Q16-Q31 sample points n to n
16 sample value data x from -16 to n-31
^{n-16 to} xn ^-31 are retained. The final stage Q31 of the shift register SR2 is the first stage Q16 when there is no sambling clock signal RLA via the selector SEL2.
Connected to. The shift register SR2 is a bidirectional shift type, and the sampling clock signal RLA is "1".
When it is, the right shift mode is set, and when it is "0", the left shift mode is set.

Stages Q15 and Q1 of shift registers SR1 and SR2
The outputs of 6 are added by the adder ADD, the addition result is given to the multiplier MUL, and is multiplied by the filter coefficient COEA. The multiplication result is given to the accumulator ACC, where the multiplication result for all orders is accumulated. Thus, the accumulator ACC outputs the filter calculation result for one sample point.

The adder ADD adds sample value data for two sample points, and the common filter coefficient COEA is added to the multiplier MU.
The reason for multiplying by L is the above-mentioned “symmetry of filter coefficient”.
by. That is, since two sample value data which are in a symmetric relationship are multiplied by the filter coefficient of the same value, they are not multiplied separately but are added and then multiplied by one time to multiply the sample value data by coefficient. I try to do it at the same time.

In FIG. 18B, the operation timing of the vertical axis advances every time slot corresponding to the master clock. The numbers shown there indicate the order for convenience and do not absolutely indicate the time slot number in one operation cycle (64 time slots). In the example of the figure, at the operation timing 1, sample values data of 32 sample points from _xn to _xn-31 are stored in the respective stages Q0 to Q31 of the shift registers SR1 and SR2.

In the illustrated example, the sampling clock signal RLA is set to "1" at the operation timing 2. As a result, the shift registers SR1 and SR2 are shifted to the right by one stage in accordance with the shift clock signals .phi.FFA and .phi.FLA, and at the operation timing 2, the state shown in the drawing is obtained. Shift clock signals φFFA and φFLA at this time
For channel 1, φFFA1 and φFL in Fig. 17
This occurs in the time slot 34 as shown in the column A1. As is clear from the figure, the shift clock signals .phi.FFA and .phi.FLA are not generated in the next one time slot, and therefore the states of the stages Q0 to Q31 do not change at the operation timing 3 in FIG. 18 (b). However, the 16 time slot width from calculation timing 3 to 18 is
Speaking of channel 1, multiplication timing signal PDOA1
It corresponds to the time slots 35 to 50 generated by (FIG. 17), during which multiplication and accumulation are performed.

That is, at multiplication timing 3, stages Q15 and Q1
The sample value data of x _n-14 and x _n-15 in 6 are added by the adder ADD, which is multiplied by the 16th order filter coefficient, and the result is held in the accumulator ACC.

During the operation timings 4 to 18, the first shift register SR1 is shifted to the right and the second shift register SR2 is shifted to the left for each time slot, and each stage Q0 is shifted.
The state of Q31 changes sequentially as shown. Therefore,
At operation timing 4, x _n-13 and x _n-16 are added, this is multiplied by the 15th order filter coefficient, and the result is accumulated in the accumulator ACC. Next calculation timing 5
Then, the same calculation is performed for x _n-12 and x _n-17 . In this way, the same filter coefficient calculation is sequentially performed in time division for the two sample value data at the symmetrical position. Similar operations are performed for certain x _{n + 1} and x _n-30 , which completes the full-order filter operation. At the next operation timing 19, the shift is performed again, and as shown in the figure, the sample value data x _{n + 1 to} x _n-30 are arranged in time order delayed by the stages Q0 to Q31.

<Odd-Order Filter Operation Basic Operation: FIG. 19> FIG. 19 is a schematic diagram for explaining the basic operation of the FIR-type filter operation when realizing filter characteristics of odd-order (31st order). (a) is a block diagram, (b) is the shift register SR of (a) at each operation timing.
1, SR2 stages Q0 to Q15, Q16 to Q30
7 shows the state of the tone signal sample value of.

Each block in (a) is the same as that shown in FIG. 18 (a), and the difference is that the output of the stage Q16 is given to the adder ADD via the gate GT. The gate GT is controlled by a signal obtained by inverting the inhibit signal INHA (INHA1 in the first channel). When the signal INHA is "1", the output signal of the stage Q16 is supplied to the adder ADD. Ban. In addition, the 16th stage 31 of the second shift register SR2 is not used, and the 15th stage Q30
And the first stage Q16 are connected via the selector SEL2.

In (b), the state change of the first shift register SR1 is the same as in FIG. 18 (b). Second shift register S
The state change of R2 is slightly different from that of FIG. 18 (in the case of even orders). The shift clock signal φFLA of the second shift register SR2 was “1” in the even-numbered mode at the operation timing 4 but becomes “0” in the odd-numbered mode (in the case of the channel 1, φFLA1 of FIG. 17). See time slot 36 in the column). Therefore, in odd mode, the first
As shown in FIG. 9B, the second shift register SR2
The contents of are not shifted at the calculation timing 4, but are sequentially shifted to the left between the calculation timings 5 and 19.

At calculation timing 3, the shift registers SR1 and SR2
In each of the stages Q0 to Q30, the tone signal sample values x _{n + 1 to} x _n-29 corresponding to the 31st delay stages are sequentially entered, and the central order sample value x x is input to the stage Q15.
_It contains _n-14 . As shown in FIG. 6, in the centrally located order of the symmetry of the odd-order mode, a unique filter coefficient is assigned corresponding to each order. Therefore,
At operation timing 3, the output of the stage Q16 is prohibited by the inhibit signal INHA, and only the output signal of the stage Q15 corresponding to the central order is added to the adder ADD.
The multiplier MUL multiplies the unique filter coefficient corresponding to the central order.

At the operation timing 4, only the first shift register SR1 is right-shifted and the second shift register SR2 is not shifted. Therefore, the stage Q15 contains x _n-13 and the stage Q16 contains x _n-15 . Further, the inhibit signal INHA becomes "0", and the gate GT is opened. In this way, the sample values x _n-13 and x _n-15 corresponding to the orders on both sides of the central order are given to the adder ADD and added, and the multiplier MUL multiplies both by the common filter coefficient.

At calculation timings 5 to 18, SR1 is sequentially shifted to the right, S
R2 is sequentially shifted to the left, sample values at symmetrical positions as shown in the figure enter stages Q15 and Q16, and both are added and multiplied by a common filter coefficient.

<Digital Filter Circuit: FIG. 14> The state memory 401 corresponding to the channel 1 will be described with reference to FIG. The 16-stage one-way shift register 71 corresponds to the first shift register SR1 shown in FIGS. 18 and 19, and is shift-controlled by the first shift clock signal φFFA1 corresponding to the channel 1. Tone generator 18 (Fig. 2)
Digital tone signal sample value data T supplied from
DX is input to the latch circuit 73, and the sample value data of channel 1 is taken into the latch circuit 73 according to the latch timing signal XLDA1. Latch timing signals XLDA1 to XLDA4, X corresponding to the channels 1 to 8 corresponding to the time division timing (see FIG. 3) of the channels in the tone signal sample value data TDX.
LDB1 to XLDB4 are generated from decoder 56 (FIG. 13). As mentioned above, the number in parentheses at the end of each signal representation in FIG. 13 indicates the time slot number in which that signal occurs. A latch circuit similar to the latch circuit 73 is provided in the state memory corresponding to each channel, and the latch timing signal XLDA1 corresponding to each is provided.
The tone signal sample value data TDX of each channel 1 to 8 is separately latched by .about.

The tone signal sample value data of channel 1 latched by the latch circuit 73 is given to the A input of the selector 74. The selector 74 selects the A input when the filter data sampling clock signal RLA1 given from the operation timing signal generating circuit 391 of FIG. 13 is "1",
In other cases, the output signal of the 16th stage of the shift register 71 applied to the B input is selected. As described above, this signal RLA1 is synchronized with the pitch of the musical sound,
The selector 74 selects new sample value data (A input) in synchronism with the pitch, and supplies this to the shift register 71. As apparent from FIG. 17, since the shift clock signal φFFA1 becomes “1” in the time slot 34 where the signal RLA1 becomes “1”, the shift register 71
Takes in the new sample value data given from the selector 74 to the first stage (Q0). As described above, the shift operation is temporarily stopped in the next time slot 35 and the right shift is sequentially performed in the subsequent time slots 36 to 51.

The bidirectional shift register 72 is the second one shown in FIGS.
Of the shift register SR2. Each stage Q16 to Q31 of the bidirectional shift register 72 has selectors SL1 to SL16 and a latch circuit L as shown.
It is composed of C1 to LC16, and is connected so that bidirectional shift is possible. That is, the first stage Q1
The output signal of the final stage (Q15) of the first shift register 71 is input to the A input of the selector SL1 of No. 6,
Selectors SL2 to SL of other stages Q17 to Q31
16 A inputs each have a latch circuit LC1 of the previous stage.
~ LC15 output is input. The outputs of the latch circuits LC2 to LC16, LC1 of the next stage are input to the B inputs of the selectors SL1 to SL16 of the respective stages.
As a result, when the A input of each of the selectors SL1 to SL16 is selected, the right shift mode is set, and when the B input is selected, the left shift mode is set. Each selector SL1 to SL
Sampling clock signal RLA as 16 selection signals
1 is used. When this is "1", the A input is selected, that is, the right shift mode is set. However, in order to invalidate the stage Q31 in the odd mode, the selector SL15 of the stage Q30 is somewhat different from the others. That is, the selector SL15 is provided with the C input, and the output signal of the stage Q16 is added thereto. When the even / odd identification data EOA1 for channel 1 is "1" (that is, even mode), the AND circuit 751 is enabled, and the signal R
When LA1 is "0", the output of the AND circuit 751 becomes a signal "1", whereby the selector SL15 selects the B input, and the output of the stage Q31 is given to the stage Q30 (shifted to the left). When the EOA1 is "0" (in the odd mode), the AND circuit 761 is enabled, and when the signal RLA1 is "0", the selector SL15 is C.
Select input and output of stage Q16 is Q30
Is given to (shifted left after skipping Q31).

With the above configuration, the first and second shift registers 7
The change state of the contents of 1, 72 is exactly the same as that shown in FIGS. 18 (b) and 19 (b) depending on whether the mode is even or odd.

The output signal of the first stage Q16 of the second shift register 72 is given to the gate 76 via the gate 75. The gate 75 is controlled by a signal obtained by inverting the inhibit signal INHA1, and corresponds to the gate GT in FIG. The gate 76 inputs the output signal of the first shift register 71 (the output signal of the stage Q15) and the output signal of the second shift register 72 (the output signal of the stage Q16) given through the gate 75, and the multiplication timing It is released by the signal PDOA1 (see FIG. 17).

The output of the gate 76 is given to the multiplier and adder 77 of the accumulating section 41, where the two tone signal sample value data are added. This adder 77 corresponds to the adder ADD shown in FIGS. Adder 7
The output of 7 is delayed by one time slot in the delay circuit 78 and input to the multiplier 79. The multiplier 79 multiplies the tone signal sample value data supplied via the delay circuit 78 by the filter coefficient data COEA supplied via the delay circuit 80. The output of the multiplier 79 is the delay circuit 81.
Are delayed by 4 time slots and provided to the shifter 82. The shift control input of the shifter 82 is supplied with weighting data WEIA via a delay circuit 83 that sets a delay of 5 time slots. This multiplier 79 and shifter 82
Corresponds to the multiplier MUL shown in FIGS. 18 and 19. That is, as described above, the filter coefficient data C
OEA is the data of the effective bit of the filter coefficient, and the multiplier 79 multiplies the effective bit of the filter coefficient by the tone signal sample value data. Then, the multiplication result is weighted data WEI in the shifter 82.
By shifting by the number of bits according to the value of A, the multiplication of the real number of filter coefficients and the tone signal sample value data is completed.

The output of the shifter 82 is given to the accumulator 84 and
The multiplication result corresponding to each order of the channels is accumulated. The output of the accumulator 84 is the latch circuit 8
5 and is latched according to the operation end timing signal FENDA. This signal FENDA is generated from the decoder 56 shown in FIG. As shown in the figure, this signal FENDA indicates that the time slots 8, 24,
It becomes "1" at 40 and 56. Time slot 56
In 1, the operation result of channel 1 is latched, in 8 the operation result of channel 2 is latched, in 24, the operation result of channel 3 is latched, and in 40, the operation result of channel 4 is latched. From the decoder 56, a B series operation end timing signal FENDB is similarly generated.

The multiplier and accumulator 41 is time-shared by the four channels. That is, the adder 77 has the gate 76 of the channel 1 state memory 401.
Output, and output signals of gates having similar functions provided in the state memories 402 to 404 of channels 2 to 4 are input in a multiplexed manner. The output gate 76 of each of the state memories 401 to 404 has a multiplication timing signal PDOA1 to PDOA4 of 16 time slot width.
Are input at different timings which are shifted by 16 time slots. Therefore, the adder 77 has each channel 1
4 signals are input in time-division multiplex every 16 time slots. In the filter coefficient data COEA and the weighting data WEIA, four channels are time-division-multiplexed at every 16 time slots at the same timing as described above. Data is time-division multiplexed.

The B-series state memory 42 and the multiplier / accumulator unit 43 also have the same configuration as in FIG. 14, but the timings of various signals are appropriately different.

The timing of the filter operation for each channel 1 to 8 in the A-series and B-series digital filter circuits (that is, the state memories 40 and 42 and the multiplier and accumulator sections 41 and 43) as shown in FIG. It is shown in FIG. In FIG. 20, the shift timing of the first shift register (71 in the case of channel 1) is shown in the shift 1 column, and the shift timing of the second shift register (72 in the case of channel 1) is shown in the shift 2 column. The shift timing is shown. The direction of the arrow indicates the shift direction (right shift or left shift). The shift timing of each channel is calculated by the operation timing signal generation circuits 391 to 39.
8 (FIG. 13) to generate first and second shift clock signals φFFA1 to φFFB4 and φFLA1 to φF.
It corresponds to the generation timing of FB4. The shift operation includes a shift operation for filter calculation and a dummy shift operation for refreshing stored data. For example, in the case of channel 1, the shifts in time slots 4 to 19 are dummy shifts. The signal (←) in the column of shift 2 indicates that the left shift is performed in the even-order mode and the shift is not performed in the odd-order mode.

In FIG. 20, the INH column indicates the inhibit signal IN.
The generation timing of HA1 to INHB4 is shown. In the odd-order mode, the inhibit signals INHA1 to INHB4 become "1" in the time slot marked with a circle.
The column of PDO is the state memory 40, 4 of each channel.
2 shows the timing at which the tone signal sample value data is input to the multiplier and accumulator units 41 and 43 from No. 2. This is the multiplication timing signal PDOA of each channel.
It corresponds to the generation timing of 1 to PDOB4. SU
The column of M shows the output timing of the accumulator 84. There is a delay of 6 time slots between the PDO and SUM timings due to delay circuits 78 and 81.
Due to the time slot delay and the one time slot delay due to the accumulation 84. In the last time slot of the output timing of the accumulator 84, the operation end timing signal FENDA is generated, and the output of the accumulator 84 is taken into the latch circuit 85.

<Parameter Memory 47: FIG. 21> FIG. 21 shows an example of a storage format of the parameter memory 47, which includes a key group table, a touch group table, a parameter address table, and a parameter bank. Actual filter parameters are stored in the parameter bank, and address data of parameters to be read from the parameter bank are stored in the parameter address table. The key group table stores information for grouping the keys corresponding to each key. As an example, the number of keys is 88 and the number of groups is 44. In the key group table, relative address data (referred to as a key group address) regarding a key group to which the key belongs is stored at an address position corresponding to each key. Therefore, the key group table is addressed by the key code KC. This key group table occupies a storage area starting from a predetermined absolute address (referred to as an offset address OADS) of the parameter memory 47.

The touch group table stores information for grouping the touch intensities corresponding to each step of the key touch intensity for each tone color. As an example, the number of timbres is 32, and this touch group table includes 32 timbre-specific areas corresponding to the values 0 to 31 of the timbre code VN, and the touch strength level that can be represented by the touch code TCH is an example. 64, and each tone color area is touched from 0 to 6
It has 64 address positions corresponding to 3. Relative address data (referred to as a touch group address) regarding a touch group to which the touch strength belongs is stored at an address position corresponding to each touch strength. As an example, the number of touch groups is 16. Therefore, the tone color code VN and the touch code TC are displayed in the touch group table.
Addressed by H. The touch group table occupies a storage area of the parameter memory 47 starting from a predetermined absolute address (this is called an offset address OAD1). Absolute address data for reading this touch group table is created by combining 11-bit relative address data (address with offset address OAD1 being 0) by combining 5-bit tone color code VN with 6-bit touch code TCH. , And is added to the offset address OAD1.

Parameter address table, for each key group,
In addition, relative address data (referred to as parameter address) of the address storing the filter parameter corresponding to each touch group is stored for each tone color. This parameter address table is for each key group 0-4.
It contains 44 key group areas corresponding to 3, which are addressed by the key group address read from the key group table described above. Each key group area includes 32 timbre-specific areas corresponding to timbres 0 to 31, and each timbre-specific area is addressed by a timbre code VN.
Each tone color area corresponds to touch groups 0-15 1
It has 6 address locations, each address location being addressed by a touch group address read from the touch group table described above. A storage position for 2 bytes is assigned to one address position, and the parameter address data is stored therein in 12 bits. This parameter address table occupies a storage area of the parameter memory 47 starting from a predetermined absolute address (this is called an offset address OAD2). For the absolute address data for reading this parameter address table, the least significant 1 bit is set to "0" or "1" (this means that 1 address position is 2
Bytes, that is, 2 absolute addresses), 4 bits of touch group address data are placed in the upper portion, 5 bits of tone color code VN are placed in the upper portion, and 6 bits of key group code are placed in the upper portion. Then, a total of 16 bits of relative address data (address whose offset address OAD2 is 0) is created,
It is created by adding this to the offset address OAD2.

The parameter bank stores 2620 types of filter parameters as an example, and includes 2620 parameter storage areas corresponding to parameter addresses 0 to 2619. One parameter storage area includes a storage position of 32 bytes (32 absolute address positions), and stores parameters corresponding to one set of filter coefficients for 16 orders. The filter coefficient for the first order is stored in the storage position of 2 bytes, and the details thereof are, as described above, 12-bit filter coefficient data (COE), 3-bit weighting data (WEI), and 1-bit even / odd. It consists of identification data (EO). However, weighting data (WE
Since I) and the even / odd identification data (EO) are common between the orders in one set of parameters, they are stored only in the storage positions of the first order and are not stored in the storage positions of other orders. However, it is also possible to store the weighting data (WEI) independently for each degree. This parameter bank is addressed by the parameter address read from the parameter address table described above. The parameter bank occupies a storage area of the parameter memory 47 starting from a predetermined absolute address (this is called an offset address OAD3). The absolute address data for reading this parameter bank is created by locating the 12-bit parameter address data in the upper 12 bits of the 17-bit relative address data (address where offset address OAD3 is 0). The offset address OA
It is created by adding to D3. By sequentially changing the lower 5 bits of this absolute address data in 32 steps, one set of filter parameters consisting of 16 orders in one parameter storage area designated by the parameter address is sequentially read.

The hierarchical parameter memory structure as shown in FIG. 21 is advantageous because it can save memory capacity. Without doing this, all combinations of 44 key groups, 32 tones, 16 touch groups (22528
If the filter parameters are individually stored in accordance with the above), a storage capacity of 22528 × 32 bytes is required. However, as shown in FIG. 21, 1408 (= 44 × 32) × 32 of the parameter address table. 402, which is a combination of bytes and 2620 x 32 bytes in the parameter bank
Only a storage capacity of 8x32 bytes is required. That is,
Even if the combinations of key groups, timbres, and touch groups are different, it is possible to use the same filter parameters, so in the example of FIG. 21, there is a structure that shares 2620 types of parameters for 22528 combinations. In this way, the memory capacity is saved.

<Parameter Processing Unit 45, Parameter Selector 46, Parameter Memory 47, Parameter Supply Circuits 48, 49: FIG. 15> The parameter processing unit 45 controls the reading of the parameter memory 47 as described above for the static mode. To do. The program memory 451 stores a program for executing the read control of the parameter memory 47 as described above.
The program counter 452 generates a program step signal PC for reading the program memory 451, and includes an 8-stage shift register 86 and an adder 8
7, gates 88 and 89, and an end detection circuit 90 are included, and count operation for eight channels is performed in a time division manner.
The key-on pulse KONP is inverted by the inverter 91,
It joins the control input of gate 88. This key-on pulse K
The ONP becomes a signal "1" when the key is pressed, and the signals corresponding to the respective channels are time-division multiplexed.
The adder 87 adds “1” given from the gate 89 to the output of the shift register 86, and the addition result is given to the shift register 86 via the gate 88. The end detection circuit 90 detects whether or not the value of the output of the shift register 86 has reached the final step of the program. When the final step is not reached, the signal "0" is output.
Is output and the signal “1” is given to the control input of the gate 89 via the inverter 92 so that the signal “1” for instructing 1 count up is given to the adder 87, but when the final step is reached. Outputs a signal "1", supplies a signal "0" to the gate 89 through the inverter 92, closes the gate 89, and stops counting.

With the above configuration, the content of the program counter 452, that is, the step signal PC is reset to "0" when the key-on pulse KONP is generated, and is incremented by 1 each time the shift register 86 makes one cycle (every 8 time slots). The count is stopped when the final step is reached. As an example, the number of program steps is 3
7, and the step signal PC output from the counter 452 sequentially changes from "0" to "36" (final step). The step signal PC is the output of the shift register 86, and eight channels are time-division multiplexed.

The program memory 451 receives the input step signal PC
Selection control signals SELC1 to SELC depending on the step of
4 and read the address data for reading the offset address memory 453. The offset address memory 453 has the above-mentioned offset address OA.
The values of DS to OAD3 are stored. The offset address data ADOF (any one of OADS to OAD3) read from the offset address memory 453 is input to the adder 454. The adder 454 is the selector 455.
Relative address data RADD and offset address data ADOF are added, and the output is added to the address input of the parameter memory 47 as the address data PRAD.

The key group address register 456, the touch group address register 457, and the parameter address register 458 each include an 8-stage shift register, and each of the key group address data KEYG, the touch group address data TCHG, and the parameter address data PA.
D is stored for each channel in a time division manner.
Selectors 93 to 9 are provided on the input side of the registers 456 to 458, respectively.
5 is provided, and the data read from the parameter memory 47 is added to one input of each selector. The other input of each selector 93-95 has each register 456-
The output of 458 is added. The selection control signals SELC2 to SELC4 from the selectors 93 to 95 are stored in the program memory 451.
The control of whether the read output data of the parameter memory 47 is loaded into the registers 456 to 458 or the data once loaded into the registers 456 to 458 is cyclically held according to the step of the program. To do. As is apparent, when the above-mentioned key group address data is read from the parameter memory 47, it is stored in the key group address register 45.
6, a selection control signal for loading the touch group address data into the touch group address register 457 when the touch group address data is read, and loading into the parameter address register 458 when the above parameter address data is read. SELC2-SE
LC4 is generated.

The address data KEYG, TCHG, and PAD stored in the registers 456 to 458 are input to the selector 455. In the sector 455, the key code KC, the tone color code VN, the touch code TCH, the least significant bit PCLSB of the step signal PC output from the program counter 452, and "4" (binary "100") from the step signal PC are output. The subtracted data PC-4 is also input. The selector 455 selects the input data in a predetermined combination according to the selection control signal SELC1 given from the program memory 451, and positions the selected data at a bit position corresponding to a predetermined weight in the relative address data RADD. Data RADD
Create and output.

The processing contents of the 37 steps executed in the parameter processing unit 45 are as follows.

When PC = 0: The key code KC is selected by the key group table read processing selection control signal SELC1, and the offset address OADS of the key group table is read as the offset address data ADOF. Further, the output data of the parameter memory 47 is transferred to the key group address register 4 by the selection control signal SELC.
Take in 56. As a result, the key group address corresponding to the key code KC is read from the key group table of the parameter memory 47, and this is read in the register 45.
Stored in 6.

When PC = 1: Touch group table read processing The tone color code VN and the touch code T are generated by the signal SELC1.
CH is selected, TCH is placed in the least significant bit, and V is placed in the upper bit.
Position N to create relative address data RADD. The offset address OAD1 of the touch group table is read as the offset address data ADOF. The parameter memory 47 is generated by the signal SELC3
Output data of touch group address register 457
Take in. As a result, the touch group address corresponding to the tone color code VN and the touch code TCH is read from the touch group table of the parameter memory 47, and stored in the register 457.

When PC = 2,3: Parameter address table read processing Key group address data KE by signal SELC1
YG, tone color code VN, touch group address data TCHG, least significant bit PCLSB of step signal PC
And select the least significant bit from PCLSB, TCHG, V
Relative address data RA by locating in the order of N and KEYG
Create a DD. The offset address OAD2 of the parameter address table is read as the data ADOF. The parameter memory 47 is generated by the signal SELC4.
Of the output data of 1) is fetched into the parameter address register 458. As a result, an appropriate parameter address is read from the parameter address table of the parameter memory 47 and stored in the register 458. As described above, one parameter address data consists of 12 bits and is stored in the storage position of 2 bytes (second
(See Figure 1). When the bit PCLSB is "0" (PC =
2), the lower 8 bits of the parameter address data are read, and when PCLSB is "1" (PC =
Step 3), the upper 4 bits of the parameter address data are read. The selector 95 sorts the bit positions so that the parameter address data is parallelized into 12-bit data and stores it in the register 458.

When PC = 4 to 35: Parameter bank read processing Parameter address data PAD is generated by signal SELC1.
Then, the step signal PC-4 obtained by subtracting 4 and 4 is selected, and the relative address data RADD is created by locating PC-4 and PAD in order from the least significant bit. Further, the offset address OAD3 of the parameter bank is read as the data ADOF. The value of the signal PC-4 changes from "0" to "31" in 32 steps of PC = 4 to 35. Therefore, 32 specified by the parameter address
One set of filter parameters consisting of bytes (see FIG. 21) is 1 from the parameter bank of the parameter memory 47.
It is read byte by byte.

When PC = 36: The program counter 452 is stopped and the filter parameter reading sequence is completed.

The filter parameters read from the parameter memory 47 are input to the timing synchronization circuit 459. This circuit 459 receives the program step signal PC and the timing signal group TS1 given from the decoder 56 (FIG. 13) of the timing signal generating circuit 39, and based on these signals, synchronizes the filter parameter of each order with a predetermined timing. Output. The output of the synchronizing circuit 459 is the filter parameter SPR for the static mode.
Is given to the A input of the parameter selector 46.
A filter parameter DPR for the dynamic mode output from the microcomputer interface 44 (FIG. 11) is given to the B input of the parameter selector 46. The selection control input SB of the selector 46 is given the dynamic / static selection signal DS output from the microcomputer interface 44, selects the B input parameter DPR in the dynamic mode, and A in the static mode.
Select the input parameter SPR.

The output of the selector 46 is input to the A and B series parameter supply circuits 48 and 49. Although a detailed example is shown only for the A series circuit 48, the B series circuit 49 has the same configuration. In the parameter supply circuit 49, the distribution circuit 485 takes in the data regarding the channels 1 to 4 of the A series from the parameter data serially given from the selector 46, parallelizes the data for each channel, and filters the filter coefficient data (channel 1). COEA1), weighting data (WEIA1 for channel 1), and even / odd identification data (EOA1 for channel 1) are parallelized,
These are storage circuits 481 to 48 corresponding to the respective channels.
Distribute into 4. For such distribution control, an appropriate timing signal TS2 is generated from the decoder 56 (FIG. 13) of the timing signal generation circuit 39, and the distribution circuit 485 is generated.
Given to.

Although the storage circuits 481 to 484 show detailed examples of the channel 1, the same applies to the other channels. 12
The filter coefficient data COEA1 of bit is the selector 96
Is input to the 16-stage shift register 97 via. In this filter coefficient data COEA1, data of 16 orders is time-division multiplexed in 16 time slots, and the data of 16 orders is shift register 97.
Is captured in each stage of. The contents of the shift register 97 are cyclically held via the selector 96. The 3-bit weighting data WEIAI is input to the latch circuit 98. The 1-bit even / odd identification data EOA1 is the latch circuit 9
9 is input. Selector 96 and latch circuits 98 and 9
The control of 9 is performed at an appropriate timing by an appropriate control signal (not shown). That is, in the static mode, the parameter memory 4 is responded to in response to the start of key pressing.
Parameter data for 16 orders read from 7
In synchronization with the timing input to the memory circuit 481 via the timing synchronization circuit 459, the selector 46, and the distribution circuit 485, the selector 96 fetches the filter coefficient data COEA1 of 16th order into the shift register 97,
The latch circuits 98 and 99 latch the weighting data WEIA1 and the even / odd identification data EOA1. Thereafter, the memory of the shift register 97 and the latch circuits 98 and 99 is held until a new pressed key is assigned to the channel. On the other hand, in the dynamic mode, the parameter data DPR is synchronized from the microcomputer interface 44 (FIG. 11) through the selector 46 and the distribution circuit 485 in synchronization with the dynamic control parameter data DPR for eight orders. Of these, the filter coefficient data COEA1 for 8th order is taken into the shift register 97, the weighting data WEIA1 is latched in the latch circuit 98, and the even-odd identification data EOA1 is latched in the latch circuit 99. Thereafter, the storage of the shift register 97 and the latch circuits 98 and 99 is held until new dynamic control parameter data DPR is given. In the dynamic mode, out of the 16 stages of the shift register 97, 8 stages corresponding to the 9th to 16th orders store the filter coefficient data of the dynamic control parameters for the 8th order and correspond to the 1st to 8th orders. Set the contents of 8 stages to 0.

The filter coefficient data output from the shift register 97 of each of the memory circuits 481 to 484 is given to the selector 486, where the channels of each channel are sequentially selected according to the timing signal TS3 and time division multiplexed. In this way, the filter coefficient data for channels 1 to 4 is time-division multiplexed, and the A series of filter coefficient data COEA
As the A-sequence multiplier and accumulator unit 41 (first
4).

The weighting data output from the latch circuit 98 of each of the storage circuits 481 to 484 is given to the selector 487, where the data of each channel is sequentially selected according to the timing signal TS4 and time division multiplexed. Weighting data WEIA of channels 1 to 4 thus time-division multiplexed.
Is an A-sequence multiplier and accumulator unit 41 (14th
Supplied).

Even / odd identification data EOA1 to E of each channel 1 to 4 latched by the latch circuit 99 of each memory circuit 481 to 484
OA4 is the state memory 401-of the corresponding channel
404 (Fig. 14) in parallel.

<Pitch Synchronous Output Circuit 50: FIG. 16> In FIG. 16, the B input of the selector 501 is connected to the multiplier and accumulator section 41 of the A series (see FIGS. 11 and 14).
Filtered tone signal sample value data SMA of channels 1 to 4 output from the figure) are given in a time division multiplex manner. The timing at which the filtered outputs of the respective channels 1 to 4 are fetched in the latch circuit 85 of FIG. 14 is the last accumulated time slot (hatched portion) in the SUM column of FIG. The channel timing of the filtered sampled value data SMA of No. 4 is shown in FIG. The C input of the selector 501 has a B-sequence multiplier and accumulator unit 43.
Filtered tone signal sample value data SMB of channels 5 to 8 output from (FIG. 11) are given in a time division multiplex manner. The channel timing of this data SMB is as shown in FIG.

The output of the 8-stage shift register 502 is given to the A input of the selector 501, and the output of the selector 501 is input to the shift register 502. This selector 5
01 and shift register 502 are for time-division-multiplexing the filtered sample value data of each channel 1 to 8 in accordance with the high-speed time-division timing of one time slot unit as shown in the channel timing of PS1 in FIG. Is. From the decoder 56 of FIG. 13, the timing signal IREGLDA that becomes "1" in the time slots 57, 13, 26 and 46 and the time slots 11 and 3 are shown.
Timing signal I which becomes "1" at 1, 44, 64
REGLDB is generated, and this is selector 5 in FIG.
01 to B selection control input SB and C selection control input SC. As a result, the data SMA given to the B input is
Channel 1 data is time slot 57
(This corresponds to the timing of channel 1 of the channel timing of PS1 shown in FIG. 3), and the data of channel 2 is selected in time slot 13 (third
It is selected at the timing of channel 2 of PS1 in the figure)
The data of channel 3 is selected in the time slot 26 (timing of channel 3 of PS1 in FIG. 3), and the data of channel 4 is selected in time slot 46 (PS in FIG. 3).
1 channel 4 timing). Also,
Channel 5 of data SMB given to C input
Data is selected in time slot 11 (timing of channel 5 of PS1 in FIG. 3), data of channel 6 is selected in time slot 31 (timing of channel 6 of PS1 in FIG. 3), and data of channel 7 is selected. Is time slot 44 (PS1 channel 7 in FIG. 3)
Timing) and the data of channel 8 is selected in the time slot 64 (timing of channel 8 of PS1 in FIG. 3).

A signal obtained by inverting the timing signals IREGLDA and 1REGGLDB in the NOR circuit 503 is applied to the A selection control input SA of the selector 501. Therefore, the filtered sample value data of each channel taken into the shift register 502 at each of the above-mentioned timings is circularly held in the shift register 502 at the other timings.

The output of the shift register 502 is given to the A input of the selector 504. The output of the selector 504 is input to the 8-stage shift register 505. Shift register 50
The output of 5 is returned to the input side through the B input of the selector 504. The selector 504 and the shift register 505 are
This is for re-sampling the output tone signal of the digital filter in synchronization with its pitch. Selector 5
The input interface 38 is connected to the A selection control input SA of 04.
The delayed pitch synchronizing signal PS1D given from (FIG. 12) is inputted through the delay circuit 506 of 8 time slots.

In FIG. 12, the pitch synchronizing signal PS1 is the OR circuit 5
1 is input to the 64-stage shift register 100. A pitch synchronizing signal delayed by 24 time slots in this shift register 100 is input to the AND circuit 101, a signal delayed by 40 time slots is input to the AND circuit 102, and a signal delayed by 48 time slots is input to the AND circuit 103. And delayed by 64 time slots are input to the AND circuit 104. Timing signals PSS1 to PS generated from the decoder 56 of FIG. 13 are supplied to the other inputs of the AND circuits 101 to 104, respectively.
S4 is input respectively. The outputs of the AND circuits 101 to 104 are given to the OR circuit 105, and the delayed pitch synchronizing signal PS1D is obtained. Each signal PSS1 to PSS4
The timing of occurrence of is shown in parentheses in FIG. Here, for example, the display "1y8" indicates that the signal "1" occurs in the first time slot in eight time slot periods. Therefore, in the case of the timing signal PSS1, since it is "1y8, 3y8", the signal "1" is generated in each of the first and third time slots in the eight time slot period. Each signal PSS in FIG.
1 to PSS4 in parentheses and the channel timing of PS1 in FIG. 3, the signal PSS1 becomes "1" at the timing of channels 1 and 3 in PS1, and PSS2 becomes channel 2 in PS1. It becomes "1" at the timing of 6 and 6, and PSS3 becomes PS.
It becomes "1" at the timing of channels 3 and 7 in 1, and PSS4 becomes "1" at the timing of channels 4 and 8 in PS1.

From the above, the pitch period signal PS1 of channels 1 and 5
24 time slots, PS1 of 2 and 6 is 40 time slot, PS1 of 3 and 7 is 48 time slot, 4 and 8
PS1 is 64 time slots, and each delayed one is a delayed pitch synchronizing signal PS1D. The reason that the delay time differs depending on the channel is that it is adjusted to the deviation of the calculation timing of each channel 1 to 4 and 5 to 8 in the adaptive digital filter device 21 (FIG. 11).

Returning to FIG. 16, the delayed pitch synchronization signal PS1D is further delayed by 8 time slots in the delay circuit 506, and applied to the input SA of the selector 504. When the signal PS1D of a certain channel is “1”, the selector 504 takes in the filtered sample value data of that channel from the shift register 502 and inputs it to the shift register 505. At other times, the contents of the shift register 505 are circularly held via the B input of the selector 504. In this way, in the circuits of the selector 504 and the shift register 505, the filtered sample value data of each channel is resampled in synchronization with the pitch of the musical sound to be generated in that channel.

<Switching of Pitch Synchronization / Asynchronization of Filter Calculation> The pitch synchronization / asynchronization designation signal PASY given from the microcomputer interface 44 (FIG. 11) to the OR circuit 51 of FIG. 12 is always “0” when the filter calculation is performed in pitch synchronization. , And the input interface 38 responds to the pitch synchronization signal PS1 with the filter calculation request signals φF1 to φF1.
Generate F8 and the delayed pitch sync signal PS1D. Therefore, when the pitch synchronization signal PS1 is generated, that is, at the sampling period synchronized with the pitch of the tone signal to be filtered, the digital filter calculation is performed. As a result, the obtained filter characteristic becomes a moving formant.

When the filter calculation is performed without synchronizing with the pitch, the pitch synchronization / asynchronization designation signal PASY is always set to "1".
Therefore, the output of the OR circuit 51 in FIG. 12 is always "1" regardless of the presence or absence of the pitch synchronization signal PS1. Therefore, the input interface 38 generates the filter calculation request signals φF1 to φF8 and the signal PS1D at a constant cycle for each filter calculation cycle (64 time slots). Therefore, the sampling frequency in the digital filter calculation is constant (for example, 50 kHz) regardless of the pitch, and the obtained filter characteristic has a fixed formant.

<Example of Filter Characteristics> Examples of filter characteristics that can be realized by the above-described embodiment are shown in FIGS. 22 and 23.

FIG. 22 shows an example of characteristics obtained when the filter order is set to an odd order (31st order), and realizes a high-pass filter characteristic. fs / 2 is 1/2 of the sampling frequency fs, is a frequency synchronized with the pitch of a musical sound in the pitch period mode, and is a constant frequency in the pitch asynchronous mode.

FIG. 23 shows an example of characteristics obtained when the order of the filter is set to an even order (32nd order), and realizes a low-pass filter characteristic.

<Modification> The pitch synchronization output circuit 50 shown in FIG. 16 uses the shift registers 502 and 505 to perform pitch synchronization processing by channel time division, but the invention is not limited to this, and the channels are stored in parallel for each channel. A circuit may be provided and pitch synchronization processing may be performed in parallel.

In the above embodiment, the FIR filter having the symmetrical coefficient is used as the digital filter, but the present invention is not limited to this, and the FR filter having the asymmetric coefficient may be used. Also, the filter type is not limited to FIR but IIR (infinite impulse response)
Alternatively, other types may be used.

The storage format of the parameter memory shown in FIG. 21 is not limited to this, and various modifications are possible. For example, such a hierarchical structure may not be adopted.

Further, the method of addressing the parameter memory is not limited to the procedure shown in the above embodiment, and various changes can be made. For example, in the embodiment, the key group table is accessed first and then the touch group table is accessed, but this may be reversed. Further, in FIG. 15, the micro-programming method in which the reading procedure is stored in the program memory 451 in advance is adopted, and the parameter memory 47 is read by this, but it does not depend on such a micro-program method. The read control may be performed by a hard-wired circuit or a complete software program.

Further, although the present invention is applied to the multi-tone electronic musical instrument in the above embodiment, it is needless to say that the present invention can also be applied to the single-tone electronic musical instrument. Further, the present invention can be applied not only to a dedicated electronic musical instrument but also to general devices having a tone signal generating or processing function.

In the above embodiment, the digital tone signal sample value data itself input from the tone generator to the adaptive digital filter device is sampled in synchronization with the pitch, but the invention is not limited to this. For example, even when a digital tone signal sampled at a fixed pitch-asynchronous fixed sampling period is input to the digital filter device, the pitch-synchronized signal is used to resample the input digital tone signal to perform a filter calculation operation in synchronization with the pitch. do it.

In the above embodiment, the pitch synchronizing signal generating circuit is included in the tone generator, and the pitch synchronizing signal generated there is introduced into the adaptive digital filter device, but the present invention is not limited to this. For example, when a digital musical tone signal having a sampling period synchronized with the pitch is input to a digital filter, a pitch synchronizing signal is generated by detecting a change in sample value data of the digital musical tone signal, and the pitch synchronizing signal generated in this way is used. The filter calculation operation may be controlled.

[Brief description of drawings]

FIG. 1 is a block diagram showing an outline of the present invention, FIG. 2 is a block diagram showing an entire configuration of an electronic musical instrument according to an embodiment of the present invention, and FIG. 3 is a timing chart of main signals in the same embodiment. Timing chart, FIG. 4 is a block diagram showing an example of the pitch synchronizing signal generating circuit included in the tone generator of FIG. 2, FIG. 5 is a block diagram showing the basic configuration of the FIR filter, FIG. 6 and FIG. Are graphs showing an example of the symmetry of the impulse response in the linear phase FIR filter when the order N is an odd number and an even number, respectively. FIGS. 8 and 9 show examples of the frequency response characteristics in the linear phase FIR filter of the order N. Are graphs for odd and even, respectively, FIG. 10 is a flowchart showing an example of a procedure for obtaining the filter coefficient, and FIG. FIG. 12 is a block diagram showing an example of the adaptive digital filter device in FIG. 12, FIG. 12 is a block diagram showing an example of the input interface in FIG. 11, and FIG. 13 is a block diagram showing an example of a timing signal generating circuit in FIG. 11 is a block diagram showing an example of a state memory, a multiplier and an accumulator section (ie an example of FIR type digital filter circuit) in FIG. 11, and FIG. 15 shows an example of a parameter processing unit and a parameter supply circuit in FIG. Block diagram, FIG. 16 is a block diagram showing an example of the pitch synchronization output circuit in FIG. 11, FIG. 17 is a timing chart showing an example of generation of various signals for controlling filter operation timing, and FIG. 18 is shown in FIG. Even number in the digital filter circuit shown FIG. 19 is a schematic diagram for explaining the basic operation of the FIR type filter operation when realizing a filter characteristic consisting of (32nd order), and FIG. 19 is a case where a filter characteristic consisting of an odd number (31st order) is realized in the same digital filter circuit. FI
FIG. 20 is a schematic diagram for explaining the basic operation of the R-type filter operation, FIG. 20 is a diagram showing the filter operation operation timing for 8 channels in the A, B2 series digital filter circuit as shown in FIG. 14, and FIG. Is a diagram showing an example of a storage format in the parameter memory shown in FIGS. 11 and 15, and FIGS. 22 and 23 are realized in an embodiment of the present invention shown in FIGS. 2 to 21. FIG. 5 is a diagram showing an example of the filter characteristics to be performed for odd-order and even-order respectively. 110 ... Digital filter circuit, 111 ... Parameter generating means, 112 ... Gate, 113, 114 ...
Selector, 10 ... Keyboard, 11 ... Key touch detector, 1
8 ... Tone generator, 19 ... Pitch synchronization signal generating circuit, 21, 22 ... Adaptive digital filter device, 40, 42 ... State memory, 41, 43 ...
... Multiplier and accumulator unit, 45 ... Parameter processing unit, 47 ... Parameter memory, 50
...... Pitch synchronization output circuit.

Claims (1)

[Claims] 1. A delay means for inputting digital sample value data of a tone signal sampled in accordance with a predetermined sampling period, sequentially delaying the sampled data, and providing a maximum of n digital sample value data at which sampling points are sequentially shifted, and , A digital filter circuit having a calculating means for performing a filter operation by operating a plurality of digital sample value data whose sampling times are sequentially shifted provided by the delay means and a filter coefficient, and the order of the filter operation is an even order. Alternatively, the parameter generating means for generating an even-odd parameter set to either odd or odd order, and the predetermined even number of n or less depending on the even-odd parameter as the plurality of digital sample value data used in the filter calculation in the calculating means. Or select an odd number of sample value data And a digital filter device other delayed sample value data equipped with the excluded switching means from said filter operation.