JPH0644749B2 - Data transceiver - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission / reception device, and more specifically, it is connected to another communication device via a plurality of channels and performs error detection or error correction on data of each channel. It relates to a data transmitter / receiver as required.

BACKGROUND OF THE INVENTION Generally, in a communication system in which data is transmitted via a transmission line, each transmission data is redundant in order to detect a bit error occurring on the transmission line and correct the error bit if necessary. Bits are added. That is, the device on the data transmission side adds a redundant bit to the transmission data,
The device on the receiving side performs error detection or error correction on the received data by using the redundant bit added to the received data and the redundant data generated by itself regarding the received data.

However, in the conventional communication system having a plurality of channels, the error detection / correction function by the redundant bit described above is required for each channel, and when data transmission / reception of a plurality of channels is supported by one device, conventionally, Since the hardware for generating and checking the redundant bit is arranged for each channel, there is a drawback that the hardware scale of the data transmitting / receiving device becomes large.

FIG. 3 shows the data transmission / reception of such multiple channels.
The whole structure of the telephone exchange system shown as an example of the system supported by one data transmission / reception apparatus is shown.

In FIG. 3, telephone 307 (307-1-1 to 30--30)
7-NM is a relay device 306 (306-1 to 306).
-N) is connected to the switch 301, and the exchange function of the switch 301 allows communication between arbitrary telephones. Each relay device 306 has a built-in data transmission / reception device, and each has a connection line 305 (305-1 to 305-1).
305-N) and connected to the switch to multiplex the voice information from the telephone to these connection lines 305. Control information such as a dial signal is multiplexed on the connection line 305 together with voice information of the telephone.

The connection control between the telephones is performed by the control processor 302 of the switch 301 receiving a dial signal at the time of making a call, interpreting the dial signal, and controlling the switch via the control line 304. The dial signal from the originating telephone is
The signal is received by the relay device 306 and input to the switch 301 as a digital control signal.

The control signal (dial signal) is transmitted from the switch 301 to the control processor 302 via the connection lines 116 to 118 and 119 to 121, the data transmission / reception device 303, and the buses 114 and 115. The control processor 302
In order to process connection requests from a plurality of telephones, data is transmitted / received to / from a plurality of transmission channels via the data transmission / reception device 303. In this case, the data transmission / reception device 303
In the above, the problem of increasing the size of the hardware described above occurs.

In this type of telephone exchange system, data is transmitted and received in units of variable length packets, each packet comprises a header section and a data section, and information indicating the packet length is set in the header section. Therefore, the data receiving side device stores the packet length shown in the header part, and
The end of the packet can be detected by counting the byte length of the received data. A CRC (Cyclic Redundancy Check) code for error detection is added to the end of each packet, and a data transmission error in each received packet can be detected using this CRC. You can If the data error is within the specified number of bits, it can be automatically corrected.
When an uncorrectable error occurs in a packet, the source device is requested to retransmit the same data.

[Object of the Invention] An object of the present invention is to provide a data transmission / reception device which can be connected to another device through a plurality of channels and can simplify a hardware configuration for redundant bit processing for detecting or correcting a data error. Is to provide.

SUMMARY OF THE INVENTION In order to achieve the above object, according to the present invention, redundant bit processing for error detection or error correction is performed when a host device reads / writes transmitted / received data from / to a buffer memory unit, thereby performing redundant bit processing. It is characterized in that the means for sharing is shared by a plurality of channels and the hardware is simplified.

More specifically, the data transmitting / receiving device of the present invention is
A plurality of channels for data transmission, a buffer memory for temporarily storing transmission / reception data to which redundant bits for error detection and error correction are added, and transmission / reception between the plurality of channels and the buffer memory All the channels read from the buffer memory by the host device, comprising redundant bit processing means between the buffer memory and a host device accessing the buffer memory. With respect to the received data, the redundant bit processing means performs error detection and error correction based on the redundant bit added to each received data and the redundant bit generated by itself.

Utilizing the redundant bit generation function of the redundant bit processing means, error detection and error to be added to each data for transmission data of all channels written in the buffer memory by the host device by the same redundant bit processing means Redundant bits for correction may be generated.

[Embodiment of the Invention] An embodiment of the data transmitting / receiving apparatus of the present invention will be described below with reference to FIG. The data transmission / reception device shown here corresponds to, for example, the data transmission / reception device 303 shown in FIG.
Connected to an external device (upper control processor 302) via the data buses 114 and 115, and connected to another device (switch 301) via a plurality of input / output channels (signal lines) 116 to 118 and 119 to 121. There is.

In FIG. 1, 101 to 103 are input channels 11
An input shift register for converting serial data input from 6 to 118 into parallel data and outputting the parallel data.
09 to 111 are output shift registers for converting parallel data into serial data and outputting to serial output channels 119 to 121, 104 is a selector for selecting one of the outputs of the input shift register, and 105 is each input. A buffer memory for temporarily storing the input data (packet) from the channel, 106 a control device for controlling the operation of the data transmission / reception device, 107 a redundant bit generation / correction redundant bit process for error detection and correction. Detection circuit, 108 is an external device (upper control processor 302)
, 112 is an internal address bus, 113 is an internal data bus, and 114 and 115 are external address buses and external data buses for connecting to the upper control processor 302, respectively. In the figure, the signal line indicated by a thick line indicates that a plurality of bits of data are transmitted in parallel.

In this example, each channel 116-118, 11
The input / output data 9 to 121 are packets of variable length, and data is transmitted / received in 1-byte units between the external device (upper control processor 302) and the data transmitting / receiving device via the data bus 115.

For example, data (packets) from the relay devices 306-1 to 306-N shown in FIG. 3 are received by the input channels 116 to 118, and a part of them is sequentially transferred to the 8-bit shift registers 101 to 103. The input data, which is output from each shift register, is sequentially selected in 1-byte units by the selector 104 and input to the control device 106.

The control device 106 manages transmission / reception of data between the input / output channel and an external device (upper control processor 302). Data transmission / reception between the control device 106 and the higher control processor 302 is performed via the buffer memory 105. Be seen. For example, the received data from the selector 104 is stored in the buffer memory 105, and the control processor 30
2 is written in the buffer memory 105 by the relay device 306
-1 to 306-N transmission data addressed to the buffer memory 10
5 and supplies it to any of the output shift registers 109 to 111 via the output bus. The output shift register is designated by giving a register address on an address bus forming a part of the output bus. Each shift register 109-111 takes in the transmission data supplied from the control device 106, parallel-serial converts it, and outputs it to the corresponding output channel 119-121.

The buffer memory 105 is provided with a data area for storing the above-mentioned transmission / reception data (packet) and a flag area for indicating the presence / absence of unprocessed transmission / reception data corresponding to each input / output channel. There is. Control device 10
When writing data for one packet from the input channel to the data area of the buffer memory 105, the bit 6 sets the bit in the flag area corresponding to the input channel to the "1" state.

The upper control processor 302 periodically checks the input channel flag area of the buffer memory 105, and if the bit is “1”, reads the packet data from the data area of the corresponding channel and sets the bit to “0” state. Return to. On the contrary, when the transmission data from the upper control processor 302 is written in the data area of the buffer memory 105, the upper control processor 302 sets the bit of the flag area of the corresponding output channel to "1".

The control device 106 periodically checks the output channel flag area of the buffer memory 105, and if the bit is “1”, reads the packet data from the data area of the corresponding channel and communicates with the above channel via the output bus. After supplying the corresponding output shift register, the state of the above bit is returned to "0".

The external device (upper control processor 302) transmits the flag bit and the transmission data to the above-mentioned buffer memory 105 via the external address bus 114 and the external data bus 115, the interface circuit 108, the internal address bus 112 and the internal data bus 113. Write and read received data and flag bits. As for the received data, after the control device 106 has completed storing one packet of data in the buffer memory 105, the control processor 302
Is read from the buffer memory 105. The transmission data is read out to the output register by the control device 106 after the writing of one packet of data from the control processor 302 to the buffer memory 105 is completed.

In the present invention, the redundant bit generation / check circuit 107 for error detection and correction is arranged between the buffer memory 105 and the interface circuit 108, and the external device (upper control processor 302) receives the received data from the buffer memory 105. The redundant bit check operation is performed when read, and the redundant bit generation operation is performed when transmission data is written in the buffer memory 105.

FIG. 2 shows an embodiment of the error detection / correction redundant bit generation / check circuit 107 shown in FIG. here,
A configuration is shown in which a CRC is used as a redundant bit for error detection, and a CRC generation circuit and a CRC check circuit are used in common.

In FIG. 2, 112 is an internal address bus, 113 is an internal data bus, 201 is a CRC generation / check circuit, 20
2 and 210 are selectors, 204 and 205 are shift registers, and 203 and 206 are the shift registers 20 described above.
4 shows a tri-state output bus buffer for outputting the contents of 4 and 205 to the internal data bus 113. Also, 2
Reference numeral 07 is a control circuit for the redundant bit generation / check circuit, and 208 and 209 are a data bus and an address bus connected to the interface circuit 108 shown in FIG.

From the external device (upper control processor 302) to the relay device 3
When writing the transmission data addressed to 06 to the buffer memory 105, the transmission data is temporarily stored in the shift register 204. The contents of the shift register 204 are the contents of the selector 2
It is serially supplied to the CRC generation / inspection circuit 201 via 02, and the CRC code corresponding to the transmission data is calculated. The transmission data supplied to the CRC generation / inspection circuit 201 is again sent to the shift register 2 via the selector 210.
It is stored in 04.

At the time when the calculation of the CRC code is completed, the shift register 204 stores the transmission data from the upper control processor again, and this transmission data is then transmitted via the tri-state buffer 203 and the internal data bus 113. It is written in the buffer memory 105.

The above operation is repeated a plurality of times in units of 1 byte, and when the writing of the transmission data for one packet into the buffer memory 105 is completed, the CRC code for the packet is calculated in the CRC generation / control circuit 201. Therefore, at a predetermined timing after the CRC calculation of the last 1 byte of the transmission data is completed, the selector 210 is switched to input the CRC code to the shift register 204 and write it into the buffer memory 105 via the data bus 113. .

On the other hand, received data input from each of the input channels 116 to 118 (from the relay device 306 to the upper control processor 30)
2) is read from the buffer 105 and is transferred via the internal data bus 113 to the shift register 20.
Once stored in 5, the CRC is passed through the selector 202.
Input to the generation / check circuit 201 serially, CR
The C code is calculated.

The received data whose CRC has been calculated is supplied to the control circuit 207 via the output bus buffer 206 and sequentially output to the data bus 208. The control circuit 207 detects the last byte of the received data (packet) by counting the byte length of the data transmitted to the upper control processor 302 via the data bus 208, and the CRC code added to this is detected. CRC check circuit 201
When it is input to, the CRC check result is fetched via the shift register 205. Therefore, the upper control processor sends the CRC check result to the data bus 20.
By accessing via 8, it is possible to know the transmission error.

[Effects of the Invention] As described above, in the data transmitting / receiving device of the present invention,
By sharing the redundant bit processing circuit for error detection and correction with multiple channels, it is possible to significantly reduce the amount of hardware as compared with the conventional device configuration provided for each channel. It will be possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the main configuration of a data transmitting / receiving apparatus according to the present invention, FIG. 2 is a diagram showing a detailed configuration of a redundant bit generating / checking circuit in FIG. 1, and FIG. It is a figure which shows the structure of the telephone exchange system which is an example of the application system of the data transmission / reception apparatus of this invention. (Explanation of symbols) 101 to 103, 109 to 111 ... Shift register,
104 ... Selector, 105 ... Buffer memory, 10
6 ... Control device of data transmission / reception device, 107 ... Redundant bit generation / inspection circuit for error detection and correction, 108 ... Interface circuit with external device (upper control device), 1
12 ... Internal address bus, 113 ... Internal data bus, 114 ... External address bus, 115 ... External data bus, 201 ... CRC generation / check circuit, 202, 2
10 ... Selector, 204 to 205 ... Shift register, 203, 206 ... Tristate buffer, 20
7 ... CRC generation / inspection circuit control circuit, 208 ... Data bus, 209 ... Address bus, 301 ... Exchange switch, 302 ... Control processor (external device), 30
3 ... Data transmitting / receiving device, 304 ... Switch control signal line, 305 ... Connection line, 116-118, 119-12
1 ... Channel, 306 ... Relay device, 307 ... Telephone, 114 ... External address bus, 115 ... External data bus

Claims (2)

[Claims] 1. A plurality of channels (11) for data transmission.
6 to 118, 119 to 121), buffer memory means (105) for temporarily storing transmission / reception data to which redundant bits for error detection and error correction are added, the plurality of channels and the buffer memory means. And a control means (106) for controlling transmission / reception of transmission / reception data between the buffer memory means and a host device (302) for accessing the buffer memory means, the buffer memory means (105) And host device (30
2) with redundant bit processing means (107), the redundant bit processing means converts the received data of all channels read from the buffer memory means by the host device into each received data. A data transmission / reception device characterized by performing error detection and error correction based on an added redundant bit and a redundant bit generated by itself. 2. The redundant bit processing means generates redundant bits for error detection and error correction to be added to each data, with respect to transmission data of all channels written in the buffer memory by the host device. The data transmission / reception device according to item 1.