JPH0644751B2 - Repeater for data transmission - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a relay device for data transmission, and more particularly to a relay device (hereinafter referred to as a relay device) suitable for a data transmission system using a balanced transmission line.

[Background of the Invention]

Conventionally, in a data transmission system of a type in which a repeater is installed, NIKKEI ELECTRONICS
As shown on pages 236 to 237 of 1984.2.27, a signal transmission line for controlling the data transmission direction of the repeater is required in addition to the data transmission line.
This situation will be described with reference to FIGS. 3 and 4.

FIG. 3 is a schematic diagram of a multipoint, polling / selection type data transmission system in which a transmission line is relayed by a repeater. Although a system control line of the repeater is not logically necessary on the main station side, In addition to the data lines DPb and DNb, the slave stations located on the opposite side of the master station from each other require the repeater direction control lines RTSP and RTSN.

FIG. 4 shows a mode of circuit connection between the repeater and the slave station, and the transmission lines DPa, DNa, DPb, DNb are the same as the transmission lines of FIG. The receiver 1a is
The differential signal from the main station is received, and the transmission line DPa has the same D
When the output level is higher than Na, the output is high level, D
When Pa is lower than DNa, the output is low. The transmitter 2a converts the output of the receiver 1a into a differential signal again and outputs it to the transmission lines DPb and DNb. On the contrary, the reception 1b and the transmitter 2b are the transmission lines DPb and DN.
The signal on b is received and sent on the transmission lines DPa and DNa. The transmission line RTSP, R is connected to the input of the receiver 1c.
It is followed by TSN, the output of which is connected to the enable terminal E of the transmitter 2a and the input of the inverter circuit 10a. The output of the inverter circuit 10a is connected to the enable terminal E of the transmitter 2b. When the enable signal is at the low level, the transmitters 2a and 2b have their outputs disabled, and their outputs have a high impedance state.

The transmitters 2c and 2d in the slave station are the transmitters 2a and 2d in the repeater.
2b, which sends data and a repeater direction control signal, respectively. The input of the transmitter 2c is transmission data, but the input of the transmitter 2d is a low fixed signal. Then, the receiver 1d receives the differential signals on the data transmission lines DPb and DNb and converts them into non-differential signals.

The slave station disables the transmitters 2c and 2d except when returning a response to the polling from the master station, so that the output is in a high impedance state. At this time, the transmission line RTSP in the input of the receiver 1c is pulled up and the line RTSN is pulled down, and the output of the receiver 1c becomes high level. That is, the transmitter 2a is enabled and the transmitter 2b is the inverter 1
Since the output of 0a is at a low level, it is in a disabled state, and only the data from the main station is transmitted to the transmission lines on both sides of the repeater.

When returning a response from the slave station to the master station, both transmitters 2c and 2d are enabled. At this time, low-fixed data is output from the transmitter 2d, the transmission line RTSP becomes low level from the transmission line RTSN, the receiver 1c senses this, the output becomes low level, and the transmitter 2a is disabled. , The transmitter 2b is enabled. Since the master station is waiting for a response from the slave station, the transmitter of the master station is in a disabled state, so the response data of the slave station is transmitted to both sides of the repeater on the data transmission line.

As is apparent from the above description, in the conventional system, in addition to the data transmission line, the transmission line for controlling the repeater is required, so the cost of the cable for the transmission line is high, the number of cables, the equipment due to the increase in diameter, This caused problems such as increased complexity of facilities.

[Object of the Invention]

An object of the present invention is to provide a novel relay device for data transmission which eliminates the problem that the conventional system has, by eliminating the need for a transmission line for controlling the data transmission direction of the relay device. It is in.

[Outline of Invention]

According to the present invention, when a signal is propagated to the data transmission line, the transmission line on the signal source side of the repeater is not in the high impedance state first, and the signal is propagated to the transmission line on the side opposite to the signal source of the repeater. It was decided that there would be a delay of a certain amount of time, and the data transmission direction of the repeater was determined by taking the one of the transmission lines on both sides of the repeater that was no longer in the high impedance state as the signal source side. To do.

Example of Invention

An embodiment of the present invention will be described below with reference to FIGS. 1, 2 and 5.

FIG. 5 is a schematic diagram of a data transmission system to which the repeater of the present invention is applied. The third point is that transmission lines RTSP and RTSN for controlling the data transmission direction of the repeater are not provided.
It differs from the figure.

FIG. 1 shows an embodiment of the repeater of the present invention. In the figure, 1a is a differential type receiver, the transmission lines DPa and DNa on the A side of FIG. 5 are connected to its input, and its output is connected to the input of the differential type transmitter 2a. Transmitter 2
The differential output of a is the transmission line DPb, D on the B side in FIG.
It is connected to Nb and constitutes one transmission line. Also, these transmission lines are connected to the differential inputs of the receiver 1b. 3a
Is a high impedance detection circuit, the data transmission lines DPa and DNa of which are connected to the input, and the output signal HZa of which is connected to one input of the OR circuit 5a. The high level fixed signal HIGH is connected to the data input terminal D of the memory element 4a, the output Ra of the OR circuit 5a is connected to the reset terminal R, and the output Ta of the inverter 6a is connected to the trigger terminal T. Storage element 4
The 1-side output of a is connected to the enable terminal E of the transmitter 2a. The storage element 4a receives the high level signal from the D terminal, and when the trigger terminal T rises from the low level to the high level, the 1-side output is at the high level, and when the reset terminal R is at the high level, it is called the trigger terminal T. It has a function of giving priority to the data terminal D, that the 1-side output is low level and the 0-side output is high level.

The output of the AND circuit 7a is connected to the other input of the OR circuit 5a. The input of the inverter 6a is the output signal HZa of the high impedance detection circuit 3a. AN
The 0-side output of the storage element 4a is connected to one input of the D circuit 7a, the output of the inverter 8a is connected to the other input, and another high-level output is connected to the input of the inverter 8a.
The output signal HZb of the impedance detection circuit 3b is connected.

Circuits 1b to 8b, 2b, 3b which are exactly the same as those described above
Etc. are connected as shown.

FIG. 2 shows the high impedance detection circuit section 3a,
3b shows the configuration. In the figure, 1c and 1d are receivers having the same functions as the above-described receivers 1a and 1b, and the circuit 11 is an inversion circuit of exclusive ORs of outputs of the receivers 1c and 1d.

To explain the operation of the repeater configured as described above, first, although not shown in FIG. 1, both the memory elements 4a and 4b are reset by power-on reset at power-on,
The transmitters 2a and 2b are in the disabled state, and the output has a high impedance.

Therefore, when data transmission is not performed, both the A side and B side transmission lines are in a high impedance state.
In the high impedance detection circuit shown in the figure, the + side input of the receiver 1c is pulled up to a high level, and the − side is pulled down to a low level. At this time, the output of the receiver 1c is at a high level. Becomes Similarly, the receiver 1d has a high level output, and the output of the exclusive OR circuit 11 has a high level HZ. In FIG. 1, the signals HZa and HZb correspond to the signal line HZ in FIG. 2 and are at high level. Therefore, the signal R in FIG.
a and Rb also become high level, both storage elements 4a and 4b are reset, the 1-side output is low, and transmitters 2a and 2b
b is in a disabled state, that is, the data transmission line DP
a, DPa, DNa, DNb are in a high impedance state.

Next, when the main station starts data transmission, the A-side data transmission lines DPa and DNa are at high level and low level, respectively, when the transmission signal is logic 1, and at low level and high level, respectively, when the transmission signal is logic 0. That is, the high impedance detection circuit 3a has a DP
Is at a high level, DN is at a low level, and the receiver 1
The + side terminal of c is high, the − side terminal is low, and the output becomes high level. On the contrary, the positive terminal of the receiver 1d is low,-
The side terminal is high and the output is low level. Then, the output HZ of the exclusive OR circuit 11 becomes low level. When the transmission signal is logic 0, DPa is at low level, DNa is at high level, and the high impedance detection circuit output HZ is at low level.

In this way, the signal HZ that is one input of the OR circuit 5a becomes low level, and the output HZb of the other high impedance detection circuit 3b is still high level at the other input of the OR circuit 5a. , Inverter 8
The output of a becomes low level, the condition of the AND circuit 7a is not established, and it becomes low level. Therefore, the OR circuit 5
The output signal Ra of a becomes low level and the reset terminal also becomes low level. Since the output of the inverter 6a changes from the low level to the high level, the storage element 4a shifts to the high level state, and the 1-side output also becomes the high level, so that the transmitter 2a is enabled and the signal received by the receiver 1a. Is transmitted to the B side through the transmitter 2a.

As a result, that is, the transmission line on the B side shifts to the signal transmission state, the output HZb of the high impedance detection circuit 3b shifts from the high level to the low level.
As a result, the output of the inverter 6b changes from the low level to the high level, so that a trigger is applied to the storage element 4b. However, the high impedance detection circuit 3a
Output HZa is already at the low level, the output of the inverter 8b, that is, the input of the AND circuit 7b is at the high level,
Similarly, the 0-side output of the memory element 4b, which is the other input of 7b, is at a high level because the element 4b is now in the reset state, and the output of the AND circuit 7b, that is, the OR circuit 5
One input of b becomes high level, and the output signal Rb of the circuit also becomes high level. Therefore, the storage element b is reset, the 1-side output is at the low level, the transmitter 2b is disabled, the output remains in the high impedance state, and the A-side transmission line is not disturbed by the transmitter 2b. .

When the signal transmission is completed and there is no output from the main station, A
The transmission line on the side is in a high impedance state. At this time, the output HZa of the high impedance detection circuit 3a
Becomes high level as described above, and as a result, the output signal Ra of the OR circuit 5a becomes high level, the memory element 4a is reset, the transmitter 2a is disabled, that is, the data transmission lines DPb and DNb are high impedance. It becomes a state. As a result, the memory element 4b remains in the reset state as before, and the transmitter 2b is also kept in the disabled state.

Although not shown in the drawing, a noise removal circuit for the high impedance detection circuit outputs HZa and HZb and a signal T
A circuit for delaying a with respect to the signal Ta may be added.

〔The invention's effect〕

According to the present invention, a transmission line for controlling the repeater is not required other than the data transmission line, so that the following effects can be obtained.

(1) The cost of the entire system can be reduced.

The reduction rate varies depending on the size of the system, but generally 12
It can be reduced by a factor of 1 to 6.

(2) Since the transmission line cable can be made thin when the system equipment is installed, the work can be simplified and the appearance of the equipment can be improved.

(3) Since the focus is on the high impedance state of the balanced transmission line, when a signal is propagated to the transmission line, it can be recognized as the transmission state regardless of whether the signal (data) is 0 or 1.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of a relay device according to the present invention, FIG. 2 is a detailed diagram of a high impedance detection circuit in FIG. 1, and FIG. 3 is a schematic of a data transmission system using a conventional relay device. FIG. 4 and FIG. 4 are configuration diagrams of a conventional repeater, and FIG. 5 is a schematic configuration diagram of a data transmission system using the relay device of the present invention. 1a to 1d ... Differential type receiver, 2a to 2f ... Differential type transmitter, 3a, 3b ... High impedance detection circuit,
4a, 4b ... Transmitter control storage element.

Claims (1)

[Claims] 1. A relay device for relaying data transmission between devices by a balanced transmission line, which is in a high impedance state when a signal is not transmitted and is in a low impedance state when a signal is transmitted, Receiving means for receiving a signal from the balanced transmission line, a first transmission line having a transmitting means for sending a signal received by the means to the balanced transmission line on the other side, and receiving a signal from the balanced transmission line on the other side In the relay device, the receiving means of the first transmission path is connected in parallel with the second transmission path including the transmission means for sending the signal received by the means to the balanced transmission line on one side. First impedance detecting means for detecting an impedance state of the input balanced transmission line on the one side, and balanced transmission line on the other side input to the receiving means of the second transmission line. If both the second impedance detecting means for detecting the impedance state of the high impedance state and the first and second impedance detecting means detect the high impedance state, the transmitting means of the first and second transmission lines are turned on. When both are in the disabled state and the first impedance detecting means detects the low impedance state prior to the second impedance detecting means, the transmitting means of the first transmission line is enabled and the second impedance detecting means is provided. A relay device for data transmission, comprising: control means for enabling the transmitting means of the second transmission path when the means detects the low impedance state prior to the first impedance detecting means.