JPH0644822B2 - Satellite receiver - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a satellite broadcast receiver for receiving a plurality of television signals having different polarization planes transmitted from a satellite.

2. Description of the Related Art Conventionally, satellite broadcasting (television signals) in the 4 GHz band (C band) such as the United States is composed of two types of signals whose polarization planes are vertical and horizontal. For example, when a television signal of 24 channels (3.72 to 4.18 GHz) is emitted from one satellite, the odd channel is sent in the vertical polarization plane and the even channel is sent in the horizontal polarization plane. Each channel (there is also a satellite with the opposite polarization plane) has an occupied band of 40 MHz and CH space of 20 MHz, and the polarization plane is switched to prevent interference. In such satellite broadcasting, a signal provided on either the vertical or horizontal plane of polarization is taken out by a polarizer provided at the focal point of a receiving antenna and transmitted to a low noise converter (LNB) provided behind the polarizer. It is composed.

FIG. 7 shows an example of the configuration of the conventional satellite broadcast receiver described above.

In FIG. 7, 1 is an antenna, 2 is a polarizer, and 3 is an LN.
B, 4a, and 4b are LNB ₃ and the columns of the polarizer 2, and the columns 4
The power to the signal cable and the polarizer 2 and the control signal transmission line 5 are installed along b. Needless to say, 6 is a column of the antenna 1, and the elevation angle and direction (eastward or westward) of the antenna 1 can be changed. Reference numeral 7 is a satellite broadcast receiver, which is composed of the following components. 8 is a tuner also called 2nd mixer, LNB ₃ is 3.72-4.18GH
The 24 waves of the center frequency of z are converted into 24 waves of 970 to 1430 MHz, and the tuner 8 tunes to one of them. The output of the tuner 8 has an IF frequency of 510 MHz and the band is, for example, 25 MHz. Reference numeral 9 denotes a video intermediate frequency amplifier circuit (hereinafter I
F circuit), which includes a bandpass wave filter (BPF). 10 is a wideband FM detection circuit, for example, PL
L detection is used. Reference numeral 11 is a voice detection circuit 11 for performing FM detection of a voice carrier being output from the FM detection circuit 10. The voice signal processing circuit 13 converts the output of the voice detection circuit 11 into an appropriate level and frequency characteristic and outputs the same. , RF
The output of the audio signal processing circuit 13 is supplied to the converter 14. On the other hand, the video signal processing circuit 12 removes the high frequency component of 4.2 MHz or more and the energy diffusion signal, outputs the signal at an appropriate level, and supplies the output of the video signal processing circuit 12 to the RF converter 14. Reference numeral 15 is an automatic polarization control circuit which changes the plane of polarization and stops it at the optimum point.

An example of the automatic polarization control circuit 15 is shown in FIG. First, the desired wave is set to N channel. Signal sent (N-
The spectra of 1), N, and (N + 1) have the same level when considered in the IF band, as indicated by the solid line in FIG. 9 (A). In this case, the center of the (N-1) channel is 490MHz,
It is assumed that the center of the (N + 1) channel is 530 MHz. When the plane of polarization of the polarizer 2 is approximately in the middle between the vertical and horizontal directions, when the signal passes through the band pass wave filter as shown in Fig. 9 (B), the output of the IF circuit 9 is shown in Fig. 9 (C). It becomes like. If the N-channel signal is vertically polarized and the plane of polarization of the polarizer 2 is vertical, the signal of the adjacent channel is reduced by about 15 dB as indicated by the dotted line in FIG. 9 (A). (When the degree of separation of the polarizer 2 is set to 15 dB) Therefore, when passing through the band pass wave filter,
The spectrum is as shown in FIG. 9 (D).

In the above description, the spectrum is illustrated assuming that the frequency shift of the FM of a normal television signal is about 10 MHz on average. The same applies to the following figures. On the other hand, the relationship between the polarization plane of the polarizer 2 and the output of the AGC detection circuit 16 is the first
It is shown by the solid line in Fig. 1 (A). The AGC detection circuit 16 uses I
A DC voltage proportional to the output of the F circuit 9 is generated, the gain of the IF amplifier circuit in the tuner 8 is controlled, and the input and output of the IF circuit 9 are kept constant. That is, AGC is not applied to the IF circuit 9. Therefore, when the plane of polarization becomes vertical and the signal amplitude becomes maximum, the output of the AGC detection circuit 16 becomes maximum. That is, the polarization plane is changed from the reference point 0 degree to the point where the polarization plane (probe in the case of a polar rotor) of the polarizer 2 is rotated horizontally by −45 degrees or more, that is, from ST in FIG.
Horizontal (-45 degrees), 0 degrees, vertical (+45 degrees) changes,
A point that is further past the vertical, that is, 1 in END in FIG.
Assuming that the sweep of the polarization plane is completed, the change in the ideal operating state is as shown by the solid line in FIG. 11 (A). Similarly, the relationship between the angle of the plane of polarization and the output of the AGC detection circuit 16 when receiving a horizontally polarized signal is shown by the dotted line in FIG. 11 (A).

It is in an ideal state that the relationship of the dotted line or the solid line of FIG. 11 (A) is obtained, but the operation at this time is shown in FIG. 8 and FIG.
Described with (A). When the desired wave is the N channel, when the channel N is designated, the output of the 3-input NOR gate 21 becomes low level, sets the flip-flop 20, and its Q output becomes high level, and the sweep voltage generating circuit 19 To generate a sawtooth voltage or a triangular wave.
On the other hand, the output of the 3-input NOR gate 21 is transmitted to the peak hold circuit 17 to discharge the held voltage. The polarization plane of the polarizer 2 changes as the output voltage of the sweep voltage generating circuit 19 changes. When a type called a ferro-feed is used as the polarizer 2, a sweep voltage is amplified and used. Since the rotation of the plane of polarization is determined in comparison with the pulse width in the type called polara, the sweep voltage is converted into the pulse width by the pulse generator 22 and supplied to the polarizer 2. Here we consider a polarota. Change the polarization plane from ST in Fig. 11 (A) to +45
Every time, when the AGC voltage is maximized value, peak hold the peak voltage P _V peak-hold circuit 17. When the sweep voltage reaches END, the same change is made from ST again. At this time, the level comparator 18 compares the output of the AGC detection circuit 16 with the output of the peak hold circuit 17, and when they match, outputs a negative pulse and resets the flip-flop 20. The Q output of the flip-flop 20 becomes low level, the sweep voltage of the sweep voltage generating circuit 19 is not generated, and the DC power for rotating the rotor of the polarizer 2 is also not supplied from the DC voltage supply circuit 23. (The DC voltage supply circuit 23 supplies DC power to the polarizer 2 only while Q of the flip-flop 20 is at a high level.) Therefore, the polarization plane of the polar rotor is + at the optimum position.
Stop at 45 degrees.

Next, consider a case where the desired wave is 4 to 5 dB weaker than the adjacent CH. (In reality, such a situation occurs in the United States.) When the plane of polarization of the polarizer 2 is in the middle between horizontal and vertical,
Alternatively, when there is no polarizer 2, the first side is set on the output side of the tuner 8.
The spectrum is as shown in Fig. 0 (D). At this time, assuming that the polarization plane in the previous state is horizontal and this time it is vertical, when the polarization plane of the polarizer 2 does not start changing, the output of the tuner 8 is the first.
It is as shown in FIG. 0 (A), and the spectrum is as shown in FIG. 10 (D) even after passing through the band pass wave filter. In such a state, when the plane of polarization is changed from ST, FIG.
(B) 'at the _H peak, P' as P of the dashed line of _V
Or become higher, even if P _'towards the _V is _P' higher than _H,
To be a peak in front of the regular P _V there. At this time, the output of the tuner 8 is as shown in FIG. When the influence of the adjacent wave is small, the solid or broken line in FIG. 11 (B) results and the optimum plane of polarization is determined as in the case of FIG. 11 (A). Even when the power is turned on or when the start of the sweep is manually instructed, the operation is performed as described above.

Incidentally, so-called ground wave interference, 500 MHz, if in the vicinity of 520 MHz, _P H of Figure 11 than the effect 12, AGC voltage at a point other than _{P V} can not set the optimum polarization becomes maximum.

Problems to be Solved by the Invention However, the above-described configuration has a problem that the following malfunctions often occur due to the strength and weakness of radio waves, interfering waves, and the like.

(1) Malfunction due to the influence of adjacent channel signal.

(2) Malfunction due to input difference between adjacent channel and desired wave signal.

(3) Malfunction due to ground wave interference.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a satellite broadcast receiver that does not cause the above malfunctions.

Means for Solving the Problems The present invention is to solve the above-mentioned problems, and a polarizer that can change the reception polarization plane in accordance with the polarization plane of a radio wave, and data that determines the polarization plane of the polarizer. A plurality of memories, a holding circuit for holding a peak voltage for optimizing the polarization plane, and a detection circuit for detecting the peak voltage, in a range where the position of the antenna is not switched. ,
The vertical and horizontal polarization planes are automatically changed, and the optimum point data is set and stored once with respect to the vertical and horizontal polarization planes, and then the polarization is based on the stored data every time the reception frequency is switched. It is configured to change and set the polarization plane of.

Operation The present invention has the above-described configuration to remove the interference of the ground wave and the adjacent wave, and by using the optimum polarization plane data, the polarization plane can be correctly set even in the channel having the strong ground wave interference.

Embodiment FIG. 1 is a block diagram of the essential parts of a satellite broadcast receiver according to an embodiment of the present invention. In the figure, reference numeral 24 is a narrow band wave device for AGC (hereinafter referred to as BPF), which has characteristics as shown in FIG. 2B. 25 is a 2-input NAND gate, 26 is an oscillator, 27 is a counter, 28 is a match detection circuit, 29 is a counter, 30 is a flip-flop (hereinafter referred to as FF), 3
1 is an inverter, 32 and 34 are 3-input AND gates, 33
Is an inverter, 35 and 37 are latch memories, 36 and 38 are flip-flops (hereinafter referred to as FF), 39 and 40 are 3-input AND gates, 41 is an OR gate, 42 is a data selector, and 43 is a 3-input NOR gate. Is.

First, the outline of these operations will be described. Temporary wave N
₁ is 5 dB weaker than the adjacent waves N ₀ and N ₂ , and if the polarizer is aligned with the polarization plane of the adjacent waves (here, vertical),
When input to the BPF 24, the solid line in FIG. The desired wave peak is 20 dB lower than the adjacent wave peak. However, IF
When it is assumed that the bandpass filter is not included in the input side of the circuit 9, and the input wave of the IF circuit 9 has the characteristic shown in FIG. 10 (B), the desired wave is It becomes the dashed-dotted line in Fig. 2 (A). The desired wave peak is 5 dB lower than the adjacent wave peak. In either case, the adjacent wave is stronger than the desired wave, so if the characteristics of the BPF 24 are the characteristics of FIG.
The output of the PF 24 is shown in FIG. 2 (C), and the influence of adjacent waves disappears. At this time, the adjacent wave is attenuated by 10 dB or more from the peak of the desired wave even at the maximum. Polarization plane is desired wave (horizontal)
When it matches the polarization plane of, the peak of the desired wave is 25 dB or more stronger than the maximum value of the adjacent wave. However, the vertical and horizontal separation of the polarizer is set to 15 dB. The output of BPF24 is AGC
It is assumed that the detection is performed by the detection circuit 16 and the peak hold is performed as described above (conventional example), and if the pulse width supplied to the polarizer is changed by the oscillator 26 to the counter 29, the polarization plane of the polarizer 2 changes. Then, a curve between the plane of polarization and the output of the AGC detection circuit 16 as shown in FIG. 11 (A) is obtained. The value of the counter 29 at the peak point is stored in the latch memories 35 and 37. That is, the latch memory 35 is the value of the counter 29 of the odd-numbered channel (here, vertical polarization is assumed), the latch memory 3
Reference numeral 7 stores the value of the counter 29 of the even channel (here, horizontal polarization), and the contents of the latch memory 35 for the odd CH and the contents of the latch memory 37 for the even CH are stored for each CH switching. Is preset in the counter 29 to determine the plane of polarization.

The operation will be described in detail below with reference to FIGS. 3 and 4. First, the polariser is a pulse motor that rotates the probe. When changing the pulse width from 0.75ms to 2.25ms, the probe rotates up to 270 °, and the standard is 1.25ms.
It is assumed that the pulse width is vertical and the polarization plane is horizontal at 1.75 ms. However, 0.75ms to 2.25ms for commercially available products
Since there are almost no 270 ° rotations and there are many rotation angles narrower than 270 °, even if the pulse width is changed from 0.75ms to 2.25ms, there is one vertical and horizontal polarization plane (optimal point). Only the characteristics shown by the wavy line or the solid line in FIG. 11 (A) can be obtained. In Fig. 1, the oscillator 26 is 3.45 with crystal control.
The counter 27 is assumed to be oscillating at MHz (pulse cycle is about 289.9 ns), and the counter 27 is a 16-bit binary counter (hereinafter referred to as a counter). Only the first bit of the counter 27 (φ _{1 in} FIG. 3) is taken out by the gate and transmitted to the NAND gate 25 and the FF 30. When the power is turned on, the antenna is switched, or the manual polarization setting is started, NO
The output of the R gate 43 changes from high to low, and the FFs 36, 38
Are reset, each becomes high level, and the AND gates 48 and 47 become conductive, so that the hold voltage of the peak hold circuit 17 is cleared at the time of CH switching, and the FF 20
Is set. Therefore, the NAND gate 25 becomes conductive. Before t _{n1 in} FIG. 3, the output of the NOR gate 43 is high →
If the counter changes from low to high, the counter 29 has been cleared. At t _n1 , the output of the NAND gate 25 becomes low level, and the counter 29 of FIG. 1 counts up by 1.
To do. The output of the NOR gate 43 is inverted by the inverter 46, and if the counter 29 is constructed as shown in FIG.
When the output of the NOR gate 43 changes from high to low, the selector 29S outputs the initial value of the memory 29M, while N
The output of the OR gate 29G becomes low level, the load terminal of the counter 29C becomes low level, and the value of the memory 29M is preset. The counter value of the value that gives a pulse width of 0.75 ms is 2587, but considering the accuracy of the polarizer, a simple value may be used, 2 ¹¹ = 2048, 2 ⁹ = 51.
The sum of 2,2 ⁵ = 32, that is, 2592 is set as an initial value. Therefore, the contents of the memory 29M are only 1 in 2 ⁴ , 2 ⁹ and 2 ¹¹ . The pulse width is 2592 x 0.2899 ms = 0.751 ms.
In this state, the output of the NAND gate 25 is added to the counter 29. However, the accuracy of changing the pulse width in the range of 0.75 to 2.25 ms may be set so that there is no practical problem. Bit increments, ie 32 × 0.2899
= 9.28 μsec increments. Therefore, the counter 29C is divided into 2 ⁵ or more and 2 ⁴ or less, and the NAND
The output of gate 25 is assumed to change the output of the 2 ^5. (I.e. ² to ⁴ may be omitted) Thus, in t _n1,
The counter 29 is set to 2592 + 32 = 2624. At the end of the first bit, the FF 30 is set at t ⁿ² . Since the width of 1 bit is 0.2899 ns, it can be ignored. At t _n3 , the output of the counter 27 becomes 2624, the coincidence output φ _n2 is output from the coincidence detection circuit 28, and the FF 30 is reset. The Q output pulse width of the FF 30 is 2624 × 0.2899 = 0.761 msec, ignoring the difference between t _{n1 and} t _n2 . Time t
_{At (n + 1) 1} , the output of the first bit from the counter 27 appears again. t _{n1 to} t _{(n + 1) 1} is 65536 × 0.2899 μs≈1
It is 9 ms, which satisfies the specifications of the polarizer widely used in the United States. At t _{(n + 1) 1} , the count 29C counts up by 1 and becomes 2624 + 32 = 2656. Therefore, t _n4 is 2656.
It is the bit and the pulse width of the Q output of FF30 is 2656 ×
0.2899 ≈ 0.770 msec. This is repeated thereafter. The maximum count is 7720, which is 7712 x 0.2899 ≈ 2.24ms. That is, 7712 = 5120 + 2592, 5120 = 160 about 270 ° is 16
The polarization plane is changed in steps of 0 and 1.7 degrees. Even if the plane of polarization deviates by 2 to 3 degrees, the signal strength at the peak point does not change so much, so a difference of ± 0.85 degrees does not matter at all. Next, after the maximum count, at t _{(n + x) 2} , the count is 29C.
Counts up and becomes 7744, the detection circuit 29A in FIG.
This is detected in the same manner as in the case where the output of the inverter 46 is added via the OR gate 29B, and the counter 29C is set to the initial value. This time, since the load terminal of the counter 29C becomes high level after t _{(n + x) 2} , the initial value of the counter 29C is 2592, and the pulse width of the Q output of FF30 is 9.3 μs narrower than the previous time. Although it varies, the optimum points of the vertical and horizontal polarization planes are between 1 and 2 ms, so an increase / decrease of 9.3 μs can be ignored. If the above operation is repeated, the pulse width of the Q output of FF30 will be expanded by about 9.3 μs in the range of about 0.75 to 2.25 ms,
This is supplied to the polarizer 2.

Next, the detection and storage of the optimum point of the plane of polarization will be described. Fourth
In the figure, it is assumed that the output of the NOR gate 43 changes from high to low to high at time T ₀ . If CH is designated (switched) at T ₁₀ following T ₀ , the positive pulse for CH switching is AND
As φ ₁₂ of FIG. 4 transmitted to the gates 48 and 47, T
It is assumed that an even CH is specified in ₁₀ . For even CH,
The AND gate 48 becomes conductive. Because FF36 is N
The output of the OR gate 43, which is reset at T ₀ ,
Because the output is high level. Therefore, AND gate 48
CH switching output appears at the output of the OR gates 49 and 50.
A pulse is output via.

In general the, CH switching, or, the power source ON or manual start, changes the output of NOR gate 43 to a low level, until the need is polarization setting, since the next CH switching is not carried out, T ₀ and CH at T ₁₀ may not perform the polarization plane set at T ₁₀ if the same even number (or the same odd number). NO
The negative pulse of the output of the R gate 43 is inverted by the inverter 46, passes through the OR gate 50, the peak hold circuit 17,
Although transmitted to the FF 20 and the counter 29, the OR gate 5
Considering an output pulse of 0, the output of the OR gate 49 and the output of the inverter 46 are the same, and therefore the setting at T ₁₀ will be described here. The output of the OR gate 50 (which is the same with the consideration of T ₀ ) is transmitted to the peak hold circuit 17, clears the hold voltage, and clears the counter 29 as described later. On the other hand, the two inputs of the NAND gate 44, that is, FF3
Since the Q of 6 and the Q of FF 38 are both low level, the output of the NAND gate 44 becomes high level, the output of the NAND gate 45 becomes negative at T ₁₀ in FIG. 4, and the FF 20 is set. It has already been described that the output of the NAND gate 25 goes low at the first bit of the counter 27 after the Q output of the FF 20 goes high. Further, at T ₁₀ , the output (positive pulse) of the OR gate 49 passes through the OR gate 50,
It is transmitted to the OR gate 29B in FIG. Therefore, the selector 29S selects the output of the memory 29M, and the counter 2
Tell 9C. On the other hand, the output of the OR gate 29B is NOR
It is inverted by the gate 29G and used as a load pulse for the counter 29C, and the counter 29C is preset to the output value of the memory 29M. From T ₁₀ (or T ₁₁ may be considered), as described above, the pulse width of the Q output of the FF 30 changes from 0.761 msec to 2.24 msec in steps of about 9.3 μs. The time during this period is 19 ms × 159≈3.02 seconds.
During this period, the output of the AGC detection circuit 16 is shown in FIG.
Change the solid line or the broken line. If it is an even-numbered channel, it becomes a broken line in FIG. 11A, and the output of the counter 27 at the point P _H is stored in memory. The value of the counter 27 at this time is 627.
If it is 2, 6272 = 2 ¹² +2 ¹¹ +2 ⁶ . or,
The pulse width at this time is 6272 × 0.2899 = 1.82 ms,
It is a value close to the standard of horizontal polarization described above. As in the conventional example,
After the peak detection, the pulse width of the Q output of the FF 30 is further widened, and when the output of the counter 29 reaches 7744, the pulse width of the Q output of the FF 30 returns to about 0.751 msec as described above. If the pulse width of the Q output of FF30 is widened from here,
A negative pulse is generated at the output of the level comparator 18 at the point P _H , and this pulse resets the FF 20 and writes the value of the counter 29 at that time into the latch memory 35. That is, since the even-numbered CH causes the AND gate 32 to conduct, the inverter 3
Since the output of 3 is low, the AND gate 34 is cut off.
When the output of the AND gate 32 rises, the latch memory 35
Write the data of the counter 29 to the
6 is set, the FF 36 becomes low level, and thereafter the AND gate 32 is cut off.
No data is written to 5 until the FF 36 is reset. In addition, the counter increment of the counter 29 is 32 = ²⁵ units, and the maximum is 7744, so 2 ¹²
Is. That is, it is sufficient to store only 8 bits of 2 ^{5 to} 2 ¹² . Similarly, the initial value is 2592 = 2 ¹¹ +2 ⁹ +2 ⁵ , and the counter 29C can be counted from 2 ⁵ ,
The counter 29C is an 8-bit counter and the first digit is 27
The comparison with the 2 ^5, the second digit as compared to the 2 ⁶ counter 27 may be similarly compare 8 digit 2 ¹² or less, fifth diagram of match detection circuit 28, the counter 29C is an 8-bit It is enough.

As described above, the data of the polarization planes of even-numbered channels were written in the memory 35 before T _{20 of} FIG. Then T
_When another even CH is specified again with ₂₀ , CH switching pulse φ
₁₁ is transmitted to the AND gates 39 and 40. FF36
Is set, the FF 38 is still reset, the AND gate 39 is turned on, the AND gate 40 is turned off, and the output of the inverter 33 is at a low level.
Outputs the B input. Therefore, as shown in FIG.
By the output of the gate 41, via the NOR gate 29G,
The output of the latch memory 35, that is, 6272 is the counter 2
It is loaded at 9C. At this time, since the FF 20 is not set, the output of the NAND gate 25 does not appear, the counter 29C does not increment, and the pulse width of the Q output of the FF 30 becomes constant (about 1.82 ms). Consider the case where an odd number CH is specified at T ₃₀ . The output of the inverter 33 becomes high level, and the AND gates 34, 40 and 47 can be conducted, and AN
The D gates 32, 39 and 48 are cut off. On the other hand, AND
Even if the gate 40 becomes conductive, the Q output of the FF 38 is at a low level, so that the gate 40 does not become conductive and the load pulse is not output from 41. The selector 42 selects the output of 37 to select the counter 2
However, it does not matter because the output of the RO gate 41 is not output and the selector 29S selects the memory 29M in FIG. On the other hand, three-input AND gate 47, FF 38 to a high, the output of inverter 33 is high, because the CH switched pulse is high, be between high levels of T ₃₀ through T _31,
Peak hold circuit 1 via OR gates 49 and 50
7, NAND gate 45, and counter 29.
The peak hold circuit 17 is cleared and the counter 29C
As described above, the initial value is set to. NAND
One side of the input of the gate 45, that is, the output of the NAND gate 44, is at a high level because the Q output of the FF 36 is high and the Q output of the FF 38 is low, and the NAND gate 45 conducts and F
F20 is set, Q output becomes high level, NA
The ND gate 25 becomes conductive, and the pulse width of the Q output of the FF 30 is changed once every 0.761 to 2.24 ms at intervals of about 9.3 .mu.s to obtain the solid curve in FIG. 11 (A). At this time, the held peak P _V is the peak-hold circuit 17, and then varying the pulse width of the Q output of FF30 from 0.751 writes the output of the counter 29 in terms of P _V. P
_When the value of the counter 27 at _V is 4128, 4128
= 2 ¹² +2 ⁵ , which is written in the latch memory 37. At this time, the output of the AND gate 34 is a positive pulse, so that the operation of writing the 2 ¹² to ²⁵ outputs of the counter 29 into the latch memory 37 is the same as that described above. Also, A
The trailing line of the output of the ND gate 34 sets the flip 38 to a low level and thereafter shuts off the AND gate 40. Further, the Q output of the FF38 becomes high level and the Q output of the FF36 has already become high level, so the output of the NAND gate 44 becomes low level and the FF is not set thereafter. Therefore, the FF20 remains reset when P _V is detected. It becomes a state. Therefore, the NAND gate 25 is cut off and the counter 29C is not incremented.

As is clear from the above description, the peak hold operation and the operation of changing the pulse width of the Q output of the FF 30 are performed until the data of both the vertical and horizontal polarization planes are written in the memory. , When the data of both polarization planes have been written, the peak hold and the change of the pulse width of the Q output of the FF 30 are not performed. In this case, the pulse width that gives P _V is 4128 × 0.2899≈1.20 ms.

When the conditions of the peak hold operation and the memory writing are arranged, for example, if the reception channel switched after the output of the NOR gate 43 changes from high → low → high is odd, the AND gate 32 becomes conductive and the data of the polarization plane of the odd channel is Is written to 35. Further, the peak hold circuit 17 is cleared by the CH switching output via the AND gate 48 and the OR gates 49 and 50, and the NAND gate 45 can be made conductive.
Set FF20 and clear the count 29C. If the first switched channel is even, the AND gate 34
Is conducted, and the data of the polarization plane of the even channel is written in the latch memory 37. Further, the peak hold circuit 17 is cleared, the FF 20 is set, and the counter 29C is cleared by the CH switching output via the AND gate 47 and the OR gates 48 and 50.

Now, after writing the polarization plane data of the even number CH in the latch memory 37, when the even number CH is designated at T ₄₀ , the contents of the latch memory 35 are preset in the counter 29C as described above. When an odd-numbered CH is designated at T ₅₀ , the AND gate 34 is cut off because the FF 38 is at a low level, and no data is written to the latch memory 37.
The gate 39 is cut off, the AND gate 40 is turned on, and C
The H switching pulse is sent to the NOR gate 2 via the OR gate 41.
Tell 9G. On the other hand, since the AND gates 47 and 48 are cut off, the CH switching pulse does not appear in the outputs of the OR gates 49 and 50. Therefore, the CH switching pulse does not appear in the output of the OR gate 29B, and the selector 29S is the data selector 42. Is transmitted to the coincidence detection circuit 28. If the selector 42 is an odd CH and the output of the inverter 33 is at a high level, the output of the latch memory 37 is transmitted to the counter 29. Therefore, the contents of the latch memory 37 are transmitted to the coincidence detection circuit 28, and the pulse of the Q output of the FF 30 is transmitted. It becomes the pulse width that gives P _V.

As described above, once both the data of the polarization planes of the odd and even CHs are stored in the memory, the pulse width corresponding to the designated CH and always providing the optimum polarization plane can be immediately set.

In FIG. 5, the output of the detection circuit 29A may slightly appear when the output of the OR gate 41 is applied to the NOR gate 29G. To prevent this, as shown in FIG. An AND gate 29D forms a logical product of the output of 29B and the output of the OR gate 41 inverted by the inverter 29F, and the NOR gate 29G and the selector 29 are formed.
All you have to do is add to S.

With the configuration as in this embodiment as described above, the input signal maximum point detection circuit and the AGC detection circuit for controlling the polarization plane can be shared.

Also, the automatic setting can be redone manually at any time.

Effects of the Invention As described above, according to the present invention, the following excellent effects can be obtained.

(1) If the polarization plane is set on a CH that has a good reception of radio waves,
The polarization plane can be set correctly even on a channel with an interfering wave.

(2) It is not necessary to reset the polarization plane every time the CH is switched.

[Brief description of drawings]

FIG. 1 is a block diagram of a main part of a satellite broadcast receiver according to an embodiment of the present invention, FIG. 2 is a spectrum diagram for explaining the operation of the present invention, and FIGS. 3 and 4 are the same time charts. Fifth
6 and 6 are block diagrams for explaining the operation of the present invention, FIG. 7 is a block diagram of a satellite broadcast receiving system, and FIG. 8 is a block diagram of a peak hold circuit for an AGC voltage for optimal setting of the polarization plane. 9 and 10 are spectrum diagrams of signals for explaining the operation, and FIG. 11 is a characteristic diagram showing the relationship between the polarization plane and the AGC voltage. 17 ... Peak hold circuit, 18 ... Level comparator,
20, 30, 36, 38 ... Flip-flops, 24 ...
... Narrow band wave filter, 25, 44, 45 ... NAND gate, 26 ... Oscillator, 27 ... Counter, 28 ... Match detection circuit, 29 ... Counter, 32, 34, 39, 4
AND gate, 43 ... NOR gate, 42 ... Selector, 41, 49, 50 ... OR gate, 35, 37 ... Latch memory, 33, 46, 31 ...
... inverter.

Claims (1)

[Claims] 1. A polarizer for selecting a polarization plane of a television signal having a vertical or horizontal polarization plane transmitted from a satellite, a low noise converter installed immediately after the polarizer, and the converter. A tuner for inputting an output, an intermediate frequency amplifier for inputting an output of the tuner, an FM detection circuit for inputting an output of the intermediate frequency amplifier, and a polarization plane control circuit for controlling a polarization plane of the polarizer. The polarization plane control circuit branches the output of the intermediate frequency amplifier and passes only a signal of a tuning channel that is input, and an AGC detection circuit that inputs the output of the band pass filter, When the tuner is tuned to a channel having a vertical (or horizontal) detection surface, the polarization plane of the detection surface is changed to change the AGC.
First storage means for storing polarization plane control data of the polarizer when the peak value of the output of the detection circuit is detected, and the tuner are tuned to a channel having a horizontal (or vertical) plane of polarization. And a second storage means for storing polarization plane control data of the polarizer when the peak value of the output of the AGC detection circuit is detected by changing the polarization plane of the polarizer. A selection means for inputting the output of the second storage means is provided, and the selection means is the first storage means or the second storage means each time the channel of the tuner is switched.
A satellite broadcast receiver characterized by outputting control data from the storage means to set the polarization plane.