JPH0644827B2 - Color signal processing circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a color signal processing circuit, and more particularly to a circuit for generating a carrier wave used for signal processing during frequency conversion operation or color demodulation operation of a carrier color signal. The present invention relates to a color signal processing circuit that can be applied to various devices including an automatic phase control circuit (APC circuit) therein.

(Prior Art) An automatic phase control circuit (APC circuit) is provided in a circuit that generates a carrier wave used for signal processing in a color signal processing circuit in a color television receiver, a color VTR, and various other devices. There is something.

If the DC gain of the APC circuit is infinite and does not include a time delay element such as a loop filter, the APC circuit will not be affected by the phase change of the reproduction color signal (reproduction low frequency conversion carrier color signal). Phase control can be performed without any time delay, but since it is impossible to configure the APC circuit as one having infinite DC gain, the residual phase is inevitable in the actual APC circuit. There is an error, and when a phase locked loop (PLL) configuration is used as the phase comparison circuit, there is a residual phase error caused by the operation principle of the PLL. The APC circuit performs APC operation at a finite response speed.

Then, the reproduction color signal (reproduction low-frequency conversion carrier color signal) includes
Normally, the S / N is deteriorated due to the inclusion of noises due to various causes. Therefore, when noise is mixed in the color burst signal extracted by the burst gate circuit of the APC circuit, even if the color burst signal extracted by the burst gate circuit is originally of the correct phase, The phase comparison circuit of the APC circuit outputs a phase error signal generated due to the presence of noise mixed in the color burst signal.

The APC circuit performs the APC operation so that the phase error signal generated corresponding to the noise mixed in the color burst signal as described above becomes zero, so that the reproduced color signal contains noise. Therefore, the phase of the reproduced color signal is changed by the operation of the APC circuit, which causes a color shift in the reproduced image.

As described above, the color shift in the reproduced image caused by the noise mixed in the color burst signal can be reduced to some extent by slowing the response speed of the APC circuit. The APC operation is carried out in the state where there exists.

However, in the case of an APC circuit configured to perform an APC operation in a state where there is a residual phase error, for example, it is possible to specify in a reproduced image by a reproduced color signal from a color VTR that causes a head striking phenomenon. A streaky color shift occurs at various positions.

The streak-like color misregistration portion generated in the reproduced image by the above-mentioned head striking is not so conspicuous when the S / N of the reproduced color signal is bad. However, for example, the frame memory or the field memory is included. When a reproduced color signal having a good S / N is obtained by using a cyclic noise reduction circuit or the like, a streak-like color shift due to the head hitting can be clearly recognized.

In order to prevent the streak-like color shift from occurring in the reproduced image even when the head is hit, the response speed of the APC circuit may be set as high as possible. When the response speed of the APC circuit is increased, the color shift that occurs in the reproduced image due to noise mixed in the color burst signal becomes a problem. Therefore, the APC circuit has been conventionally used in the state where an appropriate residual phase error exists. Since the operation is performed, it is not possible to eliminate or reduce the occurrence of streak-like color shift in the reproduced image due to the head hit.

Further, as described above, the color shift in the reproduced image caused by the noise mixed in the color burst signal can be reduced to some extent by slowing the response speed of the APC circuit. Although the APC operation is performed in the presence of the residual phase error, the APC operation is delayed as described above.
If the PC circuit causes the APC loop to be out of lock for some reason, the APC circuit will be a normal APC loop.
Color misregistration occurs in a reproduced image before returning to the operation state.

The occurrence of color misregistration due to unlocking of the APC loop in the APC circuit is caused by, for example, reproduction color signal dropout or signal-to-noise generated by repeating copying in a VTR configured to perform low-frequency conversion carrier color signal processing. The color flicker occurs at the upper part of the reproduced image due to the APC loop break occurring immediately after the vertical sync signal because the color burst signal does not exist in the vertical sync signal period. easy.

This problem can be solved by increasing the response speed of the APC circuit as much as possible. However, as described above, when the response speed of the APC circuit is increased, the noise mixed in the color burst signal causes a reproduced image. Since the color shift becomes a problem, the APC circuit is conventionally configured to perform the APC operation in the presence of an appropriate residual phase error. Therefore, it is not possible to remove or reduce the color flicker. It was difficult.

The above-mentioned problems that occur in various devices that include an automatic phase control circuit (APC circuit) in a circuit that generates a carrier wave used for signal processing during a frequency conversion operation or a color demodulation operation of a carrier color signal. In order to solve the above problem, the applicant company has previously proposed a color signal processing circuit having a configuration as illustrated in FIGS. 5 and 9.

In the proposed color signal processing circuit shown in FIG. 5 and FIG. 9, 19 is the same as the two color difference signals that should be obtained when the carrier color signal is color demodulated with two color difference axes that are orthogonal to each other. Of the two color difference signals having different signal forms (in the following description, the red color difference signal R-
(Described as the Y signal), and 20 are two color difference signals to be obtained when the carrier color signal is color demodulated by the two orthogonal color difference axes. It is an input terminal of digital data of the other color difference signal (which is described as a blue color difference signal BY signal) of the two color difference signals having the same signal form.

In the proposed color signal processing circuits shown in FIGS. 5 and 9, 21, 25 and 26 are dividers, 27 is an adder, 29 is a burst gate circuit, 31 and 33 are subtractors, 32 is a feedback coefficient circuit, 38 and 39 are multipliers, 34 is a frame memory (or field memory), 22 to 24, 28, 3
Reference numerals 6 and 37 are arithmetic circuits, 40 and 41 are output terminals, and 30 and 35 are subtractors in FIG.
In FIG. 9, 62 is a subtracter and 63 is a non-linear signal processing circuit.

In the proposed color signal processing circuit shown in FIGS. 5 and 9, assuming that the carrier color signal whose amplitude is A and whose phase is θ is input to the input terminal 19 and is demodulated on two orthogonal color difference axes. Two color difference signals Asinθ and Acosθ
One of the digital data of the two color difference signals (the RY signal and the BY signal) having the same signal form is supplied with the digital data of the color difference signal RY signal.
Two color difference signals Asinθ and Ac that should be obtained when the carrier color signal whose amplitude is A and whose phase is θ are demodulated on the two color difference axes orthogonal to each other at the input terminal 20.
Two color difference signals (RY) having the same signal form as osθ
Signal and BY signal), the other color difference signal BY signal digital data is supplied.

In the already proposed color signal processing circuit shown in FIGS. 5 and 9, the digital data of the RY signal is divided by the divider 21.
To the divider 21, and the digital data of the BY signal is supplied to the divider 21 as a divisor. Therefore, in the divider 21, Asinθ / Acosθ = tanθ
Is output, data corresponding to the quotient tan θ obtained as a result of the division is output, and the data is supplied to the arithmetic circuit 22.

The arithmetic circuit 22 outputs color phase θ data from the tan θ data supplied thereto and supplies it to the burst gate circuit 29 and the subtractor 35. The data of the color phase θ output from the arithmetic circuit 22 is calculated by the arithmetic circuit 2.
3 and 24, the arithmetic circuit 23 described above supplies the data of the color phase θ supplied thereto to the divider 25 as data of sin θ, and the arithmetic circuit 24 described above The supplied color phase θ data is supplied as a divisor to the divider 26 as cos θ data.

The BY = Acosθ digital data supplied to the input terminal 20 is given to the divider 26 as a dividend, and the divider 26 calculates Acosθ / cosθ to output the data of the color amplitude A, It is supplied to the adder 27.

Further, the digital data of RY = Asinθ supplied to the input terminal 19 is given to the divider 25 as a dividend, and the divider 25 performs the calculation of Asinθ / sinθ to output the data of the color amplitude A. And supplies it to the adder 27.

Since the data of 2A is output from the adder 27, the data is halved by the arithmetic circuit 28 to be the data of the color amplitude A, and the data of the color amplitude A is multiplied by the multipliers 38 and 39.
Is supplied to.

In the previously proposed color signal processing circuit shown in FIGS. 5 and 9 described above, color burst signal data is stored in a specific portion of each color difference signal supplied to the input terminals 19 and 20 during each horizontal blanking period. By including the above, it is possible to output the phase data of the color burst signal from the arithmetic circuit 22 in correspondence with a specific portion in each horizontal blanking period of the color difference signal.

Next, FIG. 12 shows the generation of the data of the color amplitude A which is different from the means for generating the data of the color amplitude A and the means for generating the data of the color phase θ described above with reference to FIGS. 5 and 9. FIG. 12 is a block diagram showing the means and the means for generating the data of the color phase θ, in which the carrier color signal (amplitude A, phase θ) is color demodulated at 19 in FIG. 12 with two color difference axes orthogonal to each other. One of the two color difference signals having the same signal form as that of the two color difference signals to be obtained (in the following description, the red color difference signal RY signal =
Asinθ) digital data input terminal, and 20 is the same as the two color difference signals that should be obtained when the carrier color signal is color demodulated by the two color difference axes that are orthogonal to each other. The other color difference signal of the two color difference signals having different signal forms (in the following description, it is assumed that the blue color difference signal BY signal = Acos θ).
This is an input terminal for digital data of. In the following description, the digital data supplied to the input terminals 19 and 20 is assumed to be data in 2's complement.

The digital data of the color burst signal is present at a specific position during the horizontal blanking period of at least one of the color difference signals in the digital data of the color difference signals supplied to the input terminals 19 and 20, respectively. Has been made.

Further, reference numerals 21, 22, 25, 26, 55 denote arithmetic circuits, 2
7, 46 are adders, 42, 43 are absolute value circuits, 44 is a polarity inverting circuit, 45, 51-53, 56 are changeover switches,
47 and 48 are signal generation circuits, 49 and 50 are logic 0 value detection circuits, and 54 is an OR circuit.

In FIG. 12, RY supplied to the input terminal 19
The coded bit of the digital data of the signal is the absolute value circuit 42.
And the encoded bits of the digital data of the BY signal supplied to the input terminal 20 are supplied to the absolute value circuit 43 and the signal generation circuits 47 and 48.

In the arithmetic circuit 21 to which the output data Asinθ from the absolute value circuit 42 is supplied as the dividend signal, the arithmetic circuit 22 obtains the data of tan θ obtained by performing the arithmetic operation using the output data Acosθ from the absolute value circuit 43 as the divisor signal. Give to.

The arithmetic circuit 22 outputs the data corresponding to the color phase θ from the data of tan θ supplied thereto, and supplies the data to the fixed contact L of the changeover switch 47 and the polarity reversing circuit 44. In the polarity reversing circuit 44, the color phase θ data supplied thereto is supplied to the fixed contact H of the changeover switch 45 as −θ data.

The movable contact v of the changeover switch 45 is fixed to the fixed contact L according to the changeover control signal output from the signal generating circuit 47.
And the fixed contact H are switched to each other. The mode of the switching is as follows when the control output described in the column of "control output to switch 45" in FIG. 13 is in the low level state L. The movable contact v of the changeover switch 45 is switched to the fixed contact L side, and the control output described in the column of "Control output to switch 45" in FIG. 13 is in the high level state H. At this time, the movable contact v of the changeover switch 45 is switched to the fixed contact H side.

The signal generating circuit 47 described above has the input terminal 1
The high-level state H and the low-level state L of the code bit in the digital data of the RY signal supplied from 9 and the code in the digital data of the BY signal supplied from the input terminal 20. Depending on the combination of the high level state H and the low level state L of the bit, the control output as described in the section "Control output to the switch 45" in FIG. 13 is switched. 45 can be supplied as a switching control signal.

The phase angles of 0 ° and 180 ° described in the column of “Output to adder 46” in FIG. 13 are R− supplied to the signal generating circuit 47 from the input terminal 19.
A high-level state H and a low-level state L of the sign bit in the digital data of the Y signal, and a high-level state H of the sign bit in the digital data of the BY signal supplied thereto from the input terminal 20. The phase of the signal to be supplied to the adder 46, which will be described later, is shown according to the combination with the low level state L.

The data of the color phase θ output from the arithmetic circuit 22 is supplied to the polarity reversing circuit 44, the changeover switch 45, the signal generating circuit 47, the adder 46, the changeover switch 51, and the signal generating circuit 48 which will be described later. , The signal processing circuit including the logical zero value detection circuits 49, 50, and the like performs predetermined signal processing and then outputs the signal. In the data of tan θ input to the arithmetic circuit 22, θ is 0 °. Although the angle from 0 to 360 ° is indicated, θ in the data of tan θ input to the arithmetic circuit 22 is 0.
It is based on the fact that it is possible to calculate only for angles from 90 ° to 90 °.

That is, the data of the color phase θ output from the arithmetic circuit 22 is the polarity inversion circuit 44, the changeover switch 45, the signal generating circuit 47, the adder 46, the changeover switch 51, and the signal generating circuit 48 which will be described later. When the data of tan θ input to the arithmetic circuit 22 is an angle from 0 ° to 90 ° by the signal processing circuit configured by the detection circuits 49, 50, etc. of the logic 0 value, the arithmetic circuit 22 outputs the data. The data of the calculated color phase θ is output as it is as the data of the color phase, and when the data of tan θ input to the arithmetic circuit 22 is an angle of 90 ° to 180 °, the data is output from the arithmetic circuit 22. Further, the data of tan θ input to the arithmetic circuit 22 may be 180 ° so that the data of the obtained color phase θ becomes 180 ° −θ data and is output as the data of the color phase. In the case of an angle from 270 ° to 270 °, the data of the color phase θ output from the arithmetic circuit 22 is converted into the data of 180 ° + θ and output as the data of the color phase. The input tan θ data is θ from 270 ° to 360 °
In the case of the angles up to, the data of the color phase θ output from the arithmetic circuit 22 is converted to the data of −θ and is output as the data of the color phase.

The data of the color phase θ output from the arithmetic circuit 22 described above is moved by the switching control signal as shown in the section of “Control output to the switch 46” from the signal generation circuit 47 described above. It is supplied to the adder 46 as the data of the color phase θ or the data of the color phase −θ via the changeover switch 45 whose contact point v is changed.

Since the adder 46 is supplied with the phase data as shown in the column of "output to the adder 46" in FIG. 13 from the signal generating circuit 47, the adder 46 outputs the phase data to it. The sum of the two supplied data is output and applied to the fixed contact of the changeover switch 51.

Further, data of phase 0 ° is supplied to the fixed contact of the changeover switch 51, data of phase 90 ° is supplied to the fixed contact, data of phase 180 ° is supplied to the fixed contact, and data of the fixed contact is supplied to the fixed contact. Is supplied with phase 270 ° data.

The logic 0 value detection circuit 49 to which the output data from the absolute value circuit 42 is supplied and the logic 0 value detection circuit 50 to which the output data from the absolute value circuit 43 is supplied are input to it. When the value of the digital data is a logical 0 value, the output in the high level state is supplied to the signal generating circuit 48.

Further, in the signal generation circuit 48, the sign bit of the RY signal supplied to the input terminal 19 and the input terminal 2 are input.
The sign bit of the BY signal which is supplied to 0 is also supplied, and this signal generation circuit 48 is shown in the output column in FIG. 14 by the combination of the above-mentioned four data supplied to it. A switching control signal for switching the movable contact v of the changeover switch 51 is generated so that the selected output can be output from the changeover switch 51.

In FIG. 14, H indicates a high level signal, L indicates a low level signal, and X indicates an arbitrary level signal.

The data output from the movable contact of the changeover switch 51 is output as the color phase θ data.

Since the data of the color phase θ output from the movable contact of the changeover switch 51 is also supplied to the arithmetic circuits 23 and 24, the arithmetic circuit 23 outputs the data of which absolute value is sinθ to the arithmetic circuit 25. The arithmetic circuit 24 supplies data having an absolute value of cos θ to the arithmetic circuit 26 as a divisor signal.

Since the arithmetic circuit 25 is supplied with the digital data of the RY signal as the dividend from the above-mentioned absolute value circuit 42, the arithmetic circuit 25 performs the calculation of Asinθ / sinθ so that the arithmetic circuit 25 outputs the color amplitude A Is output and given to the fixed contact L of the changeover switch 52.

Further, since the arithmetic circuit 26 is supplied with the digital data of the BY signal from the absolute value circuit 43 described above as the dividend, Acos θ / cos in the arithmetic circuit 26 is calculated.
By the calculation of θ, the data of the color amplitude A is output from the arithmetic circuit 26 and given to the fixed contact L of the changeover switch 53.

The fixed contact H of each of the changeover switches 52 and 53 described above
Data corresponding to 0 is supplied. The switching state of the movable contact v of the changeover switch 52 is controlled by the output data of the detection circuit 49 having a logical 0 value, and the movable contact v of the changeover switch 53 is changed to the logical 0.
The switching state is controlled by the output data of the value detection circuit 50.

The output data of the logical zero value detection circuits 49 and 50 are also used for the switching control of the movable contact v of the changeover switch 56, which will be described later, via the OR circuit 54.

The data of the color amplitude A output from the movable contact v of the changeover switch 52 is added by the adder 27, and then supplied to the fixed contact L of the changeover switch 56 and also to the arithmetic circuit 23. The data of the color amplitude 2A doubled by the arithmetic circuit 55 is supplied to the fixed contact H of the changeover switch 56.

Then, the data of the color amplitude 2A is output from the movable contact v of the changeover switch 56.

In the already proposed color signal processing circuit shown in FIGS. 5 and 9, the color phase θ output from the arithmetic circuit 22 during a part of a specific period during the horizontal blanking period in the color difference signal.
Is the data of the phase θ ′ of the color burst signal existing during the horizontal blanking period of the color difference signal.

As the burst gate circuit 29 to which the color phase data output from the arithmetic circuit 22 is supplied, for example, a latch circuit can be used, and a color difference signal can be supplied to the latch circuit 29 used as the burst gate circuit 29. When a burst gate pulse is applied at an intermediate time position of the color burst signal period existing during the horizontal retrace erasing period, the burst gate circuit 29 causes the color phase data latched at the burst gate time position described above. That is, the data of the phase θ ′ of the color burst signal existing during the horizontal blanking period in the color difference signal is output for one horizontal scanning period until the next burst gate pulse is applied to the burst gate circuit 29. Will continue.

By the way, as is well known in the color television technology, in order to demodulate a color signal from a carrier color signal obtained by so-called quadrature two-phase modulation of a color subcarrier with I, Q signals and two color difference signals, color synchronization is required. A signal for is needed,
For example, it is designed to be inserted as a color burst signal during the horizontal blanking period and transmitted. The color burst signal is generated integrally with the carrier color signal and transmitted together with the carrier color signal. Instead, the signal having the reference phase in the carrier color signal is bursted and separately inserted and transmitted during the horizontal blanking period in the composite color video signal (for example, the back porch of the horizontal synchronizing signal).

Further, the color difference signal obtained by performing the color demodulation of the above-mentioned carrier color signal does not have a color burst signal. Therefore, as described above, the horizontal difference of the color difference signal supplied to the input terminals 19 and 20 is obtained. The signal in the state where the color burst signal is present during a part of the blanking period is a phase reference during a part of the horizontal blanking period of the color difference signal. Means that the color burst signal is inserted.

As described above, the color burst signal is a signal used as the phase reference of the carrier color signal, and it has been conventionally known to know the state of the transmission system from the change state of the phase of the color burst signal.

The data of the phase θ'of the color burst signal output from the burst gate circuit 29 corresponds to the residual phase error generated in the color difference signal due to the APC operation of the APC circuit provided in the preceding circuit, for example. Utilizing the fact that the data has a residual phase error, the proposed color signal processing circuit shown in FIG. 5 outputs the data of the phase θ ′ of the color burst signal output from the burst gate circuit 29. The signal of the predetermined angle (180 ° in the example) is supplied to the subtractor 30 and subtracted by the predetermined angle (180 ° in the example) in the subtractor 30 so that the signal of the predetermined angle (180 ° in the example) is used as a reference. As
The subtractor 30 which described how much the phase shift has occurred
I'm trying to get it from the output.

That is, the output obtained from the subtractor 30 is, for example, a small numerical value of the phase shift amount signal Δθ corresponding to the residual phase error generated in the color difference signal due to the APC operation of the APC circuit provided in the preceding circuit. Because
It goes without saying that the calculation performed in the subsequent signal processing circuit can be easily performed with a small numerical value.

The data of the phase shift amount signal corresponding to the residual phase error of the color burst signal output from the subtractor 30 is supplied to the subtractors 31 and 33 as a minuend signal. That is, the data of the phase shift amount signal corresponding to the residual phase error of the color burst signal output from the subtractor 30 is data in which noise is mixed in the color burst signal. A known phase noise reduction circuit (noise reducer) composed of the subtractors 31 and 33, the feedback coefficient circuit 32, and the frame (or field) memory 34 represents a residual phase error of a color burst signal in a noise-free state. The phase shift amount digital data Δθ is supplied to the subtractor 35, and in the already proposed color signal processing circuit shown in FIG. 9, it is extracted by the burst gate circuit 29 as a generation circuit of the difference signal data of the color burst signal. Corresponds to the difference between the current color burst signal phase θ ′ and the average of the past color burst signal phases. It is supplied to the non-linear signal processing circuit 63 the difference signal data from the subtractor 31.

A circuit arrangement that is configured by the subtractors 31 and 33, the feedback coefficient circuit 32, and the frame (or field) memory 34, and has the same configuration as that of a known cyclic noise reduction circuit (noise reducer). Then, since the data supplied thereto has a high correlation in successive frames (or fields), the feedback rate of the feedback coefficient circuit 32 is about 90% as shown by the straight line in FIG. Such high feedback rates may be employed. In FIG. 6, the horizontal axis is the frame difference input and the vertical axis is the output. In addition, 45 in FIG.
The straight line shown by the dotted line inclined at ° shows the characteristics when the feedback ratio is 100% for reference.

First, in the proposed color signal processing circuit shown in FIG. 5, the data of the phase shift amount signal representing the residual phase error of the color burst signal output from the subtractor 30 is subtracted by the subtracters 31, 33. Is supplied as a minuend signal. The part constituted by the subtractors 31 and 33, the feedback coefficient circuit 32, and the frame (or field) memory 34 has the same configuration as that of a known cyclic noise reduction circuit (noise reducer). In the part, noise is removed from the data of the phase shift amount signal representing the residual phase error of the color burst signal output from the subtractor 30.

7 and 8 are diagrams for explaining the operation of the phase shift amount data generation circuit described above. FIG. 7 shows the phase shift amount data when the influence of the head strike does not occur in the reproduced color signal. FIG. 8 is a diagram exemplifying the data in each part of the generation circuit so that it can be visually understood, and FIG. 8 is a circuit for generating the phase shift amount data when the influence of the head hitting occurs in the reproduced color signal. It is the figure which illustrated so that the data in each part inside could be understood visually.

Each of (a) in FIGS. 7 and 8 indicates the residual phase error of the color burst signal having the phase θ ′ of the color burst signal supplied from the subtractor 30 to the subtractors 31 and 33 for each horizontal scanning period. The data of the digital data Δθ of the phase shift amount is shown, and each (b) in FIGS. 7 and 8 is supplied from the subtractor 33 to the subtractor 35 for each horizontal scanning period. Data Δ of the phase shift amount digital data Δθ that represents the residual phase error of the color burst signal with the noise of the color burst signal removed
shows θ.

The digital data Δθ of the phase shift amount corresponding to the phase shift amount of the color burst signal for each one horizontal scanning period described above.
Is the data of the phase of the color burst signal from which the non-correlated information components (noise) between successive frames (or fields) have been removed. Each of these is 1 by the APC operation of the APC circuit provided in the preceding circuit. It is the digital data Δθ of the phase shift amount that represents the residual phase error that has occurred in the color burst signal for each horizontal scanning period.

Therefore, in the subtractor 35 to which the digital data Δθ of the phase shift amount representing the residual phase error generated in the color burst signal for each one horizontal scanning period is supplied as the subtraction signal, the subtracter 35 outputs from the arithmetic circuit 22 described above. Each one done
From the phase of the color difference signal for each horizontal scanning period and the phase of the color burst signal, the digital data Δθ of the phase shift amount representing the residual phase error generated in the color burst signal for each horizontal scanning period is subtracted, and the preceding circuit The arithmetic circuit 36 outputs the digital data of the color phase from which the residual phase error included in the color difference signal and the color burst signal is removed by the APC operation of the APC circuit provided therein.
Supply to 37. Each (c) in FIG. 7 and FIG. 8 shows the digital data of the color phase of the color burst signal output from the subtractor 35.

The arithmetic circuit 36 calculates the digital data of the color phase supplied thereto and the sine function and supplies the output data to the multiplier 38, and the arithmetic circuit 37 calculates the color supplied to it. The digital data of the phase and the cosine function are calculated and the output data is supplied to the multiplier 39.

As described above, the multipliers 38 and 39 have the color amplitude A
, The color difference signal R-Y from which a large phase fluctuation has been removed is supplied from the multiplier 38.
The signal is output to the output terminal 40, and the multiplier 39 outputs the color-difference signal BY signal in the state in which large phase fluctuation is removed to the output terminal 41.

By using the proposed color signal processing circuit shown in FIG. 5, it is possible to easily obtain a color difference signal from which the residual error contained in the color signal is removed by the APC operation of the APC circuit. .

Next, in the already proposed color signal processing circuit shown in FIG.
The non-linear signal processing circuit 63 described above uses the difference signal data supplied thereto, that is, the burst gate circuit 2.
Phase θ ′ of the current color burst signal extracted at 9
And a data output from the subtractor 31, that is, an output that changes non-linearly according to the magnitude of the difference signal data corresponding to the difference from the average value of the phase of the past color burst signal, The output is supplied to the subtractor 62 as a subtraction signal.

The non-linear signal processing circuit 63 is, for example, the first
The one having the input / output characteristics as shown in FIG. 0, that is, the output holds the state of zero and is supplied as the input until the phase of the frame difference supplied as the input reaches + P1 and −P2. The phase of the frame difference is +
When P1 and -P2 are exceeded, a nonlinear signal processing circuit 63 having an input / output characteristic such that an output having a size substantially equal to the size of the input indicating the phase of the frame difference can be supplied to the subtractor 62 as a subtraction signal can be used. .

The phase states of the signals of the respective parts in the already proposed color signal processing circuit shown in FIG. 9 are as illustrated in FIG.

The burst gate circuit 29 shown in FIG. 9 is shown in FIG.
11 shows an example of the state of change on the time axis of the phase θ'of the current color burst signal output from FIG. 11, and FIG. 11B shows the past color burst signal output from the frame memory 34. 11 shows an example of the state of change of the average value of the phase of the above on the time axis. Furthermore, FIG. 11 (c) shows the output from the subtractor 31, that is, the current output from the burst gate circuit 29. This is an example of the state of change on the time axis of the phase obtained by subtracting the average value of the phases of the past color burst signals output from the frame memory 34 from the phase θ ′ of the color burst signal.

The phase data shown in (c) of FIG. 11, that is, the frame difference data of the phase of the color burst signal is transferred to the nonlinear signal processing circuit 63 having the input / output characteristics as shown in FIG. When input, the nonlinear signal processing circuit 63 outputs phase data as shown in (d) of FIG. 11, which is supplied to the subtractor 62 as a subtraction signal.

Since the color phase signal including the color burst signal having the phase as shown in FIG. 11A is supplied to the subtractor 62 as the minuend signal, the subtractor 62 uses the color phase signal shown in FIG. Data obtained by subtracting the subtrahend signal shown in FIG. 11D from the subtrahend signal shown in FIG. 11A is supplied to the arithmetic circuits 36 and 37.

The arithmetic circuit 36 calculates the digital data of the color phase supplied thereto and the sine function and supplies the output data to the multiplier 38, and the arithmetic circuit 37 calculates the color supplied to it. The digital data of the phase and the cosine function are calculated and the output data is supplied to the multiplier 39.

As described above, the multipliers 38 and 39 have the color amplitude A
, The color difference signal R-Y from which a large phase fluctuation has been removed is supplied from the multiplier 38.
The signal is output to the output terminal 40, and the multiplier 39 outputs the color-difference signal BY signal in the state in which large phase fluctuation is removed to the output terminal 41.

It is obvious that by using the already proposed color signal processing circuit shown in FIG. 9, it is possible to easily obtain a color signal which can significantly reduce the color flicker which has been a problem in the reproduced image.

(Problems to be Solved by the Invention) As is apparent from the above description of the already proposed color signal processing circuit made with reference to FIG. The problems such as color shift and color flicker that occur in a reproduced image due to the presence of residual error in the APC circuit provided in the circuit and the low response speed of the APC operation have been successfully solved. In the color signal processing circuit, (1) noise in the digital data of the phase shift amount representing the residual phase error of the color burst signal is removed, or (2) the burst gate circuit 2
Phase θ ′ of the current color burst signal extracted at 9
And a circuit arrangement used to generate difference signal data corresponding to the difference between the average value of the phase of the past color burst signal, that is, a frame (or field) memory 34 and subtractors 31, 33. And the number of feedback factors 3
The circuit arrangement configured to have the same configuration as the known number of times of noise reduction (noise reducer) using 2 and 2 can sufficiently obtain the effect intended by the color signal processing circuit described above. In this case, since a feedback coefficient circuit 32 having a high feedback rate is used, for example, a color signal processed by a color signal processing circuit from a signal source whose color signals are different from each other. The color burst signal phase of the color signal supplied to the color signal processing circuit from the new signal source is changed to the color burst signal of the color signal previously supplied to the color signal processing circuit. When the phase changes significantly with respect to the phase, it takes a relatively long time until the state of the reproduced image becomes normal.

That is, difference signal data corresponding to the difference between the phase θ ′ of the current color burst signal extracted by the burst gate circuit 29 provided in the color signal processing circuit and the average value of the phases of the past color burst signals. The circuit arrangement used to generate the noises, that is, the frame (or field) memory 34, the subtractors 31 and 33, and the feedback coefficient number 32 are used to make a known cyclic noise reduction number (noise reducer). The circuit arrangement configured as in the same configuration form as the operation for generating difference signal data corresponding to the difference between the phase θ ′ of the current color burst signal and the average value of the phases of the past color burst signals. However, since it operates so as to show the flyhole effect for the input color burst signal, the signal processing of the color signal processing circuit is performed as described above. The target color signal is switched to that from a different signal source, and the phase of the color signal color burst signal supplied to the color signal processing circuit from the new signal source is supplied to the color signal processing circuit by then. The difference between the phase of the color burst signal supplied at the present time and the average value of the phases of the past color burst signals is small when the phase of the color burst signal of the color signal has changed significantly. Since it takes a long time to do so, the phase of the color signal whose phase is corrected with reference to the signal generated by the color signal processing circuit is greatly shifted over a long period of time. Therefore, it takes a relatively long time for the reproduced image to be in a normal state, and a solution to the problem has been sought.

(Means for Solving the Problems) According to the present invention, the phase data of the carrier color signal is generated based on the two color difference signals obtained when the carrier color signal is subjected to color demodulation with two color difference axes orthogonal to each other. Phase data generating means, a memory capable of storing the phase data of the color synchronizing signal period generated by the phase data generating means described above in the color synchronizing signal period as an integer multiple of the vertical scanning period, an arithmetic circuit, and a high feedback rate. A means for generating average value data, which is supplied to a cyclic digital filter configured to include a feedback coefficient circuit, to obtain average value data of phase data in the past color synchronization signal period, and the average value data described above. Comparison of the phase data comparing means for comparing the average value data of the phase data of the past color synchronizing signal period generated by the generating means with the phase data of the current color synchronizing signal period, and the above-mentioned phase data The first counting means for counting the number of pieces of data whose comparison result in the means shows a difference of a predetermined size or more for each vertical scanning period, and the count value of the first counting means are predetermined. And a number of vertical scanning periods exceeding the predetermined number continuously exceed a predetermined number, the color signal comprising means for changing the feedback coefficient of the feedback coefficient circuit of the digital filter to decrease. A processing circuit, phase data generating means for generating phase data of the carrier color signal based on the two color difference signals obtained when color demodulating the carrier color signal with two color difference axes orthogonal to each other, and color synchronization The phase data in the color synchronization signal period generated by the phase data generating means in the signal period includes a memory capable of storing a signal having an integral multiple of the vertical scanning period, an arithmetic circuit, and a feedback coefficient circuit having a high feedback rate. Means for generating average value data, which is supplied to the configured cyclic digital filter to obtain average value data of phase data in the past color synchronization signal period, and the past value generated by the means for generating average value data. The comparison result of the phase data comparing means for comparing the average value data of the phase data of the color synchronizing signal period with the phase data of the current color synchronizing signal period and the comparison result of the phase data comparing means has a predetermined magnitude. The first counting means for counting the number of data indicating the above difference for each vertical scanning period and the number of vertical scanning periods in which the count value of the first counting means exceeds a predetermined number. When the number exceeds a predetermined number continuously,
And a means for changing the feedback coefficient of the feedback coefficient circuit of the digital filter so as to decrease, a memory capable of storing a signal of an integral multiple of the vertical scanning period, an arithmetic circuit, and a feedback coefficient circuit having a high feedback rate. (EN) A color signal processing circuit provided with means for generating a phase shift amount signal representing a residual phase error in a color synchronization signal period from a configured cyclic digital filter.

(Operation) From the phase data generating means capable of generating the phase data of the carrier color signal based on the two color difference signals obtained when the carrier color signal is color-demodulated by two color difference axes orthogonal to each other, The data of the color synchronization signal period is obtained and supplied to a cyclic digital filter including a memory capable of storing a signal of an integral multiple of the vertical scanning period, an arithmetic circuit, and a feedback coefficient circuit having a high feedback ratio. Then, the average value data of the past color phase signals is obtained.

The average value data of the past color phase signals generated by the average value data generating means is compared with the data of the color phase signals based on the current color synchronization signal to show a difference of a predetermined magnitude or more. The number of data is counted for each vertical scanning period.

The count value in each vertical scanning period exceeds the predetermined number.When the number in the vertical scanning period continuously exceeds the predetermined number, the feedback coefficient of the feedback coefficient circuit of the digital filter described above. To improve the responsiveness.

(Embodiment) Hereinafter, specific contents of the color signal processing circuit of the present invention will be described in detail with reference to the accompanying drawings. 1 and 4 are block diagrams of different embodiments of the color signal processing circuit of the present invention, and FIGS. 2 and 3 are block diagrams of control circuits having different configurations.

The color signal processing circuit of the present invention shown in FIG.
The output data of the subtracter 31 in the already proposed color signal processing circuit described with reference to the drawing is supplied to the control circuit 1, and the feedback coefficient of the feedback coefficient circuit 32 is generated by the control signal generated by the control circuit 1. FIG. 4 is a block diagram of an embodiment of a color signal processing circuit in the case of changing
The color signal processing circuit of the present invention shown in the figure supplies the output data of the subtracter 31 in the already proposed color signal processing circuit described with reference to FIG. FIG. 2 is a block diagram of an embodiment of a color signal processing circuit in the case where the feedback coefficient of the feedback coefficient circuit 32 is changed by the control signal generated by the control circuit 1, and in the following description, FIG. In the color signal processing circuit of the present invention shown in FIG. 4, detailed description of the same components as the already proposed color signal processing signal described with reference to FIGS. 9 and 5 will be omitted. .

In the color signal processing circuit of the present invention shown in FIGS. 1 and 4, the frame (or field) memory 34 is used.
The circuit arrangement configured by using the subtractor 31, 33 and the feedback coefficient circuit 32 to have a configuration similar to that of a known cyclic noise reduction circuit (noise reducer) is the color signal processing shown in FIG. In the circuit, a difference signal corresponding to the difference between the phase .theta. 'Of the current color burst signal extracted by the burst gate circuit 29 and the average value of the phases of the past color burst signals as the generation circuit of the difference signal data of the color burst signal. Data from the subtractor 31 to the non-linear signal processing circuit 63
In addition, in the already proposed color signal processing circuit shown in FIG. 4, the subtractor 33 subtracts the data of the phase shift amount Δθ that generates the digital data of the phase shift amount corresponding to the phase shift amount of the color burst signal. Although it is supplied as a subtraction signal to the multiplier 35, a well-known cyclic noise reduction circuit (noise reducer) using the frame (or field) memory 34, the subtractors 31, 33 and the feedback coefficient circuit 32 described above.
The feedback coefficient in the feedback coefficient circuit 32 in the circuit arrangement configured as a configuration similar to that of the control circuit 1
It is adapted to be changed by a control signal supplied from the output terminal b to the feedback coefficient circuit 32.

In the control circuit 1 described above, the data supplied from the subtractor 31 to the input terminal a, that is, the comparison value of the average value data of the past color phase signal and the data of the color phase signal based on the current color synchronization signal is The first counting means for counting the number of pieces of data showing a difference equal to or larger than a predetermined size for each vertical scanning period, and the count value of the first counting means described above exceed the predetermined number. When the number of vertical scanning periods exceeds a predetermined number, a control signal for reducing the feedback coefficient of the feedback coefficient circuit of the digital filter is generated, and the control signal is output from the output terminal b to the feedback coefficient circuit 32. Is provided as a control signal for controlling the feedback coefficient of the feedback coefficient circuit 32.

2 and 3 show a configuration example of a control circuit configured to have the above-mentioned functions. First, in the control circuit 1 shown in FIG. 2, the output data of the subtractor 31 supplied to the input terminal a of the control circuit 1 is converted into an absolute value by the absolute value circuit 2 and given to the comparator 3.

In the comparator 3 described above, the preset reference value α and the data supplied from the absolute value circuit 2 are compared, and the data supplied from the absolute value circuit 2 is more than the reference value α. An output signal in the case of being large is given to the monostable multivibrator 4 as a trigger signal.

The pulse generated by the monostable multivibrator 4 is counted by the counter 5, and the count value of the counter 5 is supplied to the comparator 6. Since the counter 5 is reset by the signal VD of the vertical scanning period, the count value supplied from the counter 5 to the comparator 6 is one for each vertical scanning period.

The comparator 6 compares the preset reference value β with the count value given by the counter 5, and the count value supplied from the counter 5 is more than the reference value β. When it is large, the high-level output signal is given to the monostable multivibrator 7 as a trigger signal, and is also given to the monostable multivibrator 9 via the inverter 8 as a trigger signal.

The output pulse from the monostable multivibrator 7 is given as a counted pulse to the counter 10, and the output pulse from the monostable multivibrator 9 is supplied to the counter 1.
0 is given as a reset signal.

Therefore, the count value in the counter 10 is set to a value corresponding to the number of vertical scanning periods in which the output pulse from the monostable multivibrator 7 is continuously supplied to the counter 10.

The count value of the counter 10 is supplied to the comparator 11 and compared with the reference value γ preset in the comparator 11. The comparator 11 sends a high-level output signal to the output terminal b when the count value supplied from the counter 10 is larger than the reference value γ preset in the comparator 11.

As described above, in the control circuit 1 shown in FIG.
The data supplied from 1 to the input terminal a, that is, the comparison value of the average value data of the past color phase signal and the data of the color phase signal based on the current color synchronization signal is equal to or larger than a predetermined value. The control signal can be sent to the output terminal b when the number of the data indicating the number of data is continuously appearing for a predetermined number of consecutive vertical scanning periods.

Next, in the control circuit 1 shown in FIG. 3, the output data of the subtractor 31 supplied to its input terminal a is
The absolute value is converted into an absolute value by the absolute value circuit 2 and given to the comparator 3. In the comparator 3, the reference value α preset therein is compared with the data supplied from the absolute value circuit 2, An output signal when the data supplied from the absolute value circuit 2 is larger than the reference value α is given to the monostable multivibrator 4 as a trigger signal.

The pulse generated by the monostable multivibrator 4 is converted into parallel data by the serial-parallel converter 12.
The continuous n-digit output corresponding to the predetermined number n in the serial-parallel converter 12 is supplied to the AND circuit 13, and the serial-parallel converter 12 outputs the signal VD of the vertical scanning period.
Since it is reset by the AND circuit 13, the high-level output is output from the AND circuit 13 in the vertical scanning period while the monostable multivibrator 4 outputs n or more pulses. Of the AND circuit 13 and the output from the AND circuit 13 is supplied to the reset terminal of the serial-parallel converter 15 via the inverter 14.

The serial-parallel converter 15 described above is the AND circuit 13 described above.
When the output of the AND circuit 13 takes in the high level state as data and is reset when the output of the AND circuit 13 is in the low level state, it corresponds to the predetermined number m in the serial-parallel converter 15. The control signal in a high level state is output to the output terminal b from the output side of the AND circuit 16 to which the continuous m-digit output is supplied during each vertical scanning period of the continuous predetermined number m. The above-mentioned monostable multivibrator 4 outputs a predetermined n or more pulses, that is, the subtractor 31.
The data supplied from the input terminal a to the input terminal a, that is, the comparison value of the average value data of the past color phase signal and the data of the color phase signal based on the current color synchronization signal is equal to or larger than a predetermined value. This is the case where the number of data shown is continuously appearing over a predetermined number of consecutive vertical scanning periods.

As described above, the high level output signal sent from the output terminal b is the difference between the phase θ ′ of the current color burst signal extracted by the burst gate circuit 29 and the average value of the phases of the past color burst signals. Known circuit type noise mitigation using a circuit arrangement used for generating difference signal data corresponding to, i.e., frame (or field) memory 34, subtractors 31, 33 and feedback coefficient circuit 32. The feedback coefficient of the feedback coefficient circuit 32 in the circuit arrangement configured as the same configuration as the circuit (noise reducer) is set to zero (or a small value).
Then, the circuit arrangement described above is operated so that the difference signal output from the subtractor 31 of the circuit arrangement becomes a small value within a short time.

Therefore, when the color signal targeted for signal processing in the color signal processing circuit is switched to that from a different signal source, the color of the color signal supplied from the new signal source to the color signal processing circuit is changed. When the phase of the burst signal greatly changes with respect to the phase of the color burst signal of the color signal that has been supplied to the color signal processing circuit, the control circuit 1
The feedback coefficient of the feedback coefficient circuit 32 in the above-mentioned circuit arrangement is changed to zero or a small value by the control signal output from the circuit arrangement, and the nonlinear signal processing circuit 63 (in the case of the first illustrated embodiment) or , Subtractor 35 (first
(In the case of the embodiment shown in the drawing), the data applied to the value is zero or a small value, so that the color phase signal sent from the subtractor 62 to the subsequent circuit in the case of the first embodiment,
Since the color phase signal sent from the subtractor 35 to the subsequent circuit in the case of the fourth illustrated embodiment is the color phase signal of the color signal supplied to the color signal processing circuit from the new signal source, The color signal processing circuit of the invention can satisfactorily solve the problems of the already proposed color signal processing circuit.

(Effect of the Invention) As is clear from the above description, the present invention is based on the two color difference signals obtained when the color demodulation of the carrier color signal is performed with the two color difference axes orthogonal to each other. Phase data generating means for generating phase data of the signal and phase data for the color synchronizing signal period generated by the phase data generating means for the color synchronizing signal period can be stored as a signal which is an integral multiple of the vertical scanning period. Means for generating average value data, which is supplied to a cyclic digital filter including a memory, an arithmetic circuit, and a feedback coefficient circuit having a high feedback ratio to obtain average value data of phase data in the past color synchronization signal period When,
Phase data comparing means for comparing the average value data of the phase data of the past color synchronizing signal period generated by the above mean value data generating means with the phase data of the current color synchronizing signal period, and the above phase data The first counting means for counting the number of pieces of data showing the difference equal to or larger than a predetermined size as the comparison result in the comparing means, and the count value of the first counting means in advance. And a means for changing the feedback coefficient of the feedback coefficient circuit of the digital filter to decrease when the number of vertical scanning periods exceeding the predetermined number continuously exceeds the predetermined number. Color signal processing circuit and carrier color signal orthogonal to each other 2
A phase data generating means for generating phase data of the carrier color signal based on two color difference signals obtained by color demodulation with one color difference axis; and a phase data generating means for the phase synchronization signal during the color synchronization signal period. The generated phase data of the color synchronization signal period is supplied to a cyclic digital filter configured to include a memory capable of storing a signal of an integral multiple of the vertical scanning period, an arithmetic circuit, and a feedback coefficient circuit having a high feedback rate. Mean value data generating means for obtaining average value data of phase data in the past color synchronizing signal period, and mean value data of the phase data in the past color synchronizing signal period generated by the mean value data generating means. A comparison result between the phase data comparing means for comparing the phase data in the current color synchronization signal period and the above-mentioned phase data comparing means shows a difference of a predetermined magnitude or more. First counting means for counting the number of data for each vertical scanning period, and the number of vertical scanning periods in which the count value of the first counting means exceeds a predetermined number, is continuously determined in advance. When the number exceeds a predetermined number, a means for changing the feedback coefficient of the feedback coefficient circuit of the digital filter to decrease, a memory capable of storing a signal of an integral multiple of the vertical scanning period, an arithmetic circuit, and high feedback Since it is a color signal processing circuit that comprises means for generating a phase shift amount signal that represents a residual phase error in the color synchronization signal period from a cyclic digital filter that is configured to include a rate feedback coefficient circuit, Various problems occurring in the already proposed color signal processing circuit can be solved well. That is, in the color signal processing circuit described above, the feedback coefficient circuit 3 of the color signal processing circuit 3 is provided so that the effect intended by the color signal processing circuit can be sufficiently obtained.
A signal having a high feedback rate is used as 2, and a new signal source is used, for example, when the color signal subjected to signal processing in the color signal processing circuit is switched to that from a different signal source. When the phase of the color burst signal of the color signal supplied from the to the color signal processing circuit has changed significantly with respect to the phase of the color burst signal of the color signal supplied to the color signal processing circuit until then. Took a relatively long time for the playback image to become normal,
In the color signal processing circuit of the present invention, for example, the phase of the color signal supplied to the color signal processing circuit is wide, as when the signal source supplying the color signal to the color signal processing circuit is switched. When changed, the average value data of the past color burst signals generated by the means for generating the average value data in the circuit arrangement described above is compared with the data of the color phase signal based on the current color burst signal to determine in advance. The number of pieces of data indicating a difference equal to or larger than the predetermined size is counted for each vertical scanning period, and the count value exceeds the predetermined number. When the number of vertical scanning periods exceeds the predetermined number. To
The feedback coefficient of the feedback coefficient circuit 32 in the circuit arrangement described above is changed so as to be zero (or a small value), and the difference signal output from the subtractor 31 is changed within a short time in the circuit arrangement described above. Since the operation is performed so that it becomes a small value, if the color signal that is the target of signal processing in the color signal processing circuit is switched from a different signal source, the new signal source When the phase of the color burst signal of the color signal supplied to the color signal processing circuit changes significantly with respect to the phase of the color burst signal of the color signal supplied to the color signal processing circuit, the control circuit The feedback signal of the feedback coefficient circuit 32 in the circuit arrangement described above is changed to zero or a small value by the control signal output from the circuit arrangement 1, and the nonlinear signal processing circuit 63 is changed from the circuit arrangement described above.
(In the case of the embodiment shown in FIG. 1) or the data given to the subtractor 35 (in the case of the embodiment shown in FIG. 1) is set to zero or a small value, so that the subtracter 62 in the case of the embodiment shown in FIG. From the new signal source to the color signal processing circuit, and the color phase signal transmitted from the subtractor 35 to the subsequent circuit in the case of the fourth embodiment shown in FIG. Therefore, the color signal processing circuit of the present invention can satisfactorily solve the problems of the already proposed color signal processing circuit.

[Brief description of drawings]

1 and 4 are block diagrams of different embodiments of the color signal processing circuit of the present invention, FIGS. 2 and 3 are block diagrams of control circuits having different configurations, and FIGS. 5 and 9 are Block diagram of the proposed color signal processing circuit, FIG. 6 and FIG.
FIG. 0 is a characteristic example diagram of a part of the components of the color signal processing circuit, FIGS. 7 and 8 and 11 are explanatory diagrams of signal states,
FIG. 12 is a block diagram showing a configuration example of a color amplitude signal and color phase signal generation circuit, and FIGS. 13 and 14 are diagrams for explaining the operation of the color amplitude signal and color phase signal generation circuit shown in FIG. Is. 1 ... Control circuit, 2 ... Absolute value circuit, 3, 6, 11 ... Comparator, 4, 7, 9 ... Monostable multivibrator, 5, 10
... Counter, 8,14 ... Inverter, 8 ... AFC circuit, 1
2, 15 ... Serial-parallel converter, 13, 16 ... AND circuit, 2
7, 46 ... Adder, 19, 20 ... Two chrominance signals having the same signal form as the two chrominance signals to be obtained when the carrier chrominance signal including the color burst signal is color-demodulated on the two chrominance axes Input terminals for digital data of color difference signals of one of the two, 21, 25, 26 ... Dividers, 30,
31, 33, 35 ... Subtractor, 32 ... Feedback coefficient circuit, 3
8, 39 ... Multiplier, 34 ... Frame memory (or field memory), 22-24, 28, 36, 37, 55
... arithmetic circuit, 40, 41 ... output terminals, 42, 43 ... absolute value circuit, 44 ... polarity reversing circuit, 45, 51, 52, 5
3, 56 ... Changeover switch, 47, 48 ... Signal generating circuit,
49, 50 ... Logic 0 value detection circuit, 54 ... OR circuit, 6
3 ... Nonlinear signal processing circuit, 62 ... Subtractor,

Claims (2)

[Claims] 1. Phase data generating means for generating phase data of the carrier color signal based on the two color difference signals obtained when color demodulating the carrier color signal with two color difference axes orthogonal to each other, and color. The phase data of the color synchronization signal period generated by the phase data generating means in the synchronization signal period includes a memory capable of storing a signal of an integral multiple of the vertical scanning period, an arithmetic circuit, and a feedback coefficient circuit of high feedback rate. Means for generating average value data, which is supplied to the configured cyclic digital filter to obtain average value data of phase data in the past color synchronization signal period, and the past value generated by the means for generating average value data. The comparison result in the phase data comparing means for comparing the average value data of the phase data in the color synchronizing signal period with the phase data in the current color synchronizing signal period and the comparison result in the phase data comparing means is A first counting means for counting the number of pieces of data showing a difference equal to or more than a predetermined size for each vertical scanning period; and a vertical direction in which the count value of the first counting means exceeds a predetermined number. A color signal processing circuit comprising means for changing the feedback coefficient of the feedback coefficient circuit of the digital filter so as to decrease the number when the number of scanning periods exceeds a predetermined number continuously. 2. A phase data generating means for generating phase data of the carrier color signal based on the two color difference signals obtained when the carrier color signal is color demodulated by two color difference axes orthogonal to each other. The phase data of the color synchronization signal period generated by the phase data generating means in the synchronization signal period includes a memory capable of storing a signal of an integral multiple of the vertical scanning period, an arithmetic circuit, and a feedback coefficient circuit of high feedback rate. Means for generating average value data, which is supplied to the configured cyclic digital filter to obtain average value data of phase data in the past color synchronization signal period, and the past value generated by the means for generating average value data. The comparison result in the phase data comparing means for comparing the average value data of the phase data in the color synchronizing signal period with the phase data in the current color synchronizing signal period and the comparison result in the phase data comparing means is A first counting means for counting the number of pieces of data showing a difference equal to or more than a predetermined size for each vertical scanning period; and a vertical direction in which the count value of the first counting means exceeds a predetermined number. Means for changing the feedback coefficient of the feedback coefficient circuit of the digital filter so as to decrease when the number of scanning periods continuously exceeds a predetermined number, and a signal of an integral multiple of the vertical scanning period. And a means for generating a phase shift amount signal representing a residual phase error in the color synchronization signal period from a recursive digital filter configured to include a memory capable of storing data, an arithmetic circuit, and a feedback coefficient circuit having a high feedback ratio. Color signal processing circuit