JPH0646387B2 - Micro computer - Google Patents

Description

TECHNICAL FIELD The present invention relates to a microcomputer, and more particularly to a microcomputer having a read-only memory (hereinafter abbreviated as ROM) built therein.

[Conventional technology]

In a so-called single-chip microcomputer (hereinafter abbreviated as a microcomputer) having a built-in ROM, which is formed on a semiconductor substrate, programs and numerical data are stored in the ROM. The content of the ROM is determined in a certain process in the manufacturing process of the microcomputer, and it is necessary to confirm that all the stored contents are correct at the time of manufacturing. Therefore, the contents of the ROM can be easily read to the external terminals by the logic level of the external terminals including the test terminals of the conventional microcomputer.

FIG. 3 is a block diagram showing a main part of an example of a conventional microcomputer.

In this figure, when the ROM test external terminal 3 is made non-active (for example, a "low" logic level), the microcomputer is in an operation mode normally used. RO via the address bus 9 by the program counter 5 of the CPU 2A
Addressing of M1 is performed, and instructions and data are sequentially read out and processed by CPU 2A. Further, data is input / output to / from the outside through the input / output port 8 as necessary.

Next, when the ROM test external terminal 3 is made active (for example, a “high” logic level), the test control signal 4
Then, the control circuit 6A of the CPU 2A enters the read mode of the ROM 1. After resetting, the program counter 5 in the CPU 2A increments by 1, and the control circuit 6A successively outputs the contents of the ROM to the data bus 10 one address at a time. Here, the control circuit 6A
Thus, the input / output port 8 is in an output state, the contents of the ROM 1 are sequentially output to the outside via the data bus 10 and the input / output port 8, and the expected data is externally output by an integrated circuit tester (hereinafter abbreviated as IC tester). Be compared.

[Problems to be solved by the invention]

In recent years, the range of applications of microcomputers with built-in ROM has expanded more and more, and applications requiring confidentiality, such as handling data related to money such as IC cards, are also increasing. Therefore, in order to keep confidentiality, the contents and data of the ROM built in the microcomputer are not easily output to the outside, and it is necessary to devise a ROM read test at the time of manufacturing.

[Means for solving problems]

The microcomputer of the present invention latches the data on the data bus and outputs the first and second registers for outputting to the arithmetic and logic operation unit and the ROM test external terminal to a predetermined logic level to obtain the first timing. The contents of the ROM designated by the program counter are latched in the first register via the data bus, and the comparison data with the contents of the first register is externally transmitted via the input port and the data bus at the second timing. It is latched in the second register, and at a third timing, the arithmetic result between the contents of the first and second registers by the arithmetic logic operation unit is output to the outside through the data bus and the output port, and the second or the second register is output. It has a control means for causing the program counter to be incremented at any one of the three timings.

[Action]

RO that outputs the above-mentioned conventional ROM contents to the outside
For the M read test, the present invention inputs the expected value of the ROM content from the outside into the microcomputer, compares it internally, and outputs only the result to the outside.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the microcomputer of the present invention, and FIG. 2 is a timing chart showing its operation.

The microcomputer of this embodiment is similar to the conventional example shown in FIG.
Register that latches data on 10 and outputs to ALU11
12, 13 and a test instruction code issuing circuit 15 are added.

Next, the operation of this embodiment will be described.

When the ROM test external terminal 3 is made inactive, it is a normal operation mode. The ROM 1 is addressed by the program counter 5 of the CPU 2, the instruction code is fetched into the instruction register 7 and then decoded, and the data of the ROM 1, the data memory 16, the port 8 and the like are sequentially processed by the CPU 2 including the ALU 11. Data is input / output to / from the outside through the ports 8 and 14 as necessary.

Next, when the external terminal for ROM test is activated, the read control mode of the ROM 1 is set by the test control signal 4 and the control circuit 6. Here, the program counter 5 is a master-slave flip-flop (hereinafter referred to as MS-
(Abbreviated as F / F) and an incrementer,
The ROM address increment result is the master F / F
Is latched to. Further, the address data from the data bus 10 and the output of the increment result to the address bus 9 are made by the latch to the slave F / F. First, after resetting the microcomputer, the MS-F / F of the program counter 5 is reset, and at the first timing, the address 0 of the ROM 1 is designated via the address bus 9.
The contents of address 0 of ROM1 are transferred to the data bus by the control circuit 6.
Output to 10. Further, the data on the data bus 10 is latched in the register 12. At the second timing, the expected value at address 0 of ROM 1 is externally latched to register 13 via input / output port 8 and data bus 10, and program counter 5 is incremented (+1). Third
At the timing of ALU11, register 12 to register 13
Is subtracted and the result is the data bus 10, port
It is output to the outside via 14. The next timing is the same as the above first timing, and the value of the master F / F (1st address) of the program counter 5 is output to the address bus 9 at the same time as being latched by the slave F / F, and in the ROM read mode. , Each of the addresses is sequentially read with the first to third timings as one read cycle.
Master F of the program counter 5 at the first timing
At the same time that the value of / F is latched by the slave F / F, it is output to the address bus 9, and the ROM contents of the designated address are latched in the register 12. At the second timing, the expected value of the ROM content of each address is input from the input / output port 8 and latched in the register 13 and the increment result of the program counter 5 is latched in the master F / F. At the third timing, the contents of register 13 are subtracted from the contents of register 12 in ALU 11, and the result is output to the outside via port 14.

If the ROM contents at a certain address and the expected value do not match after repeating the above ROM read test, "1" is output to the mismatch bit. During the ROM read test,
No instruction code is read from the data bus 10 into the instruction register 7. Therefore, the instruction code for performing the required operation at each timing is generated by the test control signal 4 and the test instruction code generating circuit 15 and set in the instruction register 7. This instruction code is decoded by control circuit 6, and each gate performs control for performing a required operation. In the present embodiment, only the comparison by subtracting the ROM content and the expected value has been described, but it goes without saying that the comparison can be performed by changing the expected value even if another operation such as exclusive OR is executed. It is also possible to control the calculation result by the ALU 11 to be output to the input / output port 8. The same result can be obtained by latching the increment result of the program counter 5 in the master F / F at the third timing.

〔The invention's effect〕

As described above, according to the present invention, the expected value of the ROM contents is I
By using a C tester or the like to input the data into the microcomputer from the outside and outputting only the operation result with the ROM output to the outside, only a person who knows the ROM contents in advance can perform a read test, which is a great effect on confidentiality protection. In addition, by effectively utilizing the functions of the microcomputer, a ROM output / input data comparison circuit etc. is unnecessary, and a ROM read test effective for maintaining confidentiality can be performed only by adding a simple test circuit. .

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the microcomputer of the present invention, FIG. 2 is a timing diagram showing the operation of the microcomputer of FIG. 1, and FIG. 3 is a block diagram of a conventional example. 1 ... ROM, 2 ... CPU, 3 ... ROM test external terminal, 4 ... Test control signal, 5 ... Program counter, 6 ... Control circuit, 7 ... Instruction register, 8 ... I / O port , 9 ... Address bus, 10 ... Data bus, 11 ... Arithmetic operation unit (ALU), 12 ... Register, 13 ... Register, 14 ... Output port, 15 ... Test instruction code generation circuit, 16 ... ... RAM.

Claims (1)

[Claims] 1. A ROM for storing an instruction, a program counter for designating an address of the ROM, an arithmetic and logic unit for executing an instruction read from the designated address of the ROM, and a data bus. A microcomputer including an input / output port and an external terminal for ROM test, which latches data on the data bus and outputs the data to the arithmetic logic operation unit.
By setting the second register and the ROM test external terminal to a predetermined logic level, the contents designated by the program counter and read from the ROM at the first timing are transferred to the first via the data bus. Data is transferred to the second register via the input port at the second timing, and the data is transferred to the second register at the second timing by the arithmetic logic operation unit at the third timing. A control circuit for executing arithmetic processing on the content of the second register, outputting the result to the outside through the output port, and further updating the content of the program counter at either the second or the third timing. And a microcomputer provided with.