JPH0646411B2 - End token output circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory interface circuit for executing a read / write operation from a data flow processor to a memory, and more particularly to a termination token output circuit in the memory interface circuit.

[Conventional technology]

Conventionally, there is μPD7281 manufactured by NEC Corporation as a data flow processor. As a memory interface circuit in an arithmetic processing system using this data flow processor, there is μPD9305 manufactured by NEC Corporation. The memory access operation of the μPD9305 will be described first.

The μPD9305 performs data transfer and arithmetic processing by the data flow method, and the input / output data is called a token.

A token is set data composed of a data part, an identifier indicating the meaning of the data part, a destination tag indicating the destination of the token, and the like.

For example, in the case of memory writing, a data part which is write data, a write data token having an identifier indicating the write data and a destination tag whose destination is the memory interface circuit, and a data part which is the write address, write A write address token having an identifier indicating an address and a destination tag whose destination is the memory interface circuit is input to the memory interface circuit in this order. The memory interface circuit has a plurality of write data registers inside, and when a write data token is input, the write data of the data part is set in the write data register and held.

Next, when the write address token is input, the memory interface circuit outputs the write data held in the write data register to the memory, the write address of the data portion of the write address token, and the memory write designation signal. Instruct write operation.

The memory executes the write operation according to the instruction, and when this is completed, returns an access end signal to the memory interface circuit.

The memory interface circuit receives the access end signal and ends the memory writing.

In the case of memory reading, a data section that is a read address, an identifier that has destination information indicating the destination of the read data and identifier information that the read data should have, and a read address that has a destination tag that has the memory interface circuit as the destination. Input the token to the memory interface circuit. The memory interface circuit has an address register and a read data register inside. When a read address token is input, the read address of the data part is set in the address register, the memory read operation is executed, and the read operation is performed. Input and hold the data in the read data register. Next, the value held in the read data register is used as a data part, and the destination information and the identifier information of the read data which the input read address token identifier has are decoded and output as a read data token,
The read operation is completed.

[Problems to be solved by the invention]

With the write function of the conventional memory interface circuit described above, the token input to the memory interface circuit disappears when the write operation to the memory ends. By the way, in the data flow processor, write data token to memory and write address token are generated and sent to the memory interface circuit.
I don't know when I'm writing. Here, consider a case where two processes are executed in sequence, the processing result of the previous process is written to the memory, and the next process reads and processes it. At this time, the second
Process must be processed after the memory write by the first process is completed.

The data flow processor outputs a memory write token in the first process and a memory read token in the second process, but it is not possible to determine when it was actually written in the memory. Therefore, if the start of the next process is too early, there is a risk that the second process reads the result of the first process before the process result of the first process is written in the memory.

Therefore, as a conventional method, the second process is started after a sufficient time interval for writing the processing result of the first process in the memory. However, since the second process should be able to be started immediately after the writing is completed, the conventional method has a drawback of adding unnecessary waiting time.

This is a problem in the synchronization of the process termination, and the next process activation cannot be started in synchronization with the final writing to the memory.

An object of the present invention is to provide a memory interface circuit,
An object of the present invention is to provide an end token output circuit having a function of outputting an end token indicating that the start of the next process is permitted in order to safely start between processes.

[Means for solving problems]

The present invention relates to a memory interface circuit which is connected between a plurality of data flow processors connected in a ring shape and a memory, and which executes a read / write operation to the memory according to an instruction of a token input from the data flow processor. A write data register for holding data to be written to the memory, an end data register for inputting and holding the end data, and a value of the write data register when memory write is instructed by input of the token. And a value of the end data and outputs an end signal, and an output token register for inputting and holding the end token and outputting the end token held by the input of the end signal from the comparing unit. Is characterized by.

[Action]

The write data register holds the data to be written to the memory, while the end data register holds the write end data register, and in synchronization with the start of the write operation, the contents of the write data register and the end data register are compared in the comparison section. To compare. Since the write execution of the final write data can be detected by the coincidence of the contents, it becomes possible to output the end token informing that the start of the next process is permitted.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. The end token output circuit 10 includes a write data register 26, an end data register 12, a comparison unit 13, and an output talk range circuit.
Composed of 14.

The write data register 26 receives the data to be written in the memory 20 through the signal line 104 from the token input unit 21 and holds it. The end data register 12 receives the write end data of the preceding process from the token input unit 21 through the signal line 104 and holds it. The output token register 14 inputs and holds the end token output at the end of the process from the token input unit 21 through the signal line 104. The comparison unit 13
When the write address token is input to the token input unit 21 and is held in the address register 11 of the data section and the write operation is started, the contents of the write data register 26 are terminated from the signal line 105. The contents of the data register 12 are input from the signal line 101 and compared, and if they match, an end signal is output to the signal line 102. The output token register 14 outputs the content of the output token register 14 as an end token from the signal line 103 if the end signal of the signal line 102 is ON.

The data flow processors 22 and 23 are processors that process processes including address calculation. The end token output circuit 10 includes a token input unit 21, a token output unit 24,
A memory interface circuit 30 for accessing the memory 20 is configured by being combined with the address register 11 and the read data register 25, and is connected to the data flow processors 22, 23 in a ring shape by the signal lines 107, 108, 109. Has been done.

The token input unit 21 causes the address register 11, the write data register 26, the end data register 12, and the output token register 14 to hold the data portion of the token according to the instruction of the token input from the signal line 109 via the signal line 104. The address register 11 has the memory 20 as already mentioned.
Is output to the memory 20, and the write data register 26 outputs write data in the write operation to the memory 20. The read data register 25 transfers the read data of the memory 20 to the signal line 10
The input is held from 5 and output to the signal line 106.
The signal line 111 is for passing through the token output unit 24 when the destination of the token input to the token input unit 21 is other than the memory interface circuit 30. The signal line 110 is for outputting a control signal for accessing the memory 20 when the token input by the token input unit 21 indicates a memory access. The token output unit 24 outputs a signal from the signal line 106 during a memory read operation, a signal line 111 when a token other than a memory access is input to the token input unit 21, and a signal when the end token output circuit 10 writes a process end. Input from line 103 and output as token to signal line 107.

Next, the operation of the present embodiment will be described in the case where the processing result of the first process is written in the memory 20 and the subsequent second process reads the processing result from the memory 20 and processes it.

In the first process, when a memory write token is input to the token input unit 21 from the signal line 109, the write data register 26 of the end token output circuit 10 is written to the memory 20 by the signal line 104 according to the token instruction. Enter and hold data. On the other hand, the write end address of the first process is input to and held in the end data register 12 via the signal line 104. In fact, the end token output at the end of the process is input and held in the output token register 14 by the signal line 104. Further, the write address to the memory 20 is held by the address register 11 and the signal 104. Then, by the control signal for accessing the memory 20 through the signal line 110, the memory is
The operation of writing data to 20 is started.

The comparison unit 13 synchronizes with the start of the write operation,
The contents of the write data register 26 are input from the signal line 105 and the contents of the end data register 12 are input from the signal line 101, respectively, and compared. When the write operation is completed, the contents of the write data register 26 and the contents of the end data register 12 match, so at this time, an end signal is output to the output talk register 14 through the signal line 102. As a result, the token output unit 24 outputs the process end write to the signal line 107 as a token.

The data flow processor learns from the end token that the activation of the next second process is permitted, and immediately starts the read operation of the memory 20.

〔The invention's effect〕

As described above, according to the present invention, when the data flow processor performs the processing of writing the processing result in the memory in the first process and reading the processing result in the second process, the memory of the first process The second process can be started when all the writing is completed. Therefore, it is possible to safely start the second process. That is, the end token synchronized with the memory writing is output, and if this is used as the activation token of the second process, the waiting overhead time for the activation of the second process between processes is effectively eliminated.

[Brief description of drawings]

 FIG. 1 is a block diagram showing an embodiment of the present invention. 10 …… End token output circuit 11 …… Address register 12 …… End data register 13 …… Comparison unit 14 …… Output token register 20 …… Memory 21 …… Token input unit 22,23 …… Data flow processor 24 …… Token output section 25 …… Read data register 26 …… Write data register 30 …… Memory interface circuit 100-111 …… Signal line

Claims (1)

[Claims] 1. A memory interface, which is connected between a plurality of data flow processors connected in a ring shape and a memory, and executes a read / write operation to the memory according to an instruction of a token input from the data flow processor. An end token output circuit in the circuit, which is a write data register for holding data to be written to the memory, an end data register for inputting and holding end data, and a write data register for the write data register when memory writing is instructed by input of a token. A comparison unit for comparing a value with the value of the end data and outputting an end signal; and an output token register for input-holding the end token and outputting the end token held by the input of the end signal from the comparison unit. An end token output circuit characterized by the above.