JPH0646520B2 - Semiconductor memory device - Google Patents

Description

The present invention relates to a semiconductor memory device having an error detection / correction (hereinafter referred to as "ECC") function.

[Conventional technology]

2. Description of the Related Art Recently, as semiconductor memory devices have been highly integrated, malfunction of memory cells due to incidence of α particles, that is, soft error has become a problem. As a countermeasure against this, an on-chip ECC provided with an ECC function on the same semiconductor substrate is performed.

FIG. 4 shows a circuit example of a conventional on-chip ECC semiconductor memory device. In FIG. 4, 1 is an input terminal to which the data bit a is input, and 2 is a write from the data bit a.
A write check bit generation circuit 3 for generating a check bit b, a memory cell array 3 for inputting and storing a data bit a and a write check bit b, and outputting as necessary, 3a is a data Data bit array for inputting and storing bit a, 3b is a check bit array for inputting and storing write check bit b, and 4 is inputting data bit c and outputting a new check bit e Read check bit generation circuit, 5 is a syndrome generation circuit which has a function of exclusive OR and outputs the syndrome f, 6 is a syndrome decoder which decodes the syndrome f and outputs the syndrome decode data g, and 7 is the syndrome decode Corrected data by correcting data bit c and check bit d with data g And data correction circuit for outputting the external output data i, 8 is an address decoder for selecting an external output data j to be output to the outside, 9 external output data j
Is an output terminal for outputting.

Next, the operation of the apparatus thus configured will be described. At the time of writing the _mo bit data bit a input to the input terminal 1, the write check bit generation circuit 2 outputs a plurality of data bits (including m bits) including the data bit a. A write check bit (k bit) b is generated, and the write check bit b and m data bits are written to the memory cell array 3.

When data is read from the memory cell array 3, m-bit data bit c and k-bit write check
The bit d is read at the same time, and the read check bit generating circuit 4 performs read check as a new check bit from the m-bit data bit c.
Generate bit e. Next, by the syndrome generation circuit 5, the read check bit e and the memory cell
Write check bit d read from array 3
Bitwise exclusive OR of and. As a result, if all the bits are "0", it is determined that there is no error, and if not, it is determined that there is an error. All the bits are "0", which means that the k-bit read check bit e and the write
It means that the check bit d matches.
The exclusive OR data described above is called a syndrome.
The syndrome is a data string consisting of k bits. The syndrome generation circuit 5 outputs the syndrome f to the syndrome decoder 6.

The syndrome f described above includes error bit position information, and by decoding this with the syndrome decoder 6, it is possible to know which bit is in error. In accordance with this, in the data correction circuit 7, m-bit data bit c and k-bit check bit d.
Error bits of the above are corrected, that is, inverted. In general, it becomes the corrected data set in the external data output m bits is m _o bits. In this case, _mo ≤ m bits. Therefore, as the external output output from the address decoder 8, the data j is selected and output according to the address information k input to the address decoder 8. In most cases, the address decoder 8 can also serve as a decoder (not shown) for access.

The write check bit generation circuit 2 and the read check bit generation circuit 4 are circuits that generate check bits from m data bits according to the structure of the error detection / correction code, and have the same logical operation. Therefore, there is a system in which the same circuit is used in common. As described above, the syndrome generation circuit 5 has the write check bit d read from the memory cell array 3 and the read check bit newly generated from the data bit c in the read check bit generation circuit 4. Check bit e
It is a circuit that takes an exclusive OR for each bit with. The syndrome decoder 6 is a decoder that converts a k-bit syndrome f into an m + k-bit code that specifies an error bit of the m-bit data bit c and the k-bit write check bit d, and is, for example, m +.
Of the k bits, an output is obtained in which only the error bit position is "1" and the others are "0". The data correction circuit 7 is a circuit that takes the bitwise exclusive OR of the syndrome decode data g output from the syndrome decoder 6 and the data bit c and the write check bit d to be corrected. , The data of only the error bit is inverted, that is, the error is corrected. The error-corrected m + k-bit corrected data h is written in a predetermined position in the memory cell array 3 again. In addition, m _o accessed in the corrected m bits of data bit i
The data bit of the bit is selected by the address decoder 8 and becomes the external output data j.

Next, a function test of the semiconductor memory device having the above-described on-chip ECC function will be described. The main functional tests are (a) data bit array 3a (b) check bit array 3b (c) ECC circuit system. (a) can be realized by stopping the ECC function, and (b) is a check bit array 3
This can be realized by making b directly accessible from the outside. However, there is no effective means for (c).

[Problems to be solved by the invention]

Since the conventional semiconductor memory device with on-chip ECC is configured as described above, there is a problem that it is not possible to perform a functional test only on the ECC circuit system.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor memory device having a test mode capable of testing the function of an ECC circuit system.

[Means for solving problems]

In order to solve such a problem, the present invention provides a light
A write check bit latch circuit for temporarily storing check bits, a first switching means for switching data input to the syndrome generation circuit according to a control signal, and a read check bit generation circuit Second switching means for switching data according to a control signal is provided.

[Action]

In the present invention, the functional test of the ECC circuit system is performed by the virtual data output from the second switching means.

〔Example〕

An embodiment of the semiconductor memory device according to the present invention is shown in FIG. In FIG. 1, 10 is an input switching circuit as a second switching means for switching the data input to the read check bit generation circuit 4 by a control signal, and 11 is for temporarily storing the write check bit. Is a write check bit latch circuit, and 12 is a check bit switching circuit as first switching means for switching data input to the syndrome generation circuit 5 by a control signal. In FIG. 1, the same or corresponding parts as those in FIG. 4 are designated by the same reference numerals. In terms of configuration, this device differs from the conventional semiconductor memory device shown in FIG. 4 in that the input switching circuit 10 and the write check bit latch 1 described above are used.
There are three circuits, 1 and the check / bit switching circuit 12.

The functions of these three circuits will be described. First, the input switching circuit 10 will be described. This circuit uses the control signal TE
The following operation is performed in accordance with. In the normal mode, that is, when TE = “L”, the data bit c output from the data bit array 3a is input to the read check bit generation circuit 4 to perform a normal ECC operation. In test mode, that is, TE = “H”
At this time, certain fixed data, for example, data in which all bits are "0" (hereinafter abbreviated as "all bits = 0") is input to the read check bit generation circuit 4. As a result, in the test mode, regardless of whether the data bit array 3a is good or bad, certain virtual data, for example, all bits = 0 can be input to the read check bit generation circuit 4. A specific example of this circuit is shown in FIG. In FIG. 2, A1 to A
m is an input terminal to which the m-bit data bit c is input, and 20 is an input terminal to which the control signal TE is input.

Next, the write check bit latch circuit 11 will be described. This circuit is a latch circuit for temporarily storing the write check bit generated during the write operation. This content is rewritten every time a write operation is performed.

Next, the check / bit switching circuit 12 will be described.
This circuit operates as follows according to the control signal TE. In the normal mode, that is, when TE = “L”, the write check bit d from the check bit array 3b is input and the normal ECC operation is performed. In the test mode, that is, when TE = "H",
Write check bit to the syndrome generation circuit 5
The data from the latch circuit 11, that is, the write check bit generated in the immediately preceding write operation is input. A specific example of this circuit is shown in FIG. In FIG. 3, B is an input terminal to which the k-bit write check bit is input, and 30 is an input terminal to which the control signal TE is input.

E of a device composed of a circuit having such a function
The operation of the CC test mode will be described below. By some method, for example, by temporarily stopping the ECC function, the data bit array 3a, the check bit
It is assumed that the operation test of the array 3b has been completed, that is, it is confirmed that the memory cell array 3 is all good. Read check during test mode
When data of all bits = 0 is input to the bit generation circuit 4, a read check bit e for this virtual data is generated. Therefore, at the time of the write operation immediately before that, all bits = 0 in the data bits of the same ECC circuit system.
If the ECC circuit system is operating normally, the data will not be corrected for any of the target data bits, and the corrected data h will all be "0". . When writing the data of "1" only for a certain bit and "0" for others at the time of last writing,
Data correction should be performed on the bit position where "1" is written. If all the corrected data h are "0", the ECC circuit system is operating normally. By using virtual data in this way, EC
A functional test of the C circuit system can be easily performed.

In this embodiment, as the virtual data, the case where the fixed data is all bits = 0 is shown, but this may be fixed and not all bits = 0, or may be variable data given from the outside.

Further, the case of the ECC using the Hamming code as the error correction code is shown, but the case of the ECC using another method such as the horizontal / vertical / parity check method is also applicable.

〔The invention's effect〕

As described above, the present invention includes the write check bit latch circuit for temporarily storing the write check bit, and the first switching means for switching the data input to the syndrome generation circuit according to the control signal. By providing the second switching means for switching the data input to the read check bit generation circuit according to the control signal, the virtual data can be used in the ECC circuit system, so that the function of the ECC circuit system is independent. The test can be performed, and the function test of the semiconductor memory device with the on-chip ECC can be easily performed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a semiconductor memory device according to the present invention, FIG. 2 is a detailed circuit diagram of an input switching circuit which constitutes this device, and FIG. 3 is a check bit switching which constitutes this device. A detailed circuit diagram of the circuit, and FIG. 4 are circuit diagrams showing a conventional semiconductor memory device. 1 ... Input terminal, 2 ... Write check bit generation circuit, 3 ... Memory cell array, 3a ... Data bit array, 3b ... Check bit array, 4
...... Read check bit generation circuit, 5 ... Syndrome generation circuit, 6 ... Syndrome decoder, 7 ...
Data correction circuit, 8 ... Address decoder, 9 ... Output terminal, 10 ... Input switching circuit, 11 ... Write check bit latch circuit, 12 ... Check bit switching circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shuji Miyatake 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Corporation LSE Research Institute (72) Inventor Katsumi Dosaka 4-1-1 Mizuhara, Itami-shi, Hyogo (72) Inventor Tsuyoshi Yoshihara, 4-chome, Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric Co., Ltd. (58) JP, A) JP 56-163599 (JP, A) JP 59-201296 (JP, A) JP 56-68999 (JP, A) Actual development 60-77100 (JP, U) Electronic Engine ring Mid-March 1981 p 33-43

Claims (3)

[Claims] 1. A semiconductor memory device comprising a write check bit generation circuit, a read check bit generation circuit, and a syndrome generation circuit for an error detection / correction function on the same substrate. And a write check bit latch circuit for temporarily storing the output of the check bit array output or the write check bit latch circuit output to the syndrome generation circuit according to a control signal. 2. A semiconductor memory device comprising: a switching unit 1 and a second switching unit for outputting either a data bit array output or virtual data to a read check bit generation circuit according to a control signal. 2. The semiconductor memory device according to claim 1, wherein the second switching means uses fixed data as virtual data. 3. The semiconductor memory device according to claim 1, wherein the second switching means sets the data input from the outside as virtual data.