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JPH0648198B2 - Automatic zero correction method - Google Patents
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JPH0648198B2 - Automatic zero correction method - Google Patents

Automatic zero correction method

Info

Publication number
JPH0648198B2
JPH0648198B2 JP61200978A JP20097886A JPH0648198B2 JP H0648198 B2 JPH0648198 B2 JP H0648198B2 JP 61200978 A JP61200978 A JP 61200978A JP 20097886 A JP20097886 A JP 20097886A JP H0648198 B2 JPH0648198 B2 JP H0648198B2
Authority
JP
Japan
Prior art keywords
signal
converter
cpu
value
measurement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP61200978A
Other languages
Japanese (ja)
Other versions
JPS6355412A (en
Inventor
雅洋 友枝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Seimitsu Co Ltd
Original Assignee
Tokyo Seimitsu Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Seimitsu Co Ltd filed Critical Tokyo Seimitsu Co Ltd
Priority to JP61200978A priority Critical patent/JPH0648198B2/en
Publication of JPS6355412A publication Critical patent/JPS6355412A/en
Publication of JPH0648198B2 publication Critical patent/JPH0648198B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Indication And Recording Devices For Special Purposes And Tariff Metering Devices (AREA)

Description

【発明の詳細な説明】 〈産業上の利用分野〉 この発明は比較測定の検出器、例えば差動変圧器による
検出器において、零点を自動的に補正して測定を行う回
路に係るものである。
TECHNICAL FIELD The present invention relates to a detector for comparative measurement, for example, a detector using a differential transformer, which relates to a circuit for automatically correcting the zero point for measurement. .

これらの検出器は基準となる零マスタワークによって零
点を決め、これとの差によって測定するのであるが、機
構的なズレのため零点が狂う。
These detectors determine the zero point by the reference zero master work, and measure by the difference from this, but the zero point is deviated due to mechanical deviation.

そこで測定に先立って零点の修正を行う。本発明はこの
零点補正に関する技術である。
Therefore, the zero point is corrected before the measurement. The present invention is a technique relating to this zero point correction.

〈従来技術〉 第2図において、いまデジタル表示値フルスケール±1
00の範囲でデジタル測定する場合、零点が0位置から
右にずれA点であったと仮定する。そのとき従来技術で
はA点のデジタル信号値を記憶して、測定信号によりデ
ジタル表示された表示値より、A点のデジタル信号値を
減算して測定値を作っていた。
<Prior Art> In FIG. 2, the digital display value is now full scale ± 1.
When the digital measurement is performed in the range of 00, it is assumed that the zero point is the point A which is shifted to the right from the 0 position. At that time, in the prior art, the digital signal value at the point A was stored, and the digital signal value at the point A was subtracted from the display value digitally displayed by the measurement signal to create the measured value.

しかし、これでは測定感度を倍にした場合(演算増幅器
の増幅率を倍にする)、A点の数値も倍になり、測定範
囲の最大読みまでの測定範囲が狭くなる(ダイナミック
レンジが狭くなる)。
However, in this case, when the measurement sensitivity is doubled (the amplification factor of the operational amplifier is doubled), the numerical value at the point A is also doubled, and the measurement range up to the maximum reading of the measurement range is narrowed (the dynamic range is narrowed). ).

例えば、測定感度を演算増幅器3の増幅率を上げる事に
より10倍にすると、A点100μmの最小分解能が
0.1μmになり、フルスケール100.0μmの表示
器が得られる。
For example, if the measurement sensitivity is increased 10 times by increasing the amplification factor of the operational amplifier 3, the minimum resolution at the point A of 100 μm becomes 0.1 μm, and a full scale display device of 100.0 μm can be obtained.

そのとき、A点の36μmは36.0μmとなり、表示
器のフルスケールは±10.0μmとなり測定点が表示
出来なくなるか、又は表示器をそのまま±100μmと
しておけば0.1μm台の零点補正は出来ない事にな
る。
At that time, 36 μm at point A becomes 36.0 μm, and the full scale of the display becomes ± 10.0 μm, and the measurement point cannot be displayed, or if the display is left as it is ± 100 μm, the zero point correction of 0.1 μm range is possible. It will not be possible.

そのため、初めから0.1μm迄の分解能が得られる4
桁のA/Dコンバータを用意すれば、増幅率が10倍に
なっても、前記±100と同等な精度分解能になるよう
にする事は可能である(1μm読みの時は0.1μm台
の表示は無視する)が、A/Dコンバータに高分解能・
多ビットのものが必要となり、コスト面で問題となる欠
点がある。
Therefore, a resolution of 0.1 μm can be obtained from the beginning 4
If a digit A / D converter is prepared, it is possible to obtain an accuracy resolution equivalent to ± 100 even when the amplification factor increases 10 times (in the case of 1 μm reading, 0.1 μm level (Ignore the display), but with high resolution in the A / D converter.
There is a drawback that a multi-bit type is required, which causes a problem in cost.

また、高分解能とするためにはそれだけ複雑な回路を必
要とし、これにつれてノイズに対する信頼性が低下し、
温度ドリフト等でアナログ的不安要素が増加して取り扱
いにくい欠点がある。
Also, in order to achieve high resolution, such a complicated circuit is required, and as a result, reliability against noise decreases,
There is a drawback that analog factors such as temperature drift increase and it is difficult to handle.

〈問題点を解決するための手段〉 ここで、第2図において、零点のずれAを36μmとす
ると、検出器からの整流信号と演算するCPUからの設
定単位を設定する一例として10桁で区切れば、N×
(設定単位)は、3×10だけD/Aコンバータを通し
たアナログ量で零点を左にずらせて、設定単位10μm
以下のディジタル値の数6μmが演算増幅器の出力より
出る。
<Means for Solving the Problems> Here, in FIG. 2, when the zero point shift A is 36 μm, a rectified signal from the detector and a setting unit from the CPU for calculating the rectified signal are set in units of 10 digits. If cut, N ×
(Setting unit) is the analog amount passed through the D / A converter by 3 × 10 and the zero point is shifted to the left, and the setting unit is 10 μm.
The following digital value of 6 μm appears from the output of the operational amplifier.

この6μmをCPUで記憶し、検出器回路の信号による
表示器出力の値とデジタル演算をし、零点とする。
This 6 μm is stored in the CPU, and the value of the output of the display by the signal of the detector circuit is digitally calculated to obtain the zero point.

ここで設定単位を5μmにすればN=7、n=1とな
る。
Here, if the setting unit is 5 μm, N = 7 and n = 1.

このようにすると設定される零点は設定単位数以下とな
るので、測定範囲が狭くなる度合を非常に小にすること
ができる。そしてA/Dコンバータを高精度・多ビット
のものに変更する必要も生じない。
In this way, the number of zeros set is less than or equal to the set number of units, so the degree to which the measurement range is narrowed can be made extremely small. Further, there is no need to change the A / D converter to a high precision multi-bit converter.

〈実施例〉 以下、図面を参照に本発明の実施例について説明する。<Examples> Examples of the present invention will be described below with reference to the drawings.

第1図において、検出器1からの信号出力は整流回路2
により直流アナログ信号に変換される。
In FIG. 1, the signal output from the detector 1 is the rectifier circuit 2
Is converted into a DC analog signal.

このアナログ信号は、A/Dコンバータによってディジ
タル信号となりCPU6に記憶される。
This analog signal is converted into a digital signal by the A / D converter and stored in the CPU 6.

そしてI/Oポート5を介しD/Aコンバータ7に入っ
て設定単位(上記の説明においては、10又は5)に対
して一定アナログ電圧を発生して、検出器回路の出力か
ら演算アンプ3においてアナログ演算する。
Then, it enters the D / A converter 7 through the I / O port 5 and generates a constant analog voltage for a set unit (10 or 5 in the above description), and the output of the detector circuit causes the operational amplifier 3 to output the analog voltage. Perform analog calculation.

このときCPUは演算増幅器3の出力(A/Dコンバー
タ4への入力信号)をゼロに最も近い値、すなわち設定
単位以下にするようにD/Aコンバータ7に逐次データ
を繰り返し送り設定単位以下になった時のデータをA/
Dコンバータに通し、自動零点設定値として、CPUに
デジタル記憶する。
At this time, the CPU repeatedly sends the data to the D / A converter 7 repeatedly so that the output of the operational amplifier 3 (the input signal to the A / D converter 4) becomes the value closest to zero, that is, the set unit or less, and the set unit or less. A /
It is passed through a D converter and digitally stored in the CPU as an automatic zero point setting value.

これによって自動零点調整の準備が完了したので、実際
の測定に移る。
With this, the preparation for the automatic zero adjustment is completed, and the actual measurement is started.

測定における検出器回路からの出力に対して、CPUか
らD/Aコンバータ7に対してN×(設定単位)に相当
する電圧が演算増幅器3に入れられて、演算されて、n
+測定値信号がA/Dコンバータ4に入り、CPUにお
いて、これから記憶されたnが減算されて真値が表示器
8に送られる。
With respect to the output from the detector circuit in the measurement, a voltage corresponding to N × (setting unit) is input from the CPU to the D / A converter 7 in the operational amplifier 3 and is operated to calculate n.
The + measurement value signal enters the A / D converter 4, and the stored n is subtracted from this in the CPU, and the true value is sent to the display 8.

〈効果〉 従来は最初の検出器のセットにおいて、大きく狂いがで
ると、それだけ測定範囲が狭くなるので、検出器のセッ
トに神経を使う必要があったが、本発明においては検出
器のセットの狂いと増幅率拡大測定範囲とは関係がない
ので、操作が簡単になった。
<Effect> Conventionally, if the first set of detectors is greatly out of alignment, the measurement range is narrowed accordingly, so it was necessary to use nerves in the set of detectors, but in the present invention, the set of detectors Since it has nothing to do with the deviation and the measurement range of amplification factor expansion, the operation became easier.

またA/Dコンバータの全幅が有効に使用されるため、
分解能の小さいA/Dコンバータの使用が可能で、安価
に回路を組むことができ、その実用性が著しく改善され
る。
Moreover, since the full width of the A / D converter is effectively used,
An A / D converter with a small resolution can be used, a circuit can be assembled at a low cost, and its practicality is significantly improved.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の構成を示すブロック図、第2図は零点
設定についての説明図。 1:検出器、2:整流回路 3:演算回路、4:A/Dコンバータ 5:I/Oポート、6:CPU 7:D/Aコンバータ
FIG. 1 is a block diagram showing the configuration of the present invention, and FIG. 2 is an explanatory diagram for zero point setting. 1: Detector, 2: Rectifier circuit 3: Arithmetic circuit, 4: A / D converter 5: I / O port, 6: CPU 7: D / A converter

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】アナログ信号を発信する検出器に基準零マ
スターワークを入れ、その信号を整流する整流回路と、
その信号とCPUにより設定された設定単位値信号をD
/Aコンバータで直流にした信号とを演算増幅器で演算
し、その信号出力が最小となる値をCPUに記憶し、ワ
ーク測定時、検出器回路の測定信号による表示器出力に
該CPUの記憶値を演算して出力表示する自動零点補正
方法。
1. A rectification circuit for rectifying the signal by inserting a reference zero master work into a detector that emits an analog signal.
The signal and the set unit value signal set by the CPU are D
/ The signal converted to DC by the A converter is calculated by the operational amplifier, and the value that minimizes the signal output is stored in the CPU, and the measured value of the CPU is stored in the display output by the measurement signal of the detector circuit when measuring the workpiece. Automatic zero correction method to calculate and output.
JP61200978A 1986-08-26 1986-08-26 Automatic zero correction method Expired - Fee Related JPH0648198B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61200978A JPH0648198B2 (en) 1986-08-26 1986-08-26 Automatic zero correction method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61200978A JPH0648198B2 (en) 1986-08-26 1986-08-26 Automatic zero correction method

Publications (2)

Publication Number Publication Date
JPS6355412A JPS6355412A (en) 1988-03-09
JPH0648198B2 true JPH0648198B2 (en) 1994-06-22

Family

ID=16433478

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61200978A Expired - Fee Related JPH0648198B2 (en) 1986-08-26 1986-08-26 Automatic zero correction method

Country Status (1)

Country Link
JP (1) JPH0648198B2 (en)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5233553A (en) * 1975-09-08 1977-03-14 Matsushita Electric Ind Co Ltd Offset compensatin circuit
JPS5555387U (en) * 1978-10-09 1980-04-15
JPS56125651A (en) * 1980-03-06 1981-10-02 Chino Works Ltd Temperature and humidity measuring apparatus

Also Published As

Publication number Publication date
JPS6355412A (en) 1988-03-09

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