JPH0648478B2 - Masterless serial bus occupancy control method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a bus occupancy control method when a plurality of processing devices share a communication bus, and more particularly to a control programmable controller (hereinafter abbreviated as PC). ) Is suitable for the bus occupancy control method.

[Conventional technology]

The PC inputs the states of switches, contacts, oscillators, etc. of the plant, and controls the ON / OFF of coils and motors, the opening / closing of valves, etc. by a program.
This program has a feature that it is executed at high speed and cyclically. In a system in which a plurality of PCs are connected, data transfer between the PCs occurs at high speed in synchronization with the above cycle.

Furthermore, what is required of the PC is compactness.

For that purpose, the data transfer device is preferably a serial bus rather than a parallel bus.

Also, as a control method of the serial bus, a method in which one processor can perform both the arithmetic control of the PC and the data transfer control is advantageous in terms of compactness. In the above-mentioned PC, the program is executed in the sequence of signal input, calculation, and calculation result output, but in order to perform coordinated control between PCs, at least once in this series of programs. It is necessary to transfer data and communicate the calculation results to other PCs and the outside. If this one-time data transfer cannot be secured PC
If the mutual cooperation is delayed, the controllability and responsiveness of the entire system will deteriorate.

In order to solve this problem, it is conceivable to speed up data transfer and transfer data twice or three times in one program cycle to ensure reliability. However, as shown above, one processor can In a PC that aims at compactness by performing both arithmetic control and data transfer, the processor is occupied by the data transfer processing, and it becomes difficult to secure the time for arithmetic control. Therefore, it is important to synchronize the operation cycle and the data transfer to ensure one data transfer in one program cycle and to secure the operation control time.

As a conventional serial bus occupancy control method, there is a device that serves as a master, and a method of controlling the bus occupancy right of each slave device connected to the serial bus, or there is no master and a unilateral bus occupancy request is issued. A collision detection method is known in which data is transmitted to the upper side, and when a data collision occurs on the bus, a retry is performed again with a certain time interval.

However, the former method has a problem that data transfer stops when the master stops. The latter method complicates processing such as retries associated with data collision on the bus, and makes it difficult to synchronize the arithmetic control cycle with the data transfer cycle.

An example of performing masterless bus occupancy control by a simple method is described in JP-A-58-161061.

[Problems to be Solved by the Invention]

In the method described in the conventional example (Japanese Patent Laid-Open No. 58-161061), high-speed data transfer is achieved by setting the minimum time required for the next transmission from the end of the previous reception as the setting of the transmission waiting time timer. The main purpose is to
There is a problem that the transmission cycle changes due to the influence of the amount of transmitted data and the absent PC.

An object of the present invention is to avoid a data collision on the bus with a simple configuration without providing a special priority control device, and to provide a constant transmission cycle in which the total of the arithmetic control time of each PC and the data transmission / reception time is synchronized. A masterless serial bus occupancy control method and a control device that enable cyclic data transfer to be performed.

[Means for Solving the Problems]

The present invention, in a system in which a plurality of processing devices are connected to a common bus, is determined by the transmission time interval corresponding to the serial number of each processing device determined at system startup and the number of the processing device that transmitted last time. The transmission waiting time is achieved by using the set timing device in each processing device. Particularly, the masterless serial bus occupancy control method of the present invention is to connect a plurality of processing devices to a common bus and transmit data from the plurality of processing devices to the common bus cyclically. Assigning a number to each, determining the transmission interval time corresponding to the number of processing devices, and the difference between the number of its own processing device and the number of the processing device from which its own processing device last received data, Multiply the transmission interval time and determine the transmission wait time by subtracting the time when the previous data was sent on the serial bus from this product, and after the transmission wait time elapses, its own processing device And a step of transmitting data to the device, and the transmission of the cyclic data is performed by all the processing devices within a certain transmission cycle. Further, the masterless serial bus occupancy control device of the present invention has a plurality of processing devices connected to a common bus, and the plurality of processing devices cyclically transmit data to the common bus. The processing device transmits a memory for storing a processing program and data, a micro processing unit (MPU) for reading and executing the processing program stored in the memory, and an execution result of the MPU to a process target unit, and A process input / output control circuit for receiving information from the process means in the MPU and a serial bus input / output connected to a common bus for transmitting data received from other processing devices to the MPU and transmitting data transmitted from the MPU to the common bus A circuit and a timer that gives the MPU the number of its own processing unit and the transmission interval time between each processing unit; Multiplying the difference between the number of the processing device and the number of the processing device that received the previous data by its own processing device by the transmission interval time, and subtracting the time during which the previous data from the product is transmitted on the serial bus. And a setting device that determines the transmission waiting time according to the above.

[Action]

In addition to transmitting and receiving data at synchronized transmission time intervals, it is necessary for each PC to perform predetermined arithmetic control at high speed and in a cyclic manner. Therefore, all PCs have the same priority, and data collision on the serial bus does not occur. As a means of avoiding and transferring data at fixed transmission time intervals, the time corresponding to the number of the processing device transferred last time and the number of its own processing device is set in the clock device, and this is set as the optimum transmission waiting time. By performing the correction, the correction based on the transfer data amount for performing the transmission at the constant transmission time interval is added, and the above object is achieved.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a PC to which the present invention is applied, and FIG.
An example of a control system using C is shown.

First, the overall configuration will be described with reference to FIG. The PC 1 is a central processing unit (hereinafter CPU) that mainly executes programs.
Abbreviated. ) 2 and a process input / output device (hereinafter abbreviated as PIO) 3 that controls the interface between the process 2) and the process. The CPU 2 periodically inputs the process data such as the limit switch 5 and the oscillator 8 shown in FIG. 2 from the PIO 3, executes the arithmetic operation by this process data and a program stored in advance in the CPU 2, and passes the PIO again, ON / OFF control of the motor 4 and solenoid valve 6 and opening / closing control of the adjusting valve 7 are performed. Further, as shown in FIG. 2, the PC 1 is connected to each other PC by a serial bus 9, and periodically sends out data and a calculation result necessary for the calculation control of each PC so that the PCs can cooperate with each other. Perform arithmetic control while taking.

Next, the configuration of the CPU 2 will be described with reference to FIG. A memory 26 for storing programs, data, and intermediate calculation results, a microprocessing unit (hereinafter abbreviated as MPU) 24 for executing the programs stored in the memory 26,
PIO input / output control circuit 28 for controlling the interface with PIO3 for transmitting the result of executing the program to the process, data input from PIO3, and M
A serial bus output circuit 22 for sending the result of the operation executed by the PU 24 to the serial bus 9, a data of another PC sent on the serial bus 9, a serial bus input circuit 21 for receiving the operation result, and these serial The serial bus input / output control circuit 23 that controls the bus input / output circuit, the PC number of the PC 1, the setting device 27 that sets the transmission interval of the transmission data to the serial bus, the PC number determined by the setting device 27, and the transmission cycle. It comprises a time measuring device 25 for setting a transmission time obtained from a transmission PC number and giving a transmission timing to the MPU 24.

Next, the data transfer control operation of the CPU 2 shown in FIG. 1 will be described. The MPU 24 executes a program stored in the normal-time memory 26 and controls the process equipment connected to the process input / output control circuit 28. During this arithmetic control, the timer device 2 is configured to transmit data at a constant transmission cycle.
5, the transmission timing is given to the MPU 24.
Upon receiving the transmission timing, the MPU 24 suspends the arithmetic control up to that point and starts the data transfer control. First MPU
The data 24 is sent to the serial bus 9 via the serial bus output circuit 22 by setting the output data stored in the memory 26 in the register in the serial bus input / output control circuit 23. The MPU 24 starts arithmetic control again when the transfer of its own CPU is completed. When another PC sends data to the serial bus 9, the send data is unconditionally set in the register in the serial bus input / output control circuit 23 via the serial bus input circuit 21. When the data is set, the serial bus I / O control circuit 23
Notify U24 that there is received data. As a result, the MPU 24 interrupts the arithmetic control so far,
Start receiving data. The MPU 24 transfers the data set in the register in the serial bus input / output control circuit 23 to the memory 26, and repeats the above steps until the reception is completed. After that, the MPU 24 starts arithmetic control again.

FIG. 3 shows an example of the format of the data sent to the serial bus. First, the data sent is the sending PC number (S
A) Subsequently, the transmission data amount (DL) and the transmission data (D
ATA).

4 and 5 show a data transfer processing flow chart of the MPU 24. The MPU 24 in the CPU 2 initializes the device after the reset start. The transmission control initialization process is performed after the reset start. First, the MPU 24 reads the preset own PC number, the transmission time interval t, and the total number of PCs in the setting device 27 and stores them in the memory 26. After that, the MPU 24 sets the maximum waiting time in consideration of the transmission time and the control processing time of another PC in the time measuring device 25 to confirm that there is another PC that is already transferring data on the serial bus. It becomes a state. This corresponds to steps F5, F10 and F15 of the flow chart in FIG. if,
When there is no PC that already transfers data on the serial bus within the maximum waiting time, the timing device 25 gives the MPU a transmission timing after the maximum waiting time, and data transmission is started. The MPU transmits, sets the maximum waiting time again in the clock device 24 after the transmission is completed, and executes arithmetic control. This is repeated thereafter (see steps F15 to F30 in FIG. 4).

When there is a PC that has already started data transfer on the serial bus, the fact that data has been received by the MPU 24 before the transmission timing is given by the timer 25 means that the serial bus input / output by the signal line 100 in FIG. It is output from the control circuit 23 to the MPU, and the MPU starts the reception process. The determination of whether the reception has completed successfully is made with the final reception of the data. This is because an error check code such as CRC is included in the final part of the normal data. When the transmission waiting time is set due to incorrect data when the reception data is abnormal, there is a high possibility that a data collision will occur. Therefore, the transmission waiting time is set to the timekeeping device 25 after the confirmation of the normal reception of the data two times before. The calculated transmission waiting time is used. When the reception data is abnormal, it is determined by the transmission waiting time calculated when the normal data is received two times before.

Since the transmission waiting time is set to the clock device 25 at the end of reception, if the constant waiting time is added after receiving the data as in the conventional case, the transmission cycle also changes with the change in the data amount. In order to make this a constant transmission cycle, correction is made by the amount of data previously received from another PC during the transmission waiting time. FIG. 6 shows an example of setting the transmission waiting time T. The transmission waiting time T is determined by the own PC number set by the setting circuit 27 in FIG. 1, the total number of PCs, the transmission time interval t, the transmission PC number obtained from the received data, and the data amount. Own P
When the C number is larger than the number of the PC that transmitted the data last time, the transmission waiting time T is obtained by T = (own PC number−previous transmission PC number) × t−τ _i . Here, τ _i is the time during which the previous data is sent out on the serial bus, and is the correction time for performing data transfer at the constant transmission cycle T _t . Further, t is a transmission time interval at which any PC starts transmission. τ _i is obtained by τ _i = (transmission data amount) ÷ (transmission rate). Note that it is also possible to simply make the average of τ _i τ and uniformly correct the transmission waiting time by τ. However, in this case, the transmission cycle T _t may change slightly.

Next, when the own PC number is smaller than the received PC number, the transmission waiting time T is obtained by T = (total number of PCs + own PC number−received PC number) × t−τ _i . As a result, the transmission waiting time T is always a positive number. The transmission waiting time T after the transmission of the own PC is set by the corrected maximum waiting time T = total number of PCs × t−τ _i .

The transmission waiting time obtained by the above procedure is shown in FIG.
After setting to, the PC removal check shown in steps F61 to F63 in FIG. 5 is performed.

Each PC remembers the last received PC number and this time received PC
Make a comparison with the number. If the difference between the PC number of the previous reception and the current reception is other than 1, P between the previous reception and the current reception
This indicates that C is missing. This may be because the PC that I have used so far goes down and suddenly stops transmitting. The missing PC numbers are the currently received PC number and the previously received PC number.
The number can be obtained by back-calculating the number and its difference. By knowing the number of the missing PC, it is possible to stop the process control or concentrate on the process control of the own PC during the transmission time interval corresponding to the missing PC.

Next, the received data is stored in the work area on the memory 26 in FIG. As a result, the reception process is completed, the transmission waiting state is entered, and the suspended arithmetic control is restarted (steps F40 to F65 in FIG. 4). The processing flow chart in the PC has been described above. Next, the overall control system will be described below with reference to FIG. As a precondition, it is assumed that PC # 2 is stopped due to a power failure.

Focusing on PC # 3, PC # is in execution of arithmetic control PC # 0
(3-0) × t−τ ₀ = 3t−τ after the normal reception determination is started after the data is received from
Set ₀ to enter the transmission wait state and restart arithmetic control. Then, after the lapse of t-τ ₀ time, PC # 1 starts transmission and PC # 3 starts data reception processing again. The transmission waiting time T is set to T = (3-1) × t−τ _I = in the time measuring device 25 after the normal reception of the data.
It is updated to 2t-τ ₁ and the transmission waiting state is entered, and the arithmetic control is restarted. 2t since PC # 2 is stopped due to a power failure
After the lapse of −τ ₁ hour, the PC # 3 receives the transmission timing from the timing device 25 and starts the transmission processing. The maximum waiting time is set in the time measuring device 25 after the transmission.

As described above, the transmission cycle becomes constant by adding the correction of the other PC transmission time τ to the transmission waiting time. The transmission cycle is determined by the total number of PCs and the transmission interval t, and the transmission cycle T
_t is constant such that T _t = total number of PCs × t. The total number of PCs and the transmission time interval t can be flexibly set by the setting device 27, so that a transmission system suitable for any system can be configured. The following system configuration is given as an example. The transmission system consists of 5 PCs,
If you want to perform the transmission and control in 0.2 seconds transmission period _{T t,} the total number of PC 5, easily set transmission period _{T t} of 0.2 seconds by the 0.04 second transmission time interval t can do. Incidentally, the control is performed so that the transmission is ambiguous, and the control is performed once in one transmission cycle. If three PCs may be added to this system in the future, the total number of PCs is set to 10 and the transmission interval t is set to 0.02 seconds with a margin from the beginning. As a result, even when the total number of PCs is 10 and additional PCs are added, the PCs can be added without changing the settings of the other PCs and while keeping the transmission cycle constant.

〔The invention's effect〕

According to the present invention, the sending PC in the sending data format
Number, transmission time interval set by the setting device, and
The optimum transmission wait time is calculated from the amount of transmission data in the transmission data format, and is set in the clock device of each PC to enable serial bus occupation control without data collision on the bus at a constant transmission cycle corresponding to the system. There is an effect to be realized.

[Brief description of drawings]

FIG. 1 is an internal configuration diagram of a CPU, and FIG. 2 is a PC of the present invention.
An example of system configuration according to FIG. 3, FIG. 3 is a data format on the serial bus, FIGS. 4 and 5 are transmission processing flows in the control device, FIG. 6 is a method for determining a transmission waiting time, and FIG. 7 is a serial bus. And the processing time chart of each PC is shown. 1 ... PC, 2 ... CPU, 9 ... Serial bus, 24 ... MP
U, 25 ... Clock device.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Junju Saito 5-2-1 Omika-cho, Hitachi City, Ibaraki Prefecture Hitachi Ltd. Omika Plant, Ltd. (72) Inventor Yasuhiro Asahi 5 Omika-cho, Hitachi City, Ibaraki Prefecture 2-1-1, Hitachi Ltd. Omika Plant (72) Inventor Kazuhiko Shimoyama 5-2-1 Omika-cho, Hitachi City, Ibaraki Hitachi Ltd. Omika Plant (56) References JP-A-56- 54145 (JP, A) JP 59-167729 (JP, A)

Claims (1)

[Claims] 1. A masterless serial bus occupancy control method in which a plurality of processing devices are connected to a common bus, data is cyclically transmitted from one processing device to the common bus, and the data is received by another processing device. Assigning a number to each of the devices, determining a transmission interval time corresponding to the number of the processing devices, and the number of its own processing device and the number of the processing device the own processing device previously received data. Determining the transmission waiting time by multiplying the difference by the transmission interval time, and subtracting from this product the time during which previous data smaller than the transmission interval time is being sent out on the serial bus; and the transmission waiting time. After the lapse of time, the own processing device transmits data to the common bus, and the cyclic transmission of data performed by all processing devices is performed within a certain transmission cycle. Master-less serial bus occupation control method comprising the door.