JPH0648581B2 - Data detection device for digital signal reproducing device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a digital signal reproducing apparatus such as a PCM magnetic recording / reproducing apparatus, and more particularly, in the reproducing apparatus, data detection timing is determined from quantized reproduced data. The present invention also relates to a data detection device for performing data detection that follows changes in tape running.

[Conventional technology]

FIG. 4 shows an example of a conventional digital signal reproducing apparatus. In the figure, 1 is a reproducing head for converting a signal recorded on a magnetic tape or the like into an electric signal, and 2 is a reproducing head.
Is a reproduction amplifier for amplifying a weak electric signal from the head 1, 3 is a waveform equalizing circuit for compensating for a high frequency component signal lacking in reproduction characteristics, and 4 is a binary analog signal for the reproduced analog signal. Data detection circuit for converting to a digital signal, 5
Is a PLL circuit that generates a clock that follows tape running fluctuations (jitter). In the PLL circuit 5, 6 is a phase comparison circuit that finds the phase difference between the reproduced data and the PLL clock, and 7 is a high frequency band due to waveform interference or the like. Is a low-pass filter that removes the phase fluctuation noise of the VCO. Reference numeral 9 is a flip-flop circuit for outputting reproduction data in synchronization with the reproduction clock.

Next, the operation will be described. The signal recorded on the magnetic tape medium is converted into an electric signal by the reproducing head 1. This reproduced electric signal is usually several 100 μV to several mV
However, the reproduced signal is amplified to an electric signal of about 1 V by the reproduction amplifier 2, but the reproduced signal has a high frequency signal component lost due to spacing loss of the reproduction head. Waveform distortion occurs in the component signals, and accurate zero-cross transmission of data is not performed. The waveform equalization circuit 3 compensates for this lacking high-frequency component signal, and compensates for the high-frequency characteristics in a linear phase. Usually, a transversal filter is used in this circuit, and as the circuit configuration, for example, there is one in which an active filter using a differential amplifier and a capacitor and an inductor is connected in cascade. In addition, delay lines and BBD (Bucke
t Brigade Device).

Accurate zero-cross information of the digital signal is transmitted by the waveform equalization circuit 3, and this is converted into a binary digital signal by the data detection circuit 4 having a zero-cross comparator as a main circuit. This digital signal fluctuates in the time axis direction due to tape running fluctuation (jitter), and therefore it is impossible to perform data transmission by a reference clock such as crystal oscillation.

The PLL circuit 5 is a circuit for generating a reproduction clock that follows the jitter from the reproduction data, and the reproduction data must be transmitted to the next stage by this reproduction clock. Reference numeral 9 is a flip-flop circuit for that purpose, and the detected data is transmitted to the next stage after being synchronized with the reproduction clock. The PLL circuit 5 removes high-frequency phase fluctuation noise due to waveform interference or the like from the signal output from the phase comparison circuit 6 for obtaining the phase difference between the reproduction data and the reproduction clock, and extracts only the jitter component. And a low pass filter 7 and a VCO 8 that generates a clock that follows the jitter from the electric signal input from the low pass filter 7, and the phase comparison circuit 6
As an example, an exclusive OR circuit or a sawtooth wave is generated by charging / discharging C and R, and this is sample-held using a MOS switch and a differential amplifier to reproduce the phase difference between the reproduced data and the reproduced clock. A sawtooth wave phase comparator or the like is used. The low-pass filter 7 is generally composed of C and R and a differential amplifier.

[Problems to be solved by the invention]

The conventional digital signal reproducing device is configured as described above, and an analog circuit is applied to most circuits of the device including the PLL circuit, which is disadvantageous in realizing an IC. This is because in the case of realizing an IC, a large capacity capacitor or inductance cannot be built in the IC, which causes a problem that the number of peripheral circuit parts increases.

The present invention has been made in order to solve the above-mentioned problems, and it is possible to combine the circuits after the reproduction amplifier into a digital IC and reduce the number of peripheral parts. The purpose is to provide.

[Means for solving problems]

A data detecting device of a digital signal reproducing device according to the present invention comprises a phase detecting means for detecting a data detecting phase following jitter from input sampling data by a digital signal processing, a transmission clock for transmitting reproduced data and the sampling And a clock generator for generating a sampling clock for controlling the phase detection means so that when the data detection phase is out of the predetermined range, the phase detection means is controlled to be a value within the predetermined range. Phase clock control means for controlling the clock generator so as to increase or decrease the transmission clock and the data detection period, input sampling data and the data detection phase from the phase detection means are input and synchronized with the data transmission clock by digital operation. Data for data detection It is provided with a circuit and out.

[Action]

According to the present invention, since the phase information and the reproduction data necessary for detecting the reproduction data are all obtained by digital signal processing, it is possible to easily achieve the IC and reduce the peripheral parts.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. First
The figure shows a data detecting apparatus of a digital signal reproducing apparatus according to an embodiment of the present invention. In the figure, 10 is a first register circuit for accumulating one piece of quantized reproduction data, and 11 is a continuous two-sample reproduction. A sampling point phase detection circuit for detecting how much the sampling point at which sampling is performed is deviated from the data detection point at which the reproduction data should be detected by digital operation from the data, 12 is continuous 2 sample reproduction data A zero-crossing detection circuit for detecting the presence or absence of a zero-crossing point of reproduced data by more digital calculation, 22 is a switch controlled by the zero-crossing detection circuit 12, 13 is a sampling point phase input via the switch 22, and compensates in the phase fluctuation direction. Compensation circuit, 14 When timing other than during Rokurosu detecting a second register circuit for cyclically sampling point phase value, which is constituted by a shift register. Reference numeral 15 is a digital filter circuit for removing sampling point phase fluctuation noise of high frequency components due to waveform interference, 16, 17, 18, 15
a to 15d are constituent elements of the digital filter circuit 15, 16 is a multiplier that determines the gain, 17 is a third register circuit for circulating data in the filter circuit 15, and 18 is the band thereof. Multiplier to determine,
Reference numerals 15a to 15d are digital adders. Then, the phase detection means 30 for detecting the data detection phase following the jitter from the input sampling data by the digital signal processing is constituted by the above 10 to 15 and 22.

Further, 19 is a data detection phase control circuit for making the data detection phase which is constituted by a digital circuit and is within n equal parts of the data detection period T as a detection width, and 20 is a data detection phase control circuit 19. A clock generator for generating a data transmission clock, a clock for determining the latch timing of the register circuit 14 and the register circuit 17, and a sampling clock for an A / D converter (not shown) on the basis of the output. Reference numeral 31 denotes the data detection phase control circuit 19. Is a phase clock control means for controlling the phase detection means 30 so that the data detection phase falls within a predetermined range when the data detection phase is out of the predetermined range, and data transmission for transmitting reproduction data. To increase or decrease the clock and data detection period And controls the lock generator 20.

Reference numeral 21 is a data detection circuit for performing data detection in synchronism with a data transmission clock by digital calculation based on continuous 2-sample reproduction data from the register circuit 10 and the data detection phase. Reference numeral 23 is a digital adder.

FIG. 2 shows the quantized reproduction data input to the circuit of this embodiment.

FIG. 3 shows the state of the phase information and the processing clock at each point in this embodiment. In addition, in FIG. 3, (a) to (e)
Shows the states of points a to e in FIG.

Next, the operation will be described. The weak reproduction output reproduced from the head is amplified to an electric signal of about 1V by the reproduction amplifier, then quantized by A / D conversion, and further FIR (Fin
ITE Impulse Response) A method for equalizing the waveform by digital signal processing using a filter has already been disclosed in Japanese Patent Laid-Open No.
This embodiment is a data detecting device for converting reproduced data obtained by the above method into binary digital data.

The reproduction signal input to the first register circuit 10 is A / D
It is an m-bit quantized signal which is sampled at every data detection cycle T by the converter and waveform-equalized by the FIR filter under the condition that the first Nyquist criterion is satisfied. Further, as shown in FIG. 2, this signal is such that the zero cross points of the reproduced data are given by linear approximation between the sampling points. Now, in two consecutive reproduction data, the previous reproduction data is S1 and the subsequent reproduction data is S2. These two reproduction data S1,
S2 is data obtained by sampling in the data detection period T, and the phase shift between the sampling point and the data detection point is arbitrary. Under these conditions, the input terminal of the first register circuit 10 has the signal S2 and the output terminal thereof has the signal S1. A sampling point phase detection circuit 11 is provided to detect how much the sampling point of the signal S2 deviates from the signals S1 and S2 with respect to the data detection point. However, when the data detection point is T and the data detection point is sampled in 360 equal parts,
It is the center position, and the reproduction data here is to be detected, and this is set to 0 ° in this description. Further, in FIG. 2, when the signal S2 is located on the left side of the data detection point, the phase is −phase and −180 ° at the left end in the data detection period T. On the contrary, when it is located on the right side, the phase is + phase, and it becomes + 180 ° at the right end in the cycle T.

As can be understood from FIG. 2, the sampling point phase can be detected only when the signals S1 and S2 have mutually opposite polarities.
Only when × S2 <0, the switch 22 shown in FIG. 1 is switched to the − direction, and new phase information is supplied to the compensation circuit 13.
Is output to. At this time, the sampling point phase φ (t2) output from the phase detection circuit 11 is obtained by linear approximation.
It is given by equation (1).

The sampling point phase φ obtained in this way
(T2) is −180 ° <φ (t
2) It becomes <+ 180 °.

Here, if the sampling point phase value obtained from the signals S1 and S2 does not have an equalization error due to waveform interference or a zero cross point detection error due to linear approximation, a data transmission clock should be generated using this phase information. Is possible.

Here, as shown in FIG. 3, the state where the sampling point phase shifts in the − direction and becomes −180 ° or more is because the tape speed is slower than the steady state.
When the temperature is higher than 0 °, the reproduced data is increased by one data detection. Therefore, under the conditions, one reproduction data is detected and reproduction data is removed, and the sampling point phase is set to be within the period T divided into 360 equal parts. Therefore, 360 ° may be added to this. On the contrary, the state where the sampling point phase shifts in the + direction and becomes + 180 ° or more is because the tape speed is faster than the steady state, and at + 180 ° or more, the reproduction data disappears for one data detection. Therefore, if this condition is 1
Data is detected twice during the playback data cycle, and the sampling point phase value is -36
Add 0 °. As described above, when there is no error in the sampling point phase value, the data transmission clock can be immediately generated by correcting the value and increasing or decreasing the clock as described above, if necessary.

However, in reality, phase fluctuation noise occurs due to the waveform equalization error and the linear approximation error, and the phase detection output as shown in FIG.
Express as). These noises are frequency components higher than the jitter component, and the digital filter circuit 15
Can be removed at. The digital filter circuit 15 used in this embodiment is an IIR (Infinite Impulse).
Response) type filter, which obtains each coefficient that determines its frequency characteristic using the bilinear transformation method.

In general, the cutoff frequency of this filter is often expressed as a ratio with the transmission clock, and is set to about 1% of the transmission clock frequency. Further, in this embodiment, the digital filter circuit 15 needs to output with a gain of 1, the multiplier 16 for determining the gain is given a coefficient therefor, and the frequency characteristic of the multiplier 18 for determining the band. It is determined by the coefficient given to.

The third register circuit 17 is a digital filter circuit 15
It is for circulating the data input to the inside of the filter circuit 15. FIG. 3 (c) shows the phase information output from the digital filter circuit 15. However,
Here, the case where the band of the filter is 1% of the transmission clock is shown. It should be noted that the IIR filter used in this embodiment, like the CR filter, has a phase variation in its output due to frequency components. Therefore, the output phase lags the input with respect to the relatively fast jitter component. That is, when comparing (a) and (c) of FIG. 3, when the phase data c takes a value in the vicinity of −180 °, the phase data a is already distributed in the vicinity of + 180 °. is there. Therefore, when the phase data a is input to the filter circuit 15 as it is, it becomes a noise factor as a factor of abrupt phase fluctuation. To prevent this, a compensation circuit 13 and a second register circuit 14 are provided. Further, the phase c shown in FIG. 3 (c) is near −180 °, and the phase a is already distributed near + 180 °, because the phase a exceeds −180 ° and advances further in the − phase direction. It is nothing but a thing. Therefore, the phase a output from the sampling point phase detection circuit 11
Is compensated by the phase c output from the digital filter circuit 15. That is, the compensation circuit 13
The phase information a and c are input to and the phase information compensated under the condition of the equation (2) is output.

Further, the new phase a is input via the switch 22 only when the reproduced data crosses zero, and the second phase a is cycled so that the digital filter processing is performed in the reproduced data detection period T. Register circuit 14 is provided.

With the above configuration, only the phase fluctuation at the sampling point due to the jitter is extracted from the digital filter circuit 15.

The sampling point phase obtained in this way is
It is used as a data detection phase for performing data detection. This data detection phase needs to be within ± 180 ° when the data detection period is divided into 360 equal parts as described above. The data detection phase control circuit 19 performs this processing.

Here, in FIG. 3 (c), the state of t1 is when the sampling point phase is −180 ° or more.
This state occurs because the tape speed is slow and the reproduction data is oversampled as described above. Therefore, the data detection phase control circuit 19 acts on the clock generator 20 so as to generate a clock for stopping the data detection, as shown in FIG. This operation corresponds to advancing the phase by 360 ° with respect to the sampling point phase, and the data detection phase control circuit 19 performs an operation of adding 360 ° to the sampling point phase of the phase c, and , 360 ° is also added to the data accumulated in the third register circuits 14 and 17 to compensate for the advance of the phase.

On the other hand, in the state of t2, the sampling point phase is +180
It is when the condition is above °. This state occurs because the tape speed is high and the sampling rate is lower than the reproduction data rate as described above. Therefore, the data detection phase control circuit 19 instructs the clock generator 20 as shown in FIG.
It works to generate a clock of T / 2 cycle in order to supplement the data detection by one sampling. This operation corresponds to delaying the phase by 360 ° with respect to the sampling point phase, and the data detection phase control circuit 1
9 is -360 with respect to the sampling point phase of phase c
And the second and third register circuits 1
-360 ° is also added to the data accumulated in 4 and 17 to compensate for the delayed phase. As a result, the data detection phase given to the data detection circuit 21 is given by the equation (3) at the timing of FIG. 3 (e).

From the above description, it can be understood that the data detection phase is within the range of ± 180 °, the high frequency phase fluctuation noise due to the waveform interference and the linear approximation is removed, and the information following only the jitter is obtained.

Next, the operation of the data detection circuit 21 will be described. The signals S1 and S2 and the data detection phase information from the digital filter circuit 15 are input to the data detection circuit 21,
Binary digital data is detected by digital operation in synchronization with the data transmission clock output from the clock generator 20 shown in FIG. 3 (d). This calculation is to obtain the reproduction output level at the data detection point (phase 0 ° point) from the signals S1 and S2 and the data detection phase, and the output level is given by the following equation.

Detection data = S1 − ((360 ° −data detection phase) × (S2-S1)) / 360 ° (however S1 <S2) = S2− (360 ° −data detection phase) / 360 ° (however S1 = S2) = S2 + ((360 ° -data detection phase) x (-(S2-S1)) / 360 ° (however, S1 <S2) If the result of the above formula is positive, it is "1", and if it is negative, it is "0". ", The binary digital data can be detected.

As described above, according to the present embodiment, since the posture data that is quantized and input is processed only by digital signal processing to detect data, electromagnetic conversion up to data detection including the waveform equalization circuit is performed. The system can be compacted by a digital IC. As a result, the entire digital signal reproducing device becomes compact, the number of parts can be reduced, and an inexpensive device can be provided.

In the above embodiment, the state of the phase b is shown by the equation (2), but it can be approximated by the following equation (4), and the same effect as that of the above embodiment can be obtained.

[Effects of the Invention] As described above, according to the data detecting device of the digital signal reproducing apparatus of the present invention, the quantized reproduction data can be detected only by the digital signal processing. There is an effect that the electromagnetic conversion system including the digitizing circuit up to the data detection can be integrated into a compact one by the digital IC.

[Brief description of drawings]

1 is a block diagram of a data detection device of a digital signal processing device according to an embodiment of the present invention, FIG. 2 is a conceptual diagram showing a state of an input signal of the device of FIG. 1, and FIG. 3 is a diagram of FIG. FIG. 4 is a block diagram of a conventional digital signal reproducing apparatus showing the signals of respective parts. In the figure, 10 is a first register circuit, 11 is a sampling point phase detection circuit, 12 is a zero cross detection circuit, 13 is a compensation circuit, 14 is a second register circuit, 15
Is a digital filter circuit, 17 is a third register circuit, 19 is a data detection phase control circuit, 20 is a clock generator, 21 is a data detection circuit, 30 is a phase detection means, and 31 is a phase clock control means.

Claims (3)

[Claims] 1. A data detection device applied to a digital signal reproduction device for reproducing an analog signal from digital data obtained by sampling a signal reproduced from a head at a data detection period of a period T and quantizing it into m bits. A phase detection means for detecting a data detection phase that follows jitter from input sampling data by digital signal processing, a data transmission clock for transmitting reproduction data and a clock generation for generating a sampling clock for the sampling. And a digital circuit, which controls the phase detecting means so that the detection phase falls within the predetermined range when the data detection phase is out of the predetermined range, and the clock cycle of the data transmission clock and the data detection cycle. Control the clock generator to increase or decrease Phase clock control means for inputting the input sampling data and the data detection phase, and a data detection circuit for detecting binary reproduction data in synchronization with the data transmission clock by digital operation. Data detection device for digital signal reproducing device. 2. The phase detecting means stores a first register circuit for accumulating sampling data for one data, a sampling point connected to the first register circuit for sampling and reproduction data at that time. A sampling point phase detection circuit for obtaining a phase difference from a data detection point to be detected by a digital operation as a phase difference within the data detection period T with a detection width divided into n equal parts, and the first register circuit. A zero-cross detection circuit that is connected and detects the presence or absence of zero-cross of the sampling data by digital operation, and new phase information is input from the sampling-point phase detection circuit only when the zero-cross is detected, and the sampling point is compared with the data detection phase. Compensation for compensating the phase in the phase fluctuation direction A circuit, a second register circuit for circulating the compensated data except when the zero cross is detected, and a sampling point phase fluctuation noise of a high frequency component connected to the compensation circuit to remove the data detection phase. The data detecting device of the digital signal reproducing device according to claim 1, further comprising a digital filter circuit for outputting. 3. The phase clock control means adds -n or + n to the data detection phase when the data detection phase is + (n / 2) or more or-(n / 2) or less, and -N or + n is added to the output of the second register circuit and the output of the third register circuit for circulating data in the digital filter circuit,
The clock period of the data transmission clock and the data detection period are T / 2 when the data detection phase is + (n / 2) or more, and are 2T when the data detection phase is − (n / 2) or less. The data detection device of the digital signal reproducing device according to claim 2, wherein the data detection device controls the period and the data detection period.